DESC:TITLE
A SYSTEM AND METHOD FOR DATA COMMUNICATION IN PRESENCE OF ELECTROMAGNETIC INTERFERENCE
BACKGROUND
A. Technical Field:
[001] The present disclosure relates to a method and system for data communication, more particularly the disclosure relates to real time seamless data transmission and reception in the presence of electromagnetic interference.

B. Background Art:
[002] The rapid growth of the communication industry and fast paced industrial activities have resulted in a general requirement of fast and accurate data communication that is data transmission and reception in the highly EMI induced environment.
[003] The existing method and solutions available are either manual solutions where a traditional EMI shielding techniques are engaged or in case of automated solutions, they have not currently been able to mitigate the effect of EMI.
[004] EMI is the major cause of communication failure in the wireline transceiver systems. Wireline transceiver systems are used to transmit the data at high data rate (10-400 Gbps) over potentially long PCB traces or coaxial cables. The wireline communication channel acts as an undesirable parasitic antenna for the externally injected electromagnetic interference (EMI). The EMI induces common-mode voltages and currents on the transmission line. Due to practical non-linearity of the circuits, this induced common-mode voltages and currents are converted into differential noise and superimposed on the desired differential signal and corrupts the data. In case of high EMI level, it can move the circuits out of their optimal operating regions or in a worse case may completely debias the circuit.
[005] Traditional EMI shielding technique such as large passive filters and EMI shielding are costly, bulky, and in general more impractical for state-of-art integration technologies. Recent works are focused on finding an on-chip solution to mitigate the effect of EMI. PAM4 transceiver is used to achieve 400 Gbps and higher bitrates and is currently the Ethernet standard for chip-to-chip and backplane communication. EMI can be one of the major causes of communication failure in this case.
[006] For the reasons stated above, which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art for a system and method thereof that enables fast and accurate data communication that is data transmission and reception in the highly EMI induced environment, for example data transmission and reception in the presence of EMI for backplane and chip-to-chip communication.

SUMMARY
[007] In an aspect of the present disclosure, a data communication system immune to electromagnetic interference is disclosed. The data transmission system comprises a four-level pulse amplitude modulation (PAM4) transmitter having an input and an output (OUTP, OUTN) connected to a transmission line, and the PAM4 transmitter comprises a first processing section and a second processing section. The system comprises a plurality of modified electrostatic discharge (ESD) protection circuits given to the output (OUTP, OUTN) and to a plurality of different voltage levels (V1, V2, V3, V4), an input level shifter provided between the first processing section and the second processing section, and a logic circuit, a four-level pulse amplitude modulation (PAM4) receiver connected to the transmission line, the PAM4 receiver comprises a front end differential amplifier. The low-level EMI of the transmission line is mitigated by the Input level shifter (ILS) and high level EMI is mitigated by the plurality of modified ESD protection circuits (M1_ESD and M2_ESD).

BRIEF DESCRIPTION OF THE DRAWINGS
[008] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[009] Figure 1 illustrates a circuit diagram for the traditional PAM4 transmitter.
[0010] Figure 2 illustrates a circuit diagram for EMI immune transmitter according to one of the embodiments of the present invention.
[0011] Figure 3 illustrates block diagram for the traditional PAM4 receiver circuit.
[0012] Figure 4 illustrates circuit diagram for the traditional front-end for the PAM4 receiver.
[0013] Figure 5 illustrates circuit diagram for the proposed front-end for the PAM4 receiver according to one of the embodiments of the present invention.
[0014] Figure 6 illustrates circuit diagram for the slicer.
[0015] Figure 7 illustrates circuit diagram for the differential DFF.
[0016] Figure 8 illustrates circuit diagram for a thermometer to binary decoder.
[0017] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present invention. Similarly, it will be appreciated that any flowcharts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION OF THE INVENTION
[0018] The embodiments herein provide a method and system for data communication, more particularly the disclosure relates to real time seamless data transmission and reception in the presence of electromagnetic interference. The system and method thereof of present invention enables fast and accurate data communication that is data transmission and reception in the highly EMI induced environment, for example data transmission and reception in the presence of EMI for backplane and chip-to-chip communication. Further the embodiments may be easily implemented in high speed communication lines and communication management circuits. Embodiments may also be implemented as one or more applications performed by stand alone or embedded systems.
[0019] The systems and methods described herein are explained using examples with specific details for better understanding. However, the disclosed embodiments can be worked on by a person skilled in the art without the use of these specific details.
[0020] Throughout this application, with respect to all reasonable derivatives of such terms, and unless otherwise specified (and/or unless the particular context clearly dictates otherwise), each usage of:
“a” or “an” is meant to read as “at least one.”
“the” is meant to be read as “the at least one.”
References in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[0021] Hereinafter, embodiments will be described in detail. For clarity of the description, known constructions and functions will be omitted.
[0022] Parts of the description may be presented in terms of operations performed by at least one electrical / electronic circuit, a computer system, using terms such as data, state, link, fault, packet, and the like, consistent with the manner commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. As is well understood by those skilled in the art, these quantities take the form of data stored/transferred in the form of non-transitory, computer-readable electrical, magnetic, or optical signals capable of being stored, transferred, combined, and otherwise manipulated through mechanical and electrical components of the circuits, systems, computer system; and the term circuits includes general purpose as well as special purposed electrical/electronic transceiver circuits, signal processing circuits and systems, and the term computer system includes general purpose as well as special purpose data processing machines, switches, and the like, that are standalone, adjunct or embedded.
[0023] According to an embodiment, a system and method thereof of present invention presents an EMI immune PAM4 transceiver system and method thereof, that provides an on-chip solution to mitigate the effect of EMI for wireline communication channels.
[0024] The system and method thereof according to an embodiment of the present invention i.e. EMI immune PAM4 transceiver have a wide commercial application where high-speed interconnects are required, such as data centres automobiles, healthcare, and avionics. Data centres need to process data in gigabytes per second and at even higher speeds, which includes transmitting the data over backplane at higher data rates in the presence of external interference. In aircraft, data needs to be transmitted at higher rate from various sensors to the processing unit, but due to increase in onboard circuitry, the effect of EMI ca be devastating. The EMI effects can be reduced by using EMI immune transceivers. Similarly, telesurgery and other automation industry also require high-speed EMI immune interconnects. Eventually, EMI immune PAM4 transceiver may be used in the circuits which need high-speed, low latency wireline interconnects in an EMI environment.
[0025] Figure 1 illustrates a circuit diagram for the traditional PAM4 transmitter. As depicted in the figure 1, the output of the transmitter is connected to the transmission line which is susceptible to EMI. The PAM4 transmitter is connected to a transmission line which is terminated to a resistance R to VDD at the receiver’s end. The BJTs Q1-Q4 acts as a switch and steer the currents from the constant current sources IMSB and ILSB to the output where they are added up to provide desired PAM4 voltage levels with the help of load resistance R. The mathematical expressions for the four voltage levels for different values of input MSB and LSB are given by




The effects of EMI on the traditional PAM4 transmitter is divided into two parts that are low-level EMI when the circuit moves out of the operating region and high-level EMI when the EMI is high enough to turn on the ESD diodes. When a high-level EMI is induced on the transmission line, it will turn on the ESD protection diodes and both OUTP and OUTN will clamp to VDD or GND for the traditional PAM4 transmitter. This will cause a complete loss of differential data.
[0026] In an implementation of the present invention, the EMI effects are mitigated using the Input level shifter (ILS) for low-level EMI and modified ESD protection circuits (M1_ESD and M2_ESD) for high-level EMI. The PAM4 transmitter according to an implementation of the present invention is illustrated in figure 2.
[0027] Figure 2 illustrates a four-level pulse amplitude modulation (PAM4) transmitter immune to EMI according to one of the embodiments of the present invention. The four-level pulse amplitude modulation (PAM4) transmitter (200) has an input and an output (OUTP, OUTN) connected to a transmission line (100). A four-level pulse amplitude modulation (PAM4) receiver (300) is connected to the transmission line (100) according to one of the embodiments of the present invention and the PAM4 receiver is illustrated in figure 3.
[0028] The PAM4 transmitter (200) comprises a most significant bit (MSB) processing section (210) and a least significant bit (LSB) processing section as similar to the traditional transmitter shown in figure 1. The MSB processing section (210) comprises a first constant current source (IMSB) and two Bipolar Junction Transistors (Q1, Q2) connected with the first constant current source (IMSB), and the LSB processing section (220) comprises a second constant current source (ILSB) and two Bipolar Junctions Transistors (Q3, Q4) connected with the second constant current source (ILSB).
[0029] The PAM4 transmitter (200) further comprises a plurality of modified electrostatic discharge (ESD) protection circuits (230) given to the output (OUTP, OUTN). The plurality of modified ESD protection circuits includes at least two modified ESD protection circuits (M1_ESD and M2_ESD). Each modified ESD protection circuit comprises a Diode and a plurality of MOS transistors (a, b, c, d). The plurality of MOS transistors are given and to a plurality of different voltage levels (V1, V2, V3, V4).
[0030] The EMI induced on the transmission line change the collector voltages of BJTs Q1-Q4 forcing them to move out of the operating region.
[0031] In an implementation of the present invention, an ILS circuit (240) as shown in the figure 2 is used to reduce the common-mode level of input that in turn increases the range for which collector voltage can change keeping the BJTs in the operating region. The base voltage is reduced by , this will increase the collector range by . This will make sure the circuit remains in the operating region in case of EMI insertion.
[0032] In yet another implementation of the present invention the modified ESD protection circuits (M1_ESD and M2_ESD) as shown in figure 2 are used to maintain the minimum eye-opening required according to the standard IEEE802.3bs.
[0033] According to an implementation of the present invention the modified ESD protection circuits (M1_ESD and M2_ESD) as shown in figure 2, intentionally clamp the OUTP and OUTN to different voltage levels (V1, V2, V3 AND V4) with the help of MOS switches which are controlled by input MSB and LSB. This guarantees the minimum eye-opening required according to the standard IEEE802.3bs.
[0034] The input level shifter (ILS) (240) provided between the MSB section (210) and the LSB section (220), and a logic circuit (250) as shown in figure 2. The output of the logic circuit is given to the plurality of MOS transistors (a, b, c, d) of the plurality of modified ESD protection circuits (230).
[0035] Figure 3 illustrates block diagram for the traditional PAM4 receiver circuit. The traditional PAM4 receiver (300) as shown in figure 3 consists of a front-end differential amplifier (310), a slicer (320), a D-flipflop (DFF) stage (330) provided with a buffer (334), and a thermometer-to-binary decoder (340).
[0036] Further, figure 4 illustrates circuit diagram for the traditional front-end for the PAM4 receiver. The front-end differential amplifier as shown in figure 4 is the circuit which is connected to the differential transmission line and thus make it most susceptible to the EMI which is induced on the transmission line. The disturbance which manifests as a common-mode EMI can be classified into two categories depending upon the common-mode range of the front-end differential amplifier. The categories are low-level EMI and high-level EMI. For a low-level EMI less than the input common-mode range (ICMR) (assuming the input common-mode is centred around the average of ICMR), because of the front end differential amplifier is operating in the linear region, no significant harmonic signals are produced, which makes the effect of EMI less significant. However, when a high-level EMI is applied, the input transistors will go out of saturation, and, subsequently, because of the non-linear operation, front-end differential amplifier outputs will saturate to either VDD or GND, thereby, eventually reducing the eye height.
[0037] The Reduction in eye height as an effect of induced EMI is mainly because of the limited ICMR of the front-end NMOS based differential amplifier.
[0038] In an implementation of the present invention to improve the ICMR of the amplifier, a dual, that is, an NMOS based and a PMOS based input differential amplifiers can be used.
[0039] Figure 5 illustrates circuit diagram for the proposed front-end for the PAM4 receiver according to implementation of one of the embodiments of the present invention. The proposed front-end is configured to work for the high common-mode range. The proposed front-end comprises a traditional differential amplifier (510) comprising NMOS transistors as shown in figure 4, called as NMOS part, and an additional differential amplifier (520) comprising PMOS transistors, called as PMOS part, and thus forming an increased common-mode range differential amplifier (500) as shown in figure 5. The figure 5 shows the use of a dual, that is, an NMOS based and a PMOS based input differential amplifiers to improve the ICMR of the amplifier. This approach increases the common-mode range of the input stage and linearity, thereby improving the EMI-immunity.
[0040] Figure 6 illustrates circuit diagram for the slicer.
[0041] Figure 7 illustrates circuit diagram for the differential DFF.
[0042] Figure 8 illustrates circuit diagram for a thermometer to binary decoder.
[0043] According to implementation of one of the embodiments the circuits depicted in figure 2 constitutes the PAM4 transmitter of the system of the present invention and implements the method there of according to present invention.
[0044] According to implementation of one of the embodiments the circuits depicted in figure 5 constitutes the frontend differential amplifier for the PAM4 receiver of the system of the present invention and implements the method there of according to present invention.
[0045] According to implementation of one of the embodiments the circuits depicted in figure 5 along with circuits illustrated in figure 6, figure 7, and figure 8 constitutes the PAM4 receiver of the system of the present invention and implements the method there of according to present invention.
[0046] According to implementation of one of the embodiments the circuits depicted in figure 2, and figure 5 along with circuits illustrated in figure 6, figure 7, and figure 8 constitutes the PAM4 transceiver system of the present invention and implements the method there of according to present invention.
[0047] According to implementation of one of the embodiments the circuits depicted in figure 2, and figure 5 along with circuits illustrated in figure 6, figure 7, and figure 8 constitutes the PAM4 transceiver system of the present invention and implements the method there of according to present invention that enables fast and accurate data communication that is data transmission and reception in the highly EMI induced environment, for example data transmission and reception in the presence of EMI for backplane and chip-to-chip communication.
[0048] According to one of the preferred embodiments, the system and method thereof of the present invention may be implemented as an integrated element of data communication network/communication systems.
[0049] According to one of the preferred embodiments, the system and method thereof of the present invention may be implemented as standalone system as a chip which may be used in various communication applications.
[0050] According to one of the preferred embodiments, the system and method thereof of the present invention may be implemented over an FPGA, CPLD or may be implemented as an ASIC.
[0051] Further, while one or more operations have been described as being performed by or otherwise related to certain modules, devices or entities, the operations may be performed by or otherwise related to any module, device or entity.
[0052] Further, the operations need not be performed in the disclosed order, although in some examples, an order may be preferred. Also, not all functions need to be performed to achieve the desired advantages of the disclosed system and method, and therefore not all functions are required.
[0053] While select examples of the disclosed system and method have been described, alterations and permutations of these examples will be apparent to those of ordinary skill in the art. Other changes, substitutions, and alterations are also possible without departing from the disclosed system and method in its broader aspects.
,CLAIMS:We claim:

1. A data communication system immune to electromagnetic interference, the data transmission system comprising:
a four-level pulse amplitude modulation (PAM4) transmitter (200) having an input and an output (OUTP, OUTN) connected to a transmission line (100), wherein the PAM4 transmitter (200) comprises:
a first processing section (210) and a second processing section (220);
a plurality of modified electrostatic discharge (ESD) protection circuits (230) given to the output (OUTP, OUTN) and to a plurality of different voltage levels (V1, V2, V3, V4);
an input level shifter (ILS) (240) provided between the first processing section (210) and the second processing section (220), and a logic circuit (250);
a four-level pulse amplitude modulation (PAM4) receiver (300) connected to the transmission line (100), the PAM4 receiver comprises a front end (310) stage;
wherein the low-level EMI is mitigated by the Input level shifter (ILS) (240) and high level EMI is mitigated by the plurality of modified ESD protection circuits (230).

2. The data communication system as claimed in claim 1, wherein each ESD protection circuit comprises a diode (D1) connected with a plurality of MOS transistors (a, b, c, d), wherein the plurality of MOS transistors given to the plurality of different voltage levels (V1, V2, V3, V4) and to the logic circuit (250).

3. The data communication system as claimed in claim 1, wherein the first processing section (210) is a most significant bit (MSB) processing section, comprising:
a first constant current source (IMSB); and
two Bipolar Junction Transistors (Q1, Q2) connected with the first constant current source (IMSB).

4. The data communication system as claimed in claim 1, wherein the second processing section (220) is a least significant bit (LSB) processing section, comprising:
a second constant current source (ILSB); and
two Bipolar Junctions Transistors (Q3, Q4) connected with the second constant current source (ILSB).

5. The data communication system as claimed in claim 1, wherein the front end comprises an increased common-mode range differential amplifier (500) with a NMOS part (501) working for higher input common-mode and a PMOS part (502) working for lower input common-mode.

6. The data communication system as claimed in claim 1, wherein the front end comprises a dual NMOS and PMOS based differential amplifier.

7. The data communication system as claimed in claim 1, wherein the PAM4 receiver further comprises a slicer (320), a differential DFF stage (330) coupled with a buffer (334) and a thermo-meter to binary decoder (340).

8. The data communication system as claimed in claim 1, wherein the logic circuit (250) is coupled with the plurality of modified ESD protection circuits (230).

9. The data communication system as claimed in claim 1, wherein the input level shifter (240) reduces the common-mode level of the input.

10. The data communication system as claimed in claim 1, wherein the plurality of modified ESD protection circuits (230) maintains the minimum eye-opening.