Claims:We Claim:
1. A method for digital beam forming using real time weight computations on an FPGA platform, said method comprising:
receiving a digital down converted signal at n MHz at a digital beam forming module;
computing of complex real time weights at ‘n*N’ MHz rate for forming ‘N’ beams;
running system clocks of the digital beam forming module at n*N MHz rate;
forming of N number of beams at the same time in multiplexed manner by multiplying the complex real time weights and the said digital down converted signal at a complex multiplier module;
demultiplexing the signal produced by said complex multiplier module to produce N number of output beams.

2. The method as claimed in claim 1, comprising the steps of:
receiving an input data signal;
amplifying the said input data signal;
converting amplified input data signal into a digital form;
down converting said amplified input data signal in digital form and producing the same at frequency n.

3. The method as claimed in claim 2, wherein the step of receiving an input data signal and amplifying the said input data signalis performed at an input frequency amplifier.

4. The method as claimed in claim 2, wherein the step of converting amplified input data signal into a digital form is performed at an analog to digital converter.

5. The method as claimed in claim 2, wherein the step of down converting said amplified input data signal in digital form and producing the same at frequency n is performed at a digital down converter module.

6. The method as claimed in claim 1, wherein the step of demultiplexing the signal produced by said complex multiplier module to produce N number of output beams takes place at a demultiplexer module that forms part of the Digital beam formation module.

7. The method as in claim 1, further comprising the step of:

receiving independent predetermined N number of beams for plot report generation.

8. A system for digital beam forming using real time weight computations on a field programmable gate array(FPGA) platform comprising:
atleast one input amplifying module configured to receive and amplify one or more input data signal and output an amplified signal;
atleast one analog to digital converter configured to receive the said analog amplified signal and convert said analog amplified signal into a digital signal;
atleast one digital down converter module configured to provide filtering and decimation by converting the said digital signal received into a lower frequency signal at a lower sampling rate as one or more digital down converted signal;
atleast one digital beam forming module configured to receive said one or more digital down converted signal and based on the angle provided by a Radar controller generate a signal containing predetermined N number of beams in multiplexed form;
atleast one demultiplexer to produce independent predetermined N number of beams from said signal containing predetermined N number of beams in multiplexed form.

9. A system as in claim 8, further comprising:
a signal processor configured to receive independent predetermined N number of beams for plot report generation.

10. The system as claimed in claim 8, wherein said digital beam forming module comprises of a real time weight generator module and atleast one complex multiplier.

11. The system as claimed in claim 10, wherein said real time weight generator module is configured to receive steering angle from a radar controller.

12. The system as in claim 10, wherein the real time weight generator module comprises of:

a multiplexer, a first multiplier, a second multiplier and a CORDIC.

13. The system as in claim 10, wherein, the real time weight generator module is configured to compute the one or more real time weights at n frequency multiplied by predetermined N number of beams rate for predetermined N number of beam formation.

14. The system as in claim 10, wherein the complex multiplier is configured to multiply one or more real time weight generated with said one or more down converted signal.
Dated this 28th day of September, 2018
FOR BHARAT ELECTRONICS LIMITED
By their Agent

(GIRISH VIJAYANAND SHETH) (IN/PA 1022)
KRISHNA & SAURASTRI ASSOCIATES LLP
, Description:FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

A SYSTEM AND METHOD FOR DIGITAL BEAM FORMING USING REAL TIME WEIGHT COMPUTATIONS ON A FIELD PROGRAMMABLE GATE ARRAY PLATFORM

BHARAT ELECTRONICS LIMITED,
CORPORATE OFFICE, OUTER RING ROAD, NAGAVARA, BANGALORE – 560045, KARNATAKA, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
TECHNICAL FIELD
[001] The invention herein relates generally to a radar system, and more particularly to digital beam forming for use with electronically scanned radar.
BACKGROUND
[002] Digital beamforming is well established as a method for directional signal transmission and reception. It has also established itself as a method of electronic scanning whereby individual antenna elements or subarrays are sampled and downconverted , and beam scanning is performed by a digital signal processor. However, current digital beamforming architectures often exhibit high cost and inadequate performance, including inadequate field of view (FOV), poor sensitivity, numerous grating lobes, high sidelobes and beam pattern distortion due to target motion. Furthermore, the cost of implementations may be considerable with increased computational requirements.
[003] Most of the contemporary Phased array Radars which features Digital Beam Forming (also referred to as DBF) may suffer from excessing requirements of resources for implementing Digital Beam forming in radars with multiple radiating elements. This is especially true when requiring DBF over received Data across wide range of frequencies.
[004] Various solutions implementing digital beam forming are existent in the art. US 7474262 B2Titled Digital Beam forming for an Electronically Scanned Radar System describes digital beam forming for use with electronically scanned radar. In an aspect, the document holds that the disclosure therein provides enhanced sensitivity, wide angle or field of view (FOV) coverage with narrow beams, minimized number of receivers, reduced sidelobes, eliminated grating lobes and beam compensation for target motion. In an aspect, the document holds that the disclosure therein employs a uniform overlapped subarray feed network, a time multiplexed switch matrix, and a restructured digital signal processor. Furthermore, the document holds that the disclosure therein provides that antenna channels share a receiver, rather than maintain a dedicated receiver for each antenna element, as in conventional systems. The document holds that in the disclosure therein, Doppler/frequency filtering is performed on each antenna element or subarray output prior to digital beamforming. Further, Doppler compensation is employed following Doppler/frequency filtering, followed by digital beamforming. However, since the invention therein employs one or more of a uniform overlapped subarray feed network, a time multiplexed switch matrix, and a restructured digital signal processor there may be increased cost to such implementation.
[005] Another solution is provided in US 9031165 B2 Titled Efficient signal processing for receiving and transmitting DBF arrays. Described therein is a phased-array communications system with a distributed processing architecture, where channelized beamforming is used to minimize sampling and computational requirements, as well as reduce the data rates required for the communication of data and control information between system components. A central processor within the phased array system performs parallelized synthesis of channelized beams to form composite beams in sub-bands that overlap multiple channels. The document holds that the disclosed phased array system incorporates a flexible scheme for channelization, channelized beamforming, and synthesis so that any number of composite beams may be synthesized in parallel at any one time. Further the document holds that the system is capable of simultaneously processing beams that occupy overlapping sub bands, and does not require restriction on the bandwidths or center frequencies of the subbands which the beams occupy.
[006] Another solution is provided inUS 2016/0131741A1 Titled Apparatus and method for forming beam for processing Radar signal. This document holds that the disclosure therein provides an apparatus and method for forming a beam for processing a radar signal. In order to form a beam, by processing signals that are received through a plurality of antennas, a first symbol signal and a second symbol signal, which are complex signals are generated. The first and second symbol signals include a plurality of symbols that are arranged in an antenna array order. By applying a weight value on each antenna basis and a window coefficient for windowing processing to sequentially input each symbol of the first and second symbol signals, and by accumulating on a beam basis to generate, a beam symbol signal is generated.
[007] Yet another solution is provided in EP 3147687 A1 Titled Method and device for real-time processing of elevation digital beam-forming. Disclosed therein is a real-time elevation DBF processing method, which includes: weighting and summing processing is performed on an intermediate frequency signal obtained from sampling made on each channel to obtain two channels of combined intermediate frequency signals; frequency mixing-based orthogonal demodulation is performed on signals in real number field of the two channels of combined intermediate frequency signals respectively; and cross summation is performed on two channels of demodulated intermediate frequency signals and resulting signals are low-pass filtered. Further disclosed is a real-time elevation DBF processing device.
[008] All the above solution still suffer from high resources requirement especially for implementing Digital Beam forming in radars with multiple radiating elements requiring DBF over received Data across wide range of frequencies.
SUMMARY
[009] This summary is provided to introduce concepts related to digital beam formation. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0010] One of the various embodiments herein may include one or more systems and methods for digital beam forming using real time weight computations on a field programmable gate array(FPGA) platform.
[0011] In one embodiment the method for digital beam forming using real time weight computations on an FPGA platform may comprise the steps of receiving a digital down converted signal at n MHz at a digital beam forming module and computing of complex real time weights at ‘n*N’ MHz rate for forming ‘N’ beams. Further, running system clocks of the digital beam forming module at n*N MHz rate takes place. Forming of N number of beams at the same time in multiplexed manner by multiplying the complex real time weights and the said digital down converted signal at a complex multiplier module allows for maximum resource utilization by diminishing the need for storage, at the least.
[0012] Finally, the predetermined N number of beams needed are produced by demultiplexing the signal produced by complex multiplier module to produce N number of output beams.
[0013] In one embodiment, a system for digital beam forming using real time weight computations on an FPGA platform is provided. It comprises of atleast one input amplifying module configured to receive and amplify one or more input data signal and output an amplified signal. Further, atleast one analog to digital converter configured to receive the said analog amplified signal and convert said analog amplified signal into a digital signal is provided. The signal there from is down converted at digital down converter module configured to provide filtering and decimation by converting the said digital signal received into a lower frequency signal at a lower sampling rate as one or more digital down converted signal.
[0014] A digital beam forming module is configured to receive said one or more digital down converted signal and based on the angle provided by a Radar controller generate a signal containing predetermined N number of beams in multiplexed form. The signal therefrom are needed to be demultiplexed in order to be able to form N number of beams.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0015] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0016] Fig. 1 illustrates a schematic of a system for digital beam forming using real time weight computations on an FPGA platform as per an embodiment herein.
[0017] Fig. 2 illustrates a schematic of the digital beam forming module as per an embodiment herein.
[0018] Fig 3 illustrates a schematic of the real-time weight generation module as per an embodiment herein.
[0019] Fig. 4 illustrates a schematic of the complex multiplier module as per an embodiment herein.
[0020] Fig 5 illustrates a block diagram of the complex multiplier module as per an embodiment herein.
[0021] Fig 6 illustrates a block diagram depicting the digital beam forming using real time weight computations on an FPGA platform as per an embodiment herein.
[0022] Fig 7 illustrates a block diagram depicting the digital beam forming using real time weight computations on an FPGA platform as per an embodiment herein.
[0023] Fig 8 illustrates the flowchart of a method for digital beam forming using real time weight computations on an FPGA platform as per an embodiment herein.
[0024] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0025] A system and method for digital beam forming using real time weight computations on a field programmable gate array(FPGA) platform is described. In one embodiment a method of Beam Forming which includes a process of altering the complex weights on-the-fly to achieve better resource utilization in FPGA based hardware.
[0026] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present claimed subject matter. It will be apparent, however, to one skilled in the art that the present claimed subject matter may be practiced without these details. One skilled in the art will recognize that embodiments of the present claimed subject matter, some of which are described below, may be incorporated into a number of systems.
[0027] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently claimed subject matter and are meant to avoid obscuring of the presently claimed subject matter.
[0028] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
A. Overview
[0029] Fig. 1 illustrates a schematic of a system for digital beam forming (on a receiver side) using real time weight computations on an FPGA platform as per an embodiment herein. The system(100) may comprise of various input amplifying modules 102 a-n (also referred to as input frequency amplifiers or IF AMP) that are configured to receive input data 101a-n at corresponding IF AMP. For example the IF AMP 102a is configured to receive the input data 101a and provide an analog input to a corresponding analog to digital converter (Referred to as A/D or an ADC) 103a. Similarly, input frequency amplifiers 102a-n provide input to various ADC 103a-n. Further, digital down conversion module (Referred to as DDC module) 104a-n is configured to provide filtering and decimation by converting the various digital signal received into a lower frequency signal at a lower sampling rate.
[0030] Further, a digital beam forming module (referred to as DBF) 105 may be configured to receive outputs of the various DDC 104a-n and based on the angle provided by a Radar controller generate required number of beams (N).A signal processor may be configured to receive the number of beams for plot report generation.
[0031] Fig. 2 illustrates a schematic of the digital beam forming module (DBF module) as per an embodiment herein. The DBF module 105 may comprise of a real time weight generator module204 and multiple complex multipliers 202a-n. The real time weight generator module204 is configured to receive steering angle from a radar controller. Various complex weights generated may be multiplied with the incoming data signal 201a-n from the digital down converters 104a-n. The DBF module may produce N number of beams.
[0032] Fig 3 illustrates a schematic of the real-time weight generation module as per an embodiment herein. The module may comprise of a multiplexer 304, a first multiplier 312, a second multiplier 306 and a CORDIC (for COordinate Rotation DIgital Computer) 308. As per an embodiment herein if a predefined ‘N’ beams are required to be formed, then real time weights may be computed at ‘n*N’ MHz rate. Here, “n*N” is limited by the maximum possible clock rate of the FPGA chosen. Complex weights in real time may be computed at the real-time weight generation module 204 to be then multiplied with DDC 201a-n which formed the input to the DBF processing module.
[0033] Fig. 4 illustrates a schematic of the complex multiplier module as per an embodiment herein. The complex multiplier module may be present in the DBF module as was described in reference to figure 2.
[0034] For each of the complex multiplier the two inputs that need to be multiplied includes the output of CORDIC 308 as described in reference to figure 3(depicted with numeral 401 in figure 4), and DDC modules output coming into the DBF module at n MHz (depicted with numeral 402 in figure 4).
[0035] A person skilled in the art may realize that each complex weight generated may comprise of two components, the real 405a and the imaginary 405b. Similarly, the output from the DDC module may have two components, real component 407a and an imaginary component 407b. Hence, the output of the complex multiplier 404 may be in form of real component 406a and imaginary component 406b.
[0036] Fig 5 illustrates a block diagram of the complex multiplier module as per an embodiment herein. The complex multipliers generated (502) from the input data at n MHz 501a and computation of real time weights 501b may be demultiplexed to form N beams 505. This may be done with the use of a demultiplexer 504 before the signal processing stage 106 as shown and explained in reference to figure 1.
[0037] The above concept of demultiplexing may be understood more clearly with reference to figure 6 and figure 7a, 7b. Conceptually, the input data 601 which may be input at the frequency of n MHz is multiplied with various weights generated 602a-n (each for beam 1 to N). This may be produced as an output in form of multiple beams 1 to N (depicted as 604a-n).
[0038] Fig 7 illustrates a block diagram depicting the digital beam forming using real time weight computations on an FPGA platform as per an embodiment herein. More particularly figure 7a depicts multiplexed data output after multiplying input with weights. Data will move in multiplexed way in the design as 1st range bin701 (1,2, 3..N beams data) , 2nd range bin702 (1,2,3..N beams data), so on and so forth till the last range bin703 (1,2,3..N beams data) for all PRTs.
[0039] The above multiplexed data may be required to be demultiplexed at the demultiplexer 504 described more in reference to figure 5. These demultiplexed beam data output is depicted in figure 7b. As seen there for each beam 1 to N (712, 714 until 716)the values generated in each range bins 1 to B 712a to 712n are present.
B. DBF module computation
[0040] Various modules present in the DBF module 105 more explained in reference to figure 2 to figure 7 are configured to implement computations as would be explained in more detail here.
[0041] DBF module 105 may input at any instant of time, a complex matrix with entries corresponding to output of each ADC 103a-n after passing through the DDC module 104a-n. This data along with steering angle from radar controller is used to compute various beams 1 to N.
[0042] The computation of output may be represented as follows:
OUTPUT = COEFFICIENTS *INPUT
Hence, Output Y= CX
Where,
X= Complex digitised input data 101a-101n.These real and imaginary components may be represented as I +jQ
C= complex Weights given by following equation:
Here, Beam weights may be computed for element with location m,n for the beam with offsets (u,v) as follows:
e-j*2*pi/?*(m*dx*beam_offset_u+n*dy*beam_offset_v)=e-j*k*( k2*beam_offset_v)
= e-j*k3=cosk3 -jsink3

[0043] Here, “du” that stands for offset in azimuth is equal to zero since in the example taken, Multiple beams are formed in elevation only.
Beam offsets are [(0,0),(0,dv),(0,2dv),(0,3dv),(0,4dv),(0,5dv),( 0,6dv),(0,7dv), ( 0,8dv)]
Here, m= location in x-axis
n= location in y-axis
dx= interelement spacing in x-axis
dy= interelement spacing in y-axis
du = sin(deg2rad(dAz)) = offset in azimuth = 0
dv = sin(deg2rad(dEl)) = offset in elevation
Refer the matrices given below:

Assume the following,
m = number of elements
B = total number of range bins
N = total number of beams
Coefficients size = N*m
Input size = m*B
output size = N*B
[0044] A person skilled in the art may realize that in various embodiments herein, real time computation, weights calculations using CORDIC, multipliers, and a multiplexer drastically reduces resource requirement. This may be especially true when comparing with offline mode, where weights are computed beforehand and stored in memory/LUT and are retrieved whenever complex multiplication has to be done for beam generation. This may be further appreciated in a scenario where resolution of beam formation angle is very high and if large beam steering angle range is required and if large spot frequency range is required. In such cases, large number of coefficients are required for beam formation and offline method of weight generation consume large amount of memory.
[0045] Particular embodiments present herein therefore provide an enhanced generation of complex weights with minimal resources since all the weights may be generated at a time by using multiplexer running at n*N MHz rate. Hence, the FPGA resources consumed to form all weights are equal to resources consumed for single weight generation. This may be further understood using following example.
[0046] For example, to form ‘N’ beam weights/antenna element in elevation i.e., ((0,0);(0,dv);(0,(2*dv)).......;(0,(N*dv))
where N = number of beams
dv = beam offset in elevation
Beam offsets in multiplexed way running at n*N MHz (< = maximum possible clock frequency of FPGA) may be generated. Generated value may be multiplied with constant ‘k’
where k = (2p/?) *d
d being interelement spacing
? being the wavelength. This value may be given to CORDIC to generate real and imaginary value of weights running at n*N MHz.
[0047] The complex weights generated using the learnings above may be multiplied with the input (coming from DDC modules 104a to 104n in figure 1). Particular embodiments herein provide for the above by generating the weights at n*N MHz rate if the data is coming at n MHzThen multiply all set of weights with the input at same instant by running system clock at n*N MHz rate and form all beam at the same time in multiplexed way. This may be later demultiplexed to get independent beams as described in reference to figure 5.
[0048] A person skilled in the art may realize that this concept may be used for generating any number of beams by using corresponding “N” Factor limited by the maximum frequency possible in the FPGA chosen where N is the number of beams to be formed. In an exemplary implementation shown below the result of applying above computations can be more clearly understood.
[0049] Comparison of Results obtained before and after Optimisation as implemented on Virtex®-7 - 690T an FPGA development board by XILINX® wherein CORDIC was used (as shown in fig 3) to generate complex weights:
In below example, N = 9
n =10 MHz
i.e, 9 beams have to be formed wherein input IF data rate is 10MHz
Number of resources required for a single channel when input data at 10MHz multiplies with complex weight coming at 10MHz:

Number of resources required for a single channel when input data at 10MHz multiplies with complex weights coming at 90MHz.
Number of resources for a single channel when each beam complex weight is generated using CORDIC separately

Number of resources for a single channel when multiplexed 9 beams complex weights are generated at 90MHz using single CORDIC at a time.

After computing the weights in real time, it is required to multiply the complex weights with the incoming data.
[0050] Fig 8 illustrates the flowchart of a method for digital beam forming using real time weight computations on an FPGA platform as per an embodiment herein. The method comprises the steps of receiving 801 the input data signal. This may be performed at the input frequency amplifier. Further amplifying 803of the signal for further processing takes place. Further step includes converting805 of the amplified input signal into digital input signal.
[0051] Further step includes down converting 807the input digital signal. This may be done for filtering and decimation and may be carried out using a DDC (Digital Down Convertor) module for down conversion.
[0052] Further step includes receiving809 digital down converted signal at n MHz. This may be performed at a DBF module. Computing811 of complex real time weights at ‘n*N’ MHz rate then takes place considering, ‘N’ beams are required to be formed. Also, “n*N” is limited by the maximum possible clock rate of the FPGA chosen.
[0053] Further, running 813system clocks at n*N MHz rate takes place. After this forming 815of all beam at the same time in multiplexed manner is performed. This may be performed at the DBF module. Hence, DBF software module should run at ‘n*N’ MHz rate. This enables reducing of resource by factor of ‘N’. Data will move in multiplexed way as 1st range bin (1,2,3..N beams data) , 2nd range bin (1,2,3..N beams data), so on and so forth untill last range bin (1,2,3..N beams data) for all PRTs.
[0054] Further, data can be reproduced by demultiplexing817 in the following format:
1st beam(all range bins), 2nd beam(all range bins), 3rd beam(all range bins), so on and so forth untill the nth beam(all range bins)
[0055] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0056] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the claims appended.