DESC:DESCRIPTION OF THE INVENTION:
Technical Field of the Invention
[0002] The present invention relates to the hardware design of a robust compute system capable of enabling high-speed communication. More specifically, the invention relates to the system method for enabling macro-processing systems.
Background of the Invention
[0003] In order to achieve higher integration, there have been significant changes observed in electronic packaging and distribution of components over a fabrication surface or a board. In some cases, certain chips with a large distribution of components over the chip are used to achieve higher processing and communication properties. However, such chips face challenges with respect to thermos mechanical conditions.
[0004] Data processing demands are increasing as the numbers of consumers are increasing rapidly. Data centers are expected to operate at high speed without compensating much for power. Further, the data processing demands are increasing, and users expect to maintain a certain level of performance on their mobile devices in terms of processing speed and battery life. Maintaining the user expected level of performance on a mobile device creates a dilemma of whether to sacrifice performance for longevity or sacrifice longevity for performance, all while managing the thermal issues of the multicore processors.

[0005] Currently, manufacturers manage power consumption and thermal issues in multicore devices by throttling the processing clock frequency of the multiple processor cores. Throttling the processing clock frequency of multiple processor cores of multicore devices can help manage power consumption and thermal issues by reducing the rate of work accomplished by multicore processors. However, this technique focuses on managing these issues at the expense of performance.
[0006] Further, to reduce the warpage as well as to improve the reliability of chip packages, certain technologies are under development. For example, some types of clips are described to reduce the warpage by clamping the substrate or holding the chip onto the substrate when dispensing and curing an underfill material. Also, a variety of stiffener rings or lids are provided to reduce the warpage of the substrate of chip packages. However, the conventional stiffener rings are to constrain the thermal deformation of the substrate, not bonding to the sides of the chip for constraining the thermal deformation of the chip.
[0007] For example, proper airflow circulation and keeping hot and cold air separated. There exist certain tools to help manage airflow, including rack-mounted fans and blanking panels which can help direct and contain airflow. In case of multiple racks setting up a hot and cold aisle system can also help manage airflow. In addition to the hot and cold aisle setup, a partial containment setup will also help prevent hot and cold air from mixing by preventing the air from escaping each aisle. However, these methods become a liability for the organization since the methods involve high investment and costly maintenance.
[0008] Further, in case of re-configuring, the servers in a data center or/and in upgrading the data center infrastructure, procurement, and deployment of resources is always a hectic process both in terms of technical as well as the amount of manual work involved.
[0009] Hence, there is a need for a system that is easily assemble-able/connectable, modular, flexible for creating computer systems, networks, topologies, and architectures as needed. Also, there is a need for a system that shall cater to the need of higher-order processing and communication for AI-related applications.

OBJECTIVES OF THE INVENTION:

[0010] The primary objective of the present invention is to provide a “SYSTEM” for enabling reconfigurable and flexible Modular Compute in a network environment for high performance and flexible computing.

[0011] It is the objective of the invention to provide a high-performance and flexible computing network consisting of Macro-processing systems that may be a plug-in replacement.

[0012] Another primary objective of the present invention is to provide a “METHOD” for the above system for enabling reconfigurable and flexible Macro-processing systems in a network environment for high performance and flexible computing.

[0013] Another primary objective of the present invention is to provide a “MACRO-COMPUTING SYSTEM” which comprises a plurality of reconfigurable and flexible micro-computing systems in a network environment for high-performance, flexible computing and high-speed communication.

[0014] It is the objective of the invention to provide a “system,” and “method” performed using the reconfigurable, flexible, advanced “macro-computing systems” of the present invention to enable easily assemble-able/connect-able/integratable, modular, flexible micro-computing systems in a particular combination, for creating computer systems, networks, topologies, and architectures as needed.
[0015] It is the objective of the invention to provide a “system” and “method” performed using the “modular compute” system of the present invention to provide efficient and simple cooling of devices and computing systems in the architecture of the network environment and data center.
Summary of the invention
[0016] To the enablement of the present disclosure and related ends, the at least one aspect comprises the feature(s) hereinafter completely described and particularly and/or specifically pointed out in the specification at the section of claims. The following drawings and description set forth in detail enable certain exemplary features of at least one aspect(s). Described features are indicative, however, of but a few of the many ways in which the following principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.
[0017] The disclosed method solves the problem of .higher order processing and communication by using a network of macro-processing systems. The method of enabling a macro-processing system includes obtaining instructions by a macro-processing system distributing the obtained instructions among the plurality of micro-processing systems via intra-wafer connections. The method further includes executing the distributed instructions by each of the plurality of the micro-processing systems in coordination with each other and transmitting the executed instructions by the macro-processing system.
[0018] This summary provided herein is to introduce a section of concepts in a simple and clear form which are further described in the Detailed Description. This summary provided herein is not intended to particularly identify key features or essential features of the claimed invention or subject matter, nor is it intended to be used as a support or as an aid in determining the scope of the claimed subject matter.
[0019] The above summary is descriptive and exemplary only and is not intended to be in any way restricting. In addition to the descriptive aspects, embodiments, and features described in the above summary, further features and embodiments will become apparent by reference to the accompanying drawings and the following detailed description.
Brief Description of Drawings
[0020] The foregoing and any other features of embodiments will become more evident from the following detailed description of embodiments when read along with the associated drawings. In the drawings, like elements refer to like reference numerals.
[0021] In the following description, a number of specific details are put forward in order to enable a thorough comprehension of various embodiments of the invention. However, it is evident to one skilled in the art that the embodiments of the invention may be put to practice with an equivalent arrangement or without using these specific details. In other examples, in order to avoid unnecessary obscuring of the embodiments of the invention, devices and well-known structures are clearly shown in the form of a block diagram.
[0022] FIG. 1 illustrates a network environment for enabling a macro-processing system, according to one embodiment of the invention.
[0023] FIG 2 illustrates a block diagram of a macro-processing system, according to one embodiment of the invention.
[0024] FIG. 3 illustrates a block diagram of one of the micro-processing systems, according to one embodiment of the invention.
[0025] FIG. 4 illustrates a working example of the macro-processing system, according to one embodiment of the invention.
[0026] FIG. 5 illustrates a flowchart depicting a method of functioning of the macro-processing system, according to one embodiment of the invention.
Detailed Description of Drawings
[0027] Reference to the description of the present subject will be made in detail, out of which one or more examples are shown in figures. Each one of the examples may be given to elaborate the subject matter and not serve as a limitation. Various modifications, alterations, and changes that are obvious to a person skilled in the art to which the invention relates are deemed to be within the scope, contemplation, and spirit of the invention.
[0028] The word “exemplary” will be used in this document to mean “illustration, instance or serving as an example.” Any detail described herein in the description as “exemplary” is not necessarily defined as preferred or advantageous over other aspects.
[0029] In this invention, the term “application” may also include executable content files, namely: markup language files, object code, patches, byte code, and scripts. Additionally, an “application” referred to in this subject matter may also include non-executable files in nature, for instance, data files that may need to be opened or other documents that may need to be accessed.
[0030] In this description, the terms “module”, “unit”, “component”, “system” and “database” and other similar things are aimed to refer to any kind of computer-related entity, which may include either software, hardware, firmware in execution or a combination of hardware and software. A component may either be an application running on a computing device or the computing device itself. For instance, a component may include but not be limited to being an object, a processor, a process running on a processor, a thread of execution, an executable, a computer, and/or a program. A component may be contained on either one computer and/or distributed within two or more computers. One or more components may be located within a thread of execution and/or within a process. There may be communication between these components through local and/or remote processes associated with any signal having at least one data packet (e.g., the data may interact between two different components in a distributed system, local system, and/or across a vast network such as the Internet). Furthermore, these components may be executed via numerous computer-readable media that have various data structures stored.
[0031] In this invention, the words “wireless handset”, “wireless communication device”, “wireless device”, “communication device”, and “the wireless telephone” may be used interchangeably. A variety of wireless capabilities associated with a number of portable computing devices are enabled with greater bandwidth availability after the emergence of the third generation (“3G”) and fourth-generation (“4G”) technology. Hence, a portable computing device may comprise a smartphone, a hand-held device with a wireless connection, a cellular telephone, a PDA, a navigation device, or a pager.
[0032] As used in the application, the words ‘circuit’ or ‘circuitry’ refers to one or more of the following: (a) circuits such as a microprocessor(s) or a part of a microprocessor(s), that may require firmware or software for its operation, which may not require the firmware or software to be present physically and (b) hardware-only circuit implementations (like implementations in digital and/or analog circuit) and (c) a combination of firmware (and/or software) and circuits, namely:(i) a part of software/processor(s) (including memory(ies) and software that work together to cause a device, such as a server or a mobile phone, to perform several operations) or (ii) a combination of one or more processor(s).
[0033] The definition of ‘circuitry’ may be applicable to all the uses of this term throughout the application, including the claims. The term ‘circuitry’ may also include, for instance and if applicable to a specific claim element, specific integrated circuits such as one for a mobile phone, or a baseband integrated circuit or any similar server based integrated circuit, any network device or a cellular network device. Furthermore, the term ‘circuitry’ as used in this application may also cover an implementation of a part of a microprocessor, a processor (or multiple processors) and its (or their) accompanying firmware and/or software.
[0034] In this application, the term “content” may include files that have executable content, namely: byte code, patches, object code, markup language files and scripts. Additionally, “content” referred to herein, may also cover files that are not executable in nature, like the documents that require data files that need to be accessed or documents that may need to be opened.
[0035] FIG. 1 illustrates a network environment, for enabling macro-processing systems (101/103). The Environment 100 may include a first macro-processing system 101, a second macro-processing system 103, a network 105, a remote device 107, and a local device 109.
[0036] Further, the first macro-processing system 101 may be communicatively coupled to the first macro-processing system 103 through free-space optics. In some example embodiments, the first macro-processing system 101 and the second macro-processing system 103 may also collectively be referred to as systems.
[0037] The network 105 may include the Internet or any other network capable of communicating data between devices. Suitable networks may comprise or interface with any one or more for instance, a local intranet, a LAN (Local Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), a PAN (Personal Area Network), a virtual private network (VPN), a MAN (Metropolitan Area Network), a frame relay connection, a storage area network (SAN), an Advanced Intelligent Network (AIN) connection, a synchronous optical network (SONET) connection, a digital E1, E3, T1 or T3 line, DSL (Digital Subscriber Line) connection, Digital Data Service (DDS) connection, an ISDN (Integrated Services Digital Network) line, an Ethernet connection, a dial-up port, for examples such as a V.90, V.34 or V.34b is analog modem connection, an ATM (Asynchronous Transfer Mode) connection, a cable modem or CDDI (Copper Distributed Data Interface) connection or an FDDI (Fiber Distributed Data Interface). Furthermore, communications may also comprise links to any of a variety of wireless networks, comprising GPRS (General Packet Radio Service), WAP (Wireless Application Protocol), GSM (Global System for Mobile Communication), or CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access),cellular phone networks, CDPD (cellular digital packet data), RIM (Research in Motion, Limited), GPS (Global Positioning System), duplex paging network, Bluetooth radio, or an IEEE 802.11-based radio frequency network. The network 110 can further comprise or interface with any one or more of an RS-232 serial connection, a SCSI (Small Computer Systems Interface) connection, a Fiber Channel connection, an IEEE-1394 (Firewire) connection, an IrDA (infrared) port, a Universal Serial Bus (USB) connection or other connections which may be wired or wireless, and comprise digital or analog interface or connection, with mesh or Digi® networking.
[0038] In another example embodiment, hardware implementations which are specifically dedicated, such as application-specific integrated circuits, programmable logic arrays, and many other hardware devices, can be built to implement numerous methods described hereafter. Applications may also include the apparatus of various embodiments can broadly include a variety of computer systems electronic boards. In more than one example, embodiments described hereafter may carry out functions using more than two specific devices with related control or interconnected hardware modules and data signals which can be transmitted and received between and through any of the modules, or as portions of an application-specific integrated circuit. Accordingly, the present system comprises of firmware, software, and hardware implementations.
[0039] In an example embodiment, the remote device 107 may be communicatively coupled to the system (101 /or 103) via the network 105. In some example embodiments, the remote device 107 may include but not limited to mobile phones, laptops, desktops and the like. In some example embodiments, the remote device 107 may receive a plurality notification based on one or more functions associated with the system (101 and/or 103).
[0040] In an example embodiment, the local device 109 may receive and/or send data to any of the systems (101 and/or 103). The local devices 109 may include but not limited to a keyboard, mouse, touch screen, pen tablet, joystick, MIDI keyboard, scanner, digital, camera, video camera, microphone monitor, projector, TV screen, printer, plotter, speakers, external hard drives, media card readers, digital, camcorders, digital mixers, MIDI equipment and the like. In some example embodiments, the peripheral devices 109may be any circuitry to determine data integrity associated with the received optical signals.
[0041] Further, communication between the local devices 109 and the system (101 or 103) may be wired or wireless in nature. Similarly, communication between the remote devices 107 and the system (101 or 103) may be wired or wireless in nature—however, communication between the systems (101 and 103) is based on free-space optics.
[0042] . FIG 2 illustrates a block diagram of a macro-processing system (101 or 103) , according to one embodiment of the invention. The macro-processing system comprises a plurality of micro-processing systems (201-213) and a coupling port 215. The plurality of micro-processing systems includes a first micro-processing system 201, a second micro-processing system 203, a third micro-processing system 205, a fourth micro-processing system 207, a fifth micro-processing system 209, a sixth micro-processing system 211, a seventh micro-processing system 213. Each of the plurality of the micro-processing systems (201-213) are connected by an internal wire bonding.
[0043] In some example embodiments, the macro-processing system (101 or 103) may be formed by an un-diced silicon wafer of 8-inch diameter. The silicon wafer acts as an interposer on which the plurality of the micro-processing systems (201-213) and the coupling port 215 are placed, and their respective wire bond-based interconnections are established. In some example embodiments, the coupling port 215 may be used to connect the macro-processing system (101 or 103) to external devices. In some example embodiments, the coupling port 215 may be used as a power supply port as well.
[0044] FIG. 3 illustrates a block diagram of one of the micro-processing systems, according to one embodiment of the invention. The micro-processing system (201-213), for example, considered the first micro-processing system (201), comprises a processor 301, a first FPGA 303A, a second FPGA, 303B, a memory 305, a CPLD 309, power couplers (307A-307B), an optical transceiver 311. The processor 301 may be any processor, such as 32-bit processors using a flat address space, such as a Hitachi SH1, an Intel 960, an Intel 80386, a Motorola 68020 (or any other processors carrying similar or bigger addressing space). Processors other than the above mentioned processors that may be built in the future are also apt. The processor can include but is not limited to the general processor, Application Specific Integrated Circuit (ASIC), Digital Signal Processing (DSP) chip, AT89S52 microcontroller firmware, or a combination thereof.
[0045] Processors which are suitable for carrying out a computer program may include, by example, both special and general-purpose microprocessors or processors of any kind for a digital computers. Generally, a processor obtains instructions and data through a read-only memory card or random-access memory (RAM) or both. The vital elements of a computer are its processor for carrying out instructions and multiple memory devices for hoarding data and instructions. Generally, a computer includes, or be operatively associated with transferring data to or receive data from, or both, multiple mass storage devices for hoarding data, e.g., magneto-optical disks, magnetic, or optical disks. However, a computer requires no such devices. Moreover, a computer can be lodged into another device without much effort, e.g., a personal digital assistant (PDA),a mobile telephone, a GPS receiver, a mobile audio player, to name a few. Computer-readable media which are suitable for hoarding computer programs and data consists of all forms of media, and memory devices, non-volatile memory, including semiconductor memory devices, e.g., EEPROM, EPROM, and magnetic disks, flash memory devices; e.g., removable disks or internal hard disks ; magneto optical disks, DVD-ROM disks and CD ROM . The memory can be of non-transitory form such as a RAM, ROM, flash memory, etc. The processor along with the memory can be supplemented by, or subsumed in, special purpose logic circuits. In some example embodiments, the first FPGA 303A and the second FPGA 303B includes configurable logic blocks that are controlled by the processor 301. In some example embodiments, the CPLD 309 includes a reprogrammable array for AND/OR gates that may execute a multitude of logic functions/operations, controlled by the processor 301.
[0046] In accordance with an example embodiment, the memory 305 includes both static memory (e.g., ROM, CD-ROM, etc.) and dynamic memory (e.g., RAM, magnetic disk, writable optical disk, etc.) for enabling the execution of instructions distributed by the macro-processing system, in sync with the other micro-processing systems. In some example embodiments, the power couplers (307A and 307B) include capacitors that regulate the supply of power.
[0047] In accordance with an example embodiment, the optical transceiver 311 includes an array of LASER/PID and lens assembly that transmits and/or receives instructions in the form of light via free-space communication. In transmission mode, the executed instructions are converted into optical signals by the LASERs, and in reception mode, the instructions are received in the optical signal form and that is converted into electrical signals by the PID. The Detailed working of the micro-processing system to enable the macro-processing system is explained in the FIG. 4.
[0048] FIG. 4 illustrates a working example of the macro-processing system, according to one embodiment of the invention. The macro-processing system (101/103) is covered by a layer of transparent cover 401. In some cases, the transparent cover maybe a glass of refractive index of air. The plurality of micro-processing systems (201-213) is placed on an 8-inch circular interposer having an integrated re-distribution layer. The macro-processing system (101 or 103) executes parallel processing of instructions at a high execution rate as 14 FPGAs, 7 processors, 7 CPLDs, 7 memories function in tandem. Further, each of the transceivers, has the capacity to communicate at 200Gbps, and the macro-processing system (101 or 103), comprising 7 micro-processing systems, together form a total of 36 transceivers cumulatively achieving a speed of 7.2Tbps.
[0049] Each component on the macro-processing system (101 or 103), and any of the micro-processing systems may be placed using solder ball-based attachment and epoxy attaches, which enables flexible physical reconfiguration of components. Further, usage of CMOS process and other regular processing thereby avoiding any excessive Engineering time on new process development.
[0050] In some example embodiments, with the proposed arrangement, a distributed computing system between multiple working modules becomes possible. All the devices have a common interposer for interconnectivity and can connect in parallel with a layer above or below. All Hex pads can connect independently with the layers above or below as well. Throughout the disclosure, the micro-processing system may also be referred to as the Hex pad.
[0051] A network of the macro-processing systems may be used for easy incorporation into AI-based applications where data transfer connectivity is expected to rise by orders of magnitude. Further, Free Space Communication associated with the macro-processing system will ensure direct communication with practically little to no cabling simplifying the cable issue at Data Centre. At a Data Centre, a network of macro-processing systems will offer greater performance while significantly reducing the carbon footprint and the physical real estate occupancy. The macro-processing unit may be provided power using a coupling port 215, and with the advent of Optical Interconnects, the power consumption per bit is also reduced to <3pJ/bit.
[0052] In some example embodiments, a data center may comprise a series of macro-processing systems connected along a horizontal plane and vertical plane. Any macro-processing system that obtains instructions for execution, after executing the instructions, transmits the executed instructions to any other macro-processing system in the series of macro-processing systems. The transmission from one macro-processing system and reception from another macro-processing system is performed via free-space optics. This transmission and reception may take place across any plane. In some example embodiments, the transmission may take place to a system outside the series of macro-processing systems.
[0053] In some example embodiments, the wafer base may be oriented for optimized placement of various components. For example, each of the micro-processing systems and associated components may be placed according to a certain orientation that enables easy assembly of the macro-processing system. Involvement of many components may make the assembly process complex, in order to eliminate the complexity, a certain orientation is allocated to each of the component. In such case, the assembly tool may accurately place the components dynamically. Further, while establishing communication between two macro-processing systems, wafer of one of the macro-processing system may slightly be rotated in clockwise/anti-clockwise direction to couple optical transceivers. Such fine arrangements, enable dynamic and smooth communication between the two macro-processing systems.
[0054] FIG. 5 illustrates a flowchart depicting a method of functioning of the macro-processing system (101 or 103), according to one embodiment of the invention. The flowchart shall be understood that each block of the flow chart of the method may be realized by various components, such as circuitry, firmware, processor, and/or other devices associated with the execution of software. The method may be implemented by a software executable by a computer system. The software may include computer-executable program instructions. In some examples, at least one function described in the method may be embodied by computer program instructions. The computer program instructions, which imply the functions of the method, may be stored by the memory and executed by the processor. Alternatively, the computer program instructions may be uploaded onto any programmable apparatus (for example, hardware, computer) to produce a machine, such that the resulting machine or other programmable apparatus implements the functions mentioned in the flow chart. Further, in some embodiments, the computer program instructions may be loaded onto one computer that is remotely located or on multiple computers that are located at one site or distributed across multiple sites. The multiple computers distributed across multiple sites may be interconnected through a communication network.
[0055] It shall also be understood that one or more blocks of the flow chart and/or combinations of the blocks of the flow chart may be implemented by special purpose hardware-based computer systems which perform the described functions or combinations of special purpose hardware and computer-executable instructions.
[0056] In accordance with an embodiment, at step 501, the method includes obtaining instructions by a macro-processing system. For example, in a network of macro-processing systems, one of the macro-processing systems obtains certain instructions to be executed.
[0057] In accordance with an embodiment, at step 503, distributing the obtained instructions among the plurality of micro-processing systems via intra-wafer connections. For example, the obtained instructions are distributed among the plurality of micro-processing systems by the micro-processing system. In an embodiment, the obtained instructions are distributed among the plurality of micro-processing systems via intra-wafer communication. The intra-wafer communication may correspond to an integrated wire bond-based communication.
[0058] In accordance with an embodiment, at step 505, executing the distributed instructions by each of the plurality of the micro-processing systems in coordination with each other. For example, the micro-processing systems that receive the instructions execute the same, using the available resources in or-ordination with each other.
[0059] In accordance with an embodiment, at step 507, transmitting the executed instructions by the macro-processing system. For example, the executed instruction is transmitted to another macro-processing system via optics-based communication enabled by a LASER and lens array associated with the micro-processing system.
[0060] The above-detailed description includes a description of the invention in connection with a number of embodiments and implementations. The invention is not limited by the number of embodiments and implementations but covers various obvious modifications and equivalent arrangements which lie within the purview of the appended claims. Though aspects of the invention are expressed in certain combinations among the claims, it is considered that these features may be arranged in any combination and order. Any element, step, or feature used in the detailed description of the invention should not be construed as crucial to the invention unless explicitly mentioned as such. It is also presumed by the attached claims to consider all such possible features along with advantages of the present invention which shall fall within the scope of the invention and true spirit. Therefore, the specification and accompanied drawings are to be contemplated in an illustrative and exemplary rather in limiting sense.
,CLAIMS:We claim,

1. A method, comprising
obtaining (501) instructions by a macro-processing system, wherein the macro-processing system includes a plurality of micro-processing systems;
distributing (503) the obtained instructions among the plurality of micro-processing systems;
executing (505), by each of the plurality of the micro-processing systems, the corresponding distributed instructions; and
transmitting (507) the executed instructions by the micro-processing system.

2. The method of claim 1, wherein the obtained instructions are distributed among the plurality of micro-processing systems via intra-wafer communication.

3. The method of claim 2, wherein the intra-wafer communication corresponds to an integrated wire bond-based communication.

4. The method of claim 1, wherein the executed instructions are transmitted to another macro-processing system via optics-based communication, and wherein the optics-based communication is enabled by a LASER and lens array associated with the macro-processing system.

5. The method of claim 1, wherein the macro-processing system includes the plurality of micro-processing systems and a coupling port, wherein the macro-processing system is connected to one or more external devices via the coupling port, and wherein the coupling port acts as a power supply port of the macro-processing system.

6. A system, comprising:
a macro-processing system (101) comprising a plurality of micro-processing systems (201-213);
wherein the macro-processing system (101) is configured to:
obtain instructions to be executed; and
distribute the obtained instructions among the plurality of micro-processing systems (201-213); and
wherein each micro-processing system of the plurality of micro-processing systems (201-213) is configured to execute the corresponding distributed instructions.

7. The system of claim 6, wherein the macro-processing system (101) is further configured to transmit the executed instructions.

8. The system of claim 7, wherein the executed instructions are transmitted to another macro-processing system (103) via optics-based communication, and wherein the optics-based communication is enabled by a LASER and lens array associated with the macro-processing system (101).

9. The system of claim 6, wherein the obtained instructions are distributed among the plurality of micro-processing systems (201-213) via intra-wafer communication, and wherein the intra-wafer communication corresponds to an integrated wire bond-based communication.

10. The system of claim 6, wherein the macro-processing system (101) includes the plurality of micro-processing systems (201-213) and a coupling port (215), wherein the macro-processing system (101) is connected to one or more external devices via the coupling port (215), and wherein the coupling port (215) acts as a power supply port of the macro-processing system (101).