DESC:RELATED PATENT APPLICATION:

This application claims the priority to and benefit of Indian Patent Application No. 202041023264 filed on June 03, 2020; the disclosure of which are incorporated herein by reference.

FIELD OF THE INVENTION:

The present invention relates to computer technology domain. More specifically, the invention relates to a system and method for enabling high-performance computing systems based on construction and assembly of an optics-based compute system.

BACKGROUND OF THE INVENTION:

Higher integration has become a trend in modern electronic packaging. One of the major challenges is to improve the thermo mechanical reliability when the package is subjected to thermal loads. However, the conjunct interfaces near the free edge always suffer high stress gradients and even can generate cracks, because the packaging components are fabricated with different thermal and mechanical properties.

Traditionally, chip manufacturers connect two monolithic central processing units (CPUs) together in a multichip module (MCM). An MCM is a package with pins where multiple integrated circuits, or chips (ICs), semiconductor dies, and/or other components are integrated. This is usually done on a unifying substrate, so when the MCM is in use it can be treated as if it were one large chip. An MCM is sometimes referred to as a hybrid IC. Chiplets are the individual ICs that make up an MCM. They provide a way to minimize the challenges of building with cutting-edge transistor technology. In recent days, the chiplet technology largely applied to scale beyond moore’s law.

Currently, manufactures manage power consumption and thermal issues in multi-core devices by throttling the processing clock frequency of the multiple processor cores. Throttling the processing clock frequency of multiple processor cores of the multi-core devices can help manage power consumption and thermal issues by reducing the rate of work accomplished by the multi-core processors. However, this technique focuses on managing these issues at the expense of performance.

Further, it is highly desirable to provide improved computer architectures and methods for providing and using such architectures that provide sufficient speed performance in large scale parallel processing data centers, while maintaining or reducing their power consumption. Such architectures should allow conventional software and operating systems to be employed where possible so that serial tasks are still available, but those tasks involving parallel operations can be achieved at significantly increased performance thereby reducing the burden to employ more numerous, and more powerful processors to expand capacity.

Eventually, when the system has ability to process significant load of data, the system needs to be provided with adequate data at a required rate. In traditional systems, numbers of instructions executed by the processor will be proportional to the rate at which data is received. In such cases scheduling algorithms associated with operating systems will be able to enable effective resource utilization. When the system has capacity to execute instructions at an improved rate, and if the instructions to be executed are not fetched at the required rate, it would affect resource utilization cycle of the system.

Further, in case of re-configuring the servers in a data center or/and in upgrading the data center infrastructure, procurement and deployment of resources is always a hectic process both in terms of technical as well as amount of manual work involved.

Hence, there is a need for construction and assembly of a system which is designed for high performance computing applications. For efficient enablement of the system there is a need for utilizing multiple technologies along with packaging methodologies. Further, to supplement the systems which are designed for high performance computing applications, there is a need for developing a high data rate communication mechanism both for inter-system communication and intra-system communication with thermal stability.

OBJECTIVES OF THE INVENTION:

The primary objective of the present invention is to design and provide a system and method for enabling high-performance computing systems (HPC Systems) based on construction and assembly of an optics-based compute system and thus meet the requirement of the need as stated above.

It is the objective of the invention to provide a modular distributed computing system interconnected with high-speed chip-to-chip, module-to-module optical interconnects. The optical interconnect acts as a replacement for on-chip/on-board highspeed data bus.

It is the objective of the invention to provide a proprietary high speed, free space optical interconnect “LightKonnect™” which is closely integrated with reconfigurable compute engines (FPGAs)/other application processors.

It is the objective of the invention to provide a high performance computing system (i.e. LightCompute™ system) which consists of one or more, preferably plurality of lego-like optoelectronic processors (i.e. “LightCompute™” lego which is optics based compute system, the construction of which is described herewith) and chip-to-chip, module-to-module high bandwidth free-space interconnects achieved by optical engine (i.e. “LightKonnect™”) for HPC and datacenters.

It is the objective of the present invention to utilize the capabilities of the optical engine (“LightKonnect™”) in the “LightCompute™” HPC system of the present invention.

Another objective of the invention is to provide a chip-to-chip, module-to-module, high speed, free-space optical interconnect and its applications using a System in Package (SIP).

An optical based System-in-Package (SIP) using the optical interconnect and engine (“LightKonnect™”) in the “LightCompute™” HPC system of the present invention.

SUMMARY OF THE INVENTION:

The present invention discloses a system and method for enabling construction and assembly of an optics based compute system. More specifically, the invention describes a system and method for enabling high-performance computing (HPC) systems based on construction and assembly of an optics based compute system. Further, enabling construction and assembly of said optics based compute system comprises at least one memory to store instructions and at least one processor execute the instructions, in order to automate the process of construction and assembly of the optics based compute system, wherein the method comprises transmitting one or more signals from at least one of a plurality of components placed on a interposer of a hybrid 3D transceiving module. The method may also include controlling, by a processor, an optical channel based on the transmitted one or more signals.

Further, the invention comprises enabling inter module and intra module, reception of the one or more transmitted signals. The method may further comprise, providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following summary, description and the drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.

In one embodiment, the invention provides and describes the proprietary “LightCompute™” system, free space optical interconnect “LightKonnect™” and an SIP module using the same, which are developed by the Applicant using the and/or in conjunction with the construction and assembly of said optics based compute system of present invention described herewith which is based on free space optical communication.

LightCompute™ system consists of lego-like optoelectronic processors and chip-to-chip, module-to-module high bandwidth free-space interconnects for HPC & datacenters. At the heart of this system, the proprietary high speed, free space optical interconnect “LightKonnect™” is developed which is closely integrated with reconfigurable compute engines (FPGAs)/other application processors. The FPGA, multiple Optical Engines, and peripherals are reflow soldered on an Organic Interposer as a SIP module. These modules can be configured in a 3D array with predefined orientation to enable free space optical coupling between SIPs. Data transfer rate between them is only limited by the on-chip SerDes of the logic devices.

LightCompute™ is a high performance, low power, optically interconnected array of System-in-Package (SIP) modules that can be scaled up for future computing needs. LightCompute™ combines an FPGA/custom application processor with “LightKonnect™” multi-Terabit free space optical IO bus to obtain high performance/watt efficiency. By packaging optoelectronics with FPGAs, the present invention develops and provides a highly power-efficient distributed computing system.

The Applicant has developed an unique hexagonal package/board designs (patent pending) which enables the system of the present invention to achieve high bi-section bandwidth and higher low-latency redundancy channels between the processors in comparison to 2D-tile arrays, linear, ring or torus arrays.

The LightCompute™ system can be scaled by assembling self-similar (low-cost of manufacturing) SIPs. Each SIP comes pre-loaded with application libraries for AI/HPC example use-cases demonstrating compute-distribution among the legos achieving acceleration and power efficiency. These can be used as templates for building customer applications for standalone or array of legos. We are currently working on data sharing between processors through our proof-of-concept Optical Engine that demonstrates accelerating DNN computations.

A system for enabling high-performance computing based on construction and assembly of an optics-based compute system (M1 or M2,…or Mn), wherein the said optics-based com-pute system comprises:
- one or more processor (201) which is reconfigurable,
- one or more memory (203) to store instructions, and
- one or more communication interface (205),
all assembled in an assembly and configured to enable chip-to-chip, module-to-module high bandwidth free-space interconnects and free-space optical communication;
wherein the said processor (201) executes the stored instructions of memory (203) in order to enable the compute system and automate the process of construction, assembly and communication,
- an interposer (317);
- a plurality of first components which comprises a switch IC (301) associated with a LASER driver (303), a LASER (305), a trans-impedance amplifier (TIA 307) and a PIN diode (309);
- a plurality of second components which comprises a plurality of alternative layers of Metal (313) and Redistribution Layer i.e RDL layers (315);
- a plurality of third component which comprises a glass block (321), signal optimizers (323a and 323b), dynamic channel holders (325a and 325b), inter-system channels (327a and 327b), intra-system channels (329a and 329b) and system holders (331a and 331b),
wherein the plurality of first components is connected to a plurality of second components via one or more electrical bumps (311a to 311o); and
wherein co-coordinated action of said plurality of first components, plurality of second components, and plurality of third components enables inter-system and intra-system free-space communication of the said optics-based compute system (M1 or M2,…or Mn).

The system wherein said alternative layering of Metal layers (313) and RDL layers (315) comprises:
- four layers of metal (313) viz. METAL1 (313d), METAL2 (313c), METAL3 (313b), METAL4 (313a), and
- four layers of RDL (315) viz. RDL1 (315d), RDL2 (315c), RDL3 (315b), RDL4 (315a),
wherein the layering is done by placing one layer of metal followed by one layer of RDL in alternative fashion.

The system, wherein the in the said layering,
- RDL4 (315a) is sandwiched between the metal layer4 (313a) and the metal layer 3 (313b),
- RDL3 (315b) is sandwiched between the metal layer3 (313b) and the metal layer2 (313c),
- RDL2 (315c) is sandwiched between the metal layer2 (313c) and the metal layer1 (313d), and
- RDL1 (315d) is sandwiched between the metal layer1 (313d) and the interposer (317).

The system, wherein the interposer (317) may comprise one or more through silicon vias (319a – 319d), and wherein the interpose (317) is sandwiched between the RDL1 (315d) of the plurality of second component and glass block (321) of a plurality of third compo-nent.

The system, wherein the switch IC (301) of the first plurality of components is the compu-tational unit which may include at least one processor (201), at least one memory (203) and communication interface (205), wherein the switch IC (301) is reconfigurable and may re-motely be operated by users based on configuration of the user interface.

The system, wherein the said intra-system communication comprises transmitting a signal from signal a laser driver (303) complemented by LASER (305), wherein the transmitted signal is passed through the second plurality of components and the third plurality of com-ponents, wherein the transmitted signal traverses from the intra-system channel (329b), through the glass block (321) and another intra-system channel (329a), and wherein the transmitted signal is received by the PIN diode (309) and the received signal is amplified by the trans-impedance amplifier (TIA) (307).

The system, wherein the inter-system communication is enabled by co-coordinated action by the first plurality of components, the second plurality of components and the third plu-rality of components, wherein signal from the LASER (305) traverses the intra-system channel (329b) and reaches the inter-system channel (327b), through the glass block (321) after the transmitted signal has been configured by the optimizer (323b), wherein the dy-namic channel holder (325b) may be used to align the inter-system channel (327b) to a network that exists the compute system (M1 and/or M2 and/or Mn).

The system, wherein the inter-system communication comprises the transmitted signal from any other compute system via the network may be received using the inter-system channel (327a) and the received signal may further be configured by the optimizer (323a) and sent to the PIN (309) via the glass block (321) and the intra-system channel (329a), wherein the dynamic channel holder (325a) may be used to align the inter-system channel (327a) to the external network.

The system, wherein the modular compute system (M1 and/or M2 and/or Mn) is construct-ed in a 3D hybrid model based on multiple techniques of fabrication at different stages of assembly which involves layering and/or vertically stacking integrated circuits (ICs) or cir-cuitry to achieve higher performance, increased functionality, lower power consumption, and a smaller footprint, and the modular compute system (M1 and/or M2 and/or Mn) may be attached to a network of circular using the system holders (331a and 331b).

The system, wherein the said construction and assembly of an optics based compute sys-tem (M1 and/or M2 and/or Mn) may be configured in a first configuration (two-way con-figuration) or a second configuration (one-way configuration).

The system, wherein the first configuration (two-way configuration), includes a switch IC (401) coupled with a heat sink (406), may be placed on an interposer (417), wherein the transmission of signals enabled by a laser driver (403) associated with a LASER (405), is transmitted through an intra-system channel (429b), further the transmitted signal is con-figured by an optimizer (423b), and transmitted to a network through an inter-system channel (427b), and wherein the inter-system channel (427b) may be controlled by a pro-cessor complemented dynamic channel holders (425c and 425d).

The system, wherein the modular compute system (M1 and/or M2 and/or Mn) may receive the transmitted signals from another compute system, and wherein the received signal may be configured by dynamic channel holders (425a and 425b) at an inter-system channel (427a) stage and further configured by an optimizer (423a), wherein the configured signal is delivered to a PIN diode (409) through an intra-system channel (429a) of the interposer (417) and the received signal by the PIN diode (409) may be amplified by the Trans-Impedance Amplifier (407), and the Switch IC (401) may execute at least one instructions based on information obtained as output from the TIA (407).

1. The system, wherein a plurality of electrical bumps (i.e. 411a-411p) may be used to place the PIN (409), the TIA (407), the Switch (401), the LASER driver (403) and the LASER (405) on the interposer (417) and system holders (431a and 431b) may be used to place the compute system (M1 and/or M2 and/or Mn) on a network.

The said system, wherein the optics based communication set up of the system may be ob-served in a first plane (i.e. lower plane) of the dual plane, wherein the optics based com-munication set of the system may include V-groves and Single Mode Fiber (SMF) enabled dynamic channel holders (425a-425d), inter-system channels (427a and 427b) (optical fi-ber), the optimizers (423a and 423b) (combination of lens and prism);
or
the compute and electronic based communication set of the system may be observed in a second plane (i.e. upper plane) wherein the compute set may include the heat sink (406) enabled switch IC (401), wherein the heat sink (406) is used to boost computational capacity of the switch IC (401) by eliminating the thermal stress and other hindrances, PIN (409), the TIA (407), the LASER driver (403), the LASER (405), the electrical bumps (411a-411p).

The said system, wherein the second configuration (one-way configuration) involves a sin-gle plane communication and computation which comprises a heat sink (506) enabled switch IC (501), a LASER driver (503), carriers (510a and 510b), a LASER (505), a TIA (507), a PIN (509), optimizers (523a and 523b), inter system channels (527a and 527b), intra system channels (529a and 529b), dynamic channel holders (525a-525d) are placed on an interposer (517) through a plurality of solder bumps (511a-511p).

The said system, wherein the interposer (517) may be conserved as reference plane, and wherein the optic based and electric based communication set may be placed on any side of the reference plane, and wherein the electric based set employs solder bump based in-terconnections and whereas the optics based set employs wire-bound inter connections.

The said system, wherein the carrier circuits (510a and 510b) electrically connected via solder bumps (511a-511p) to the PIN (509) and the LASER (505) enables single planar communication and computation.

The said system, wherein the carrier (510a) enables perpendicular reception of optical sig-nals by the PIN (509) and the carrier (510b) enables perpendicular transmission of optical signals by the LASER (505). The said system, wherein the system holders (531a and 531b) may be present in the second plane, or the first plane or reference plane and any combina-tion of thereof.

The said system, wherein the reference plane may be considered as a platform for placing various elements of assembly, wherein the elements may be distributed on both planes of the platform, or the elements may be distributed on one of the planes of the platform. The said system, wherein a zero-polymer circuit board (PCB) like structured may be construct-ed, wherein the optical interconnects and channels may be pre-determined and the com-pute systems may be assembled in a modular fashion, to create a network of an optics based compute systems (M1, M2,…Mn).

The said system, wherein the each of the optics based compute systems (M1, M2,…Mn) is designed in a modular hexagonal shape having six sides (LightCompute™ Processor Lego), each side having for free-space optical communication, wherein plurality of modu-lar hexagonal legos may be implemented one or more clusters placed on a platform, or clus-ters may be arranged in a array or array may be arranged in a 3D array stack, wherein the arrangement allows chip-to-chip, processor-to-processor, rack-to-rack signals communica-tion. The said system, wherein the optics based compute systems (M1, M2,…Mn) is LightCompute™ Processor Lego which may be provided in a System-in-Package (SIP) for HPC to be used in a network environment (100) such as data center.

An optical interconnect for modular distributed computing system, wherein the optical in-terconnect acts as a replacement for on-chip/on-board highspeed data bus, wherein the op-tical interconnect between the processors can be communicating in free space, through waveguides, buried in a PCB or on system-in-package, on-chip or through fiber-optic ca-bles, and wherein the optical interconnect may be packaged along with the bare die of the compute engine on the same package, interposer or the PCB.

A modular distributed computing system comprising optics based compute systems (M1, M2,…Mn) designed in a modular hexagonal shape having six sides (LightCompute™ Pro-cessor Lego), wherein the said each modular hexagonal lego comprises:
- one or more processor (201) which is reconfigurable,
- one or more memory (203) to store instructions, and
- one or more communication interface (205),
all assembled in an assembly and configured to enable chip-to-chip, module-to-module high bandwidth free-space interconnects and free-space optical communication;
wherein the said processor (201) executes the stored instructions of memory (203) in order to enable the compute system and automate the process of construction, assembly and communication,
wherein the logos are interconnected with high speed chip-to-chip, module-to-module optical interconnects, wherein the optical interconnect acts as a replacement for on-chip/on-board highspeed data bus.

The said modular distributed computing system, wherein the compute systems (legos) may be distributed in multiple clusters, wherein each cluster may have one or more pre-determined slots for the compute system (M1and/or M2 and/or Mn), wherein each slot may be pre-configured to enable inter system optic based communication, wherein further the cluster of legos may be arranged in array and arrays may be arranged in a 3D stack, which may be packaged in a server blade.

The said modular distributed computing system, wherein the cluster comprises two clusters (A and B) or more clusters, wherein cluster (A) comprises seven slots (601a, 603a, 605a, 607a, 609a, 611a, and 613a) and each slot may be interconnected using the optics based communication channel (615a), and cluster (B) comprises seven slots (601b, 603b, 605b, 607b, 609b, 611b, and 613b) and each slot may be interconnected using the optics based communication channel (615b).

The said modular distributed computing system, wherein the inter cluster communication may be enabled based on the same optic based communication channels, which comprises a communication, wherein the compute system slot (611a) of cluster (A) may be connected to the compute system slot (603b) of the cluster (B) are connected based on the pre-determined optics based communication channel.

The said modular distributed computing system, wherein in the slots of each Cluster (A) and Cluster (B), modular compute systems (M1, M2,……..M7) can be assembled such that cluster (A) may comprise seven modular systems (legos) viz. (M1, M2, M3, M4, M5, M6, and M7) placed on seven slots (601a, 603a, 605a, 607a, 609a, 611a, and 613a) respective-ly; and similarly cluster (B) may comprise seven modular systems (legos) viz. (M1, M2, M3, M4, M5, M6, and M7) placed on seven slots (601b, 603b, 605b, 607b, 609b, 611b, and 613b) respectively.

The said modular distributed computing system, wherein in one slot more than one modu-lar unit may be placed co-axial to the vertical axis such as the slot (601a) may hold one or more modular unit, whereas each modular unit may execute different operations, and the slot (601a) may comprise a centra processing unit (CPU), a graphic processing unit (GPU), a Field Programmable Gate Arrays (FPGA) or other related units, wherein multiple modu-lar units in a single slot may be placed (‘3D stacking’).

The said modular distributed computing system, wherein the modular units may be placed in a network such that at least two modular units communicate through free space optical (FSO) coupling, such as that the slots (601a and 603a) are configured to have any one side of the slot (i.e. any edge of 601a) parallel and co-axial to any one side of the slot (i.e. any edge of 603a), and wherein the free-space coupling is enabled at the edges which may be used for communication.

The said optics based compute system (M1, M2,…Mn) and the modular distributed com-puting system, wherein the said systems are used for enabling high-performance computing systems (HPC Systems) and as a SIP in a network environment, wherein the compute sys-tem is executed by a processor involving the method steps (701-707).

The said optics based compute system (M1, M2,…Mn) and the modular distributed com-puting system, wherein he system is performed by a method for enabling high-performance computing systems (HPC Systems) based on construction and assembly of an optics based compute system wherein the communication of signal and/or data between the compute systems (M1, M2,….Mn) and/or between the multiple clusters, each cluster comprising compute systems (M1, M2,….Mn) can be achieved by free space optical communication using opto-electrical connector (107) and/or a 3D transceiver module, wherein the trans-ceiver module may comprise one or more optical engine.

A method for enabling high-performance computing systems (HPC Systems) based on construction and assembly of an optics based compute system (M1, M2,….Mn) wherein method involves one or more processor which is performed according the method steps (701-707) which comprises:

- step 701 which includes enabling construction and assembly of an optics based com-pute system, which comprises transmitting one or more signals from at least one of a plurality of components placed on an interposer of a hybrid 3D transceiving module;

- step 703 which includes configuring and/or controlling, by a processor, an optical channel based on the transmitted one or more signals;

- step 705 which includes enabling inter module and intra module, reception of the one or more transmitted signals; and

- step 707 which includes providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module.

The method comprises transmitting one or more signals from at least one of a plurality of components placed on an interposer (317) of a hybrid 3D transceiving module, controlling, by a processor, an optical channel based on the transmitted one or more signals, enabling inter module and intra module, reception of the one or more transmitted signals and providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module. The above method is performed in optics based compute system comprises electrical bumps (311a to 311o), interposer (317), glass block (321), a switch IC (301), associated with a LASER driver (303), a LASER (305), TIA (307) and a PIN diode (309) [FIGS 3-6, 8-10].

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to limit the key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

BRIEF DESCRIPTION OF DRAWINGS OF THE INVENTION:

The foregoing and other features of embodiments will become more apparent from the following detailed description of embodiments when read in conjunction with the accompanying drawings. In the drawings, like reference numerals refer to like elements. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It is apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the embodiments of the invention.

FIG. 1: Shows and illustrates a network environment (100), for enabling an optics based compute system, according to one embodiment of the invention.

FIG 2: Shows and illustrates a block diagram of an assembly system, according to one embodiment of the invention.

FIG. 3: Shows and illustrates a diagram for construction and assembly of an optics based compute system, according to one embodiment of the invention.

FIG. 4: Shows and illustrates a diagram for construction and assembly of an optics based compute system based on two-way configuration, according to one embodiment of the invention.

FIG. 5: Shows and illustrates a diagram for construction and assembly of an optics based compute system based on one-way configuration, according to one embodiment of the invention.

FIG. 6: Shows and illustrates a diagram for implementing an optics based compute system, according to one embodiment of the invention.
FIG. 7: Shows and illustrates a flow chart for the system and the method steps for enabling construction and assembly of an optics based compute system, according to one embodiment of the invention.

FIG. 8: Shows and illustrate 3D Stacking of LightCompute™ Processor Legos in a server blade.

FIG 9: Shows and illustrate cross-section view of the hexagon assembly. Optical Engines reflowed on interposer transmitting/receiving via prisms and glass cap.

FIG 10: Shows and illustrate Processor-to-Processor interconnect possibilities with one embodiment vs. traditional rack-to-rack distributed computing system.

DETAILED DESCRIPTION OF THE INVENTION:

The present invention discloses a system and method for enabling construction and assembly of an optics based compute system. More specifically, the invention describes a system and method for enabling high-performance computing (HPC) systems based on construction and assembly of an optics based compute system. The optics based compute system may comprise one or more compute system (M). The said compute system may be modular compute system.

Further, enabling construction and assembly of the optics based compute system comprises at least one memory to store instructions and at least one processor execute the instructions, in order to automate the process of construction and assembly of the optics based compute system, wherein the method comprises transmitting one or more signals from at least one of a plurality of components placed on a interposer of a hybrid 3D transceiving module. The method may also include controlling, by a processor, an optical channel based on the transmitted one or more signals.

Further, the invention comprises enabling inter module and intra module, reception of the one or more transmitted signals. The method may further comprise, providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module.

In one aspect the present invention provides a system for enabling high-performance computing systems or SIP (FIGS 6, 8-10) based on construction and assembly of an optics based compute system (FIGS 2-5).

High-performance computing systems
The high-performance computing systems (HPC System) of the present invention is designed for performing high performance computing applications. In one embodiment the HPC System comprises “LightCompute™” System developed by the Applicant. The said “LightCompute™” System involves and is based on “optics based compute system” the design, construction, assembly with communication and enabling details are described in the present invention.

To supplement the above said HPC system which is designed for high performance computing applications, the present invention develops and provides a high data rate communication mechanism based on optical communication both for inter-system communication and intra-system communication with thermal stability. In one embodiment the above said high data rate communication mechanism comprises optical data communication mechanism which involves free space communication achieved by free space optics/optical (FSO) communication and/or achieved by free space optics/optical engine system (FSO Engine System). In one embodiment the optical interconnect and FSO engine system comprises “LightKonnect™” System developed by Applicant.

Compute System (M): The “LightCompute™ lego”
In one embodiment the “optics based compute system” of the present invention is the compute systems (M) which may be the “LightCompute™ lego” proprietarily developed by the Applicant. The “optics based compute system” of the high-performance computing (HPCs) systems of present invention comprises one or more compute systems (M), wherein the said one or more compute systems (M) comprises first compute system (M1), second compute system (M2),…….upto “n” numbers of such compute systems. In one embodiment each compute system (M1 or M2,….or Mn) is a hexagonal modular compute system which is like a hexagonal “lego”. In one embodiment the above said lego like hexagonal modular compute system (M1 or M2,….or Mn) are termed as “LightCompute™ lego”. In one embodiment the said hexagonal modular compute system (lego) comprises one or more processor and/or one or more memory, communication interfaces, peripherals equipments and devices all connected in a network which are outline in Figures 1-2 and further described in paragraphs below.

In one embodiment each modular computing system (each lego) comprises reconfigurable processor such as FPGA and memory.

The purpose of the present invention is to provide a chip-to-chip, module-to-module, high speed, free-space optical interconnect and its applications using a System in Package (SIP). It primarily covers the design and functionality of LightKonnect™ - free-space optical engine component and describes the LightCompute™ system of legos, which is the complete system utilizing the capabilities of the optical engine. LightCompute™ is a high performance, low power, optically interconnected array of System-in-Package (SIP) module that can be scaled up for future computing needs.

“LightCompute™” System:
The “LightCompute™” System comprises “LightCompute™ legos” and “LightKonnect™” and other components. In one embodiment, a plurality of “LightCompute™ legos” are interconnected with Free Space Optic (FSO) interconnects and optical engine which is termed as “LightKonnect™” for signal and/or data exchange and communication and thus forms the said LightCompute™ system for high performance computing (HPC).

LightCompute™ system consists of lego-like optoelectronic processors (“LightCompute™” lego) and chip-to-chip, module-to-module high bandwidth free-space interconnects achieved by optical engine “LightKonnect™” for HPC and datacenters. At the heart of the HPC system, the above said proprietary high speed, free space optical interconnect “LightKonnect™” is closely integrated with reconfigurable compute engines (FPGAs)/other application processors. “LightCompute™” is the complete HPC system utilizing the capabilities of the optical engine (“LightKonnect™”). The FPGA, multiple Optical Engines, and peripherals are reflow soldered on an Organic Interposer as a SIP module. These modules can be configured in a 3D array with predefined orientation to enable free space optical coupling between SIPs. Data transfer rate between them is only limited by the on-chip SerDes of the logic devices. LightCompute™ is a high performance, low power, optically interconnected array of System-in-Package (SIP) module that can be scaled up for future computing needs. The complete LightCompute™ system and SIP are further described below and shown in Figures 6, 8-10.

Reference will now be made in detail to the description of the present subject matter, one or more examples of which are shown in figures 1-10. Each example is provided to explain the subject matter and not a limitation. Various changes and modifications obvious to one skilled in the art to which the invention pertains are deemed to be within the spirit, scope and contemplation of the invention.

In this description, the word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

In this description, the term “application” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an “application” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed. Further, in this description “ application” may include files with executable content created based on Hardware description language (HDL), where HDL is a specialized computer language used to program electronic and digital logic circuits. The structure, operation and design of the circuits are programmable using HDL. HDL includes a textual description consisting of operators, expressions, statements, inputs, and outputs.

The term “content” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, “content” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

The term “Switch IC” may include IC switching voltage regulators are integrated circuits (ICs) that store energy in an inductor, transformer, or capacitor and then use this storage device to transfer energy from the input to the output in discrete packets over a low-resistance switch. Voltage regulators may further include buck converter, boost converter, buck-boost converter etc. Further, the switch ICs may have different packaging verities, for example Dual in-line packages (DIP) can be made of ceramic (CIP) or plastic (PDIP). Quad flat packages (QFPs) contain a large number of fine, flexible, gull wing shaped leads. SC-70, one of the smallest available IC packages, is well-suited for applications where space is extremely limited. Small outline (SO) packages are available with 8, 14, or 20 pins. Transistor outline (TO) packages are commonly available. TO-92 is a single in-line package used for low power devices. TO-220 is suitable for high power, medium-current, and fast-switching products. TO-263 is the surface-mount version of the TO-220 package. And other IC packages for IC switching voltage regulators include shrink small outline package (SSOP), small outline integrated circuit (SOIC), small outline package (SOP), small outline J-lead (SOJ), discrete package (DPAK), and power package (PPAK).

The term “LASER driver” laser diode controllers are uniquely designed to drive a laser diode by providing a current instead of a voltage to the laser diode. They typically have a “soft start” to avoid damaging the laser diode while being powered on or off, transient protection, as well as a high modulation bandwidth – often 150 kHz or more. Further, Laser diode drivers are sometimes also referred to as current drivers, current controllers or laser diode controllers and the names are used almost interchangeably. All laser diodes, also called diode lasers or semiconductor lasers, require a laser diode driver to operate. Throughout the disclosure LASER or laser may refer to laser diodes. Lasers emit optic signals proportional to the input current leveraged by the laser driver.

The term “PIN” may include the PIN diode, which is one type of photo detector, used to convert optical signal into an electrical signal. The PIN diode comprises of three regions, namely P-region, I-region and N-region. Typically, both the P and N regions are heavily doped due to they are utilized for Ohmic contacts. The intrinsic region in the diode is in contrast to a PN junction diode. This region makes the PIN diode a lower rectifier, but it makes it appropriate for fast switches, attenuators, photo detectors. Further, PIN produces electrical current proportional to the magnitude of the received optic signal.

The term “TIA” may include Trans Impedance Amplifier (TIA), which is a converter circuit which converts the input current to a proportional output voltage. When current flows through a resistor it creates a voltage drop across the resistor which will be proportional to the value of current and the value resistor itself. Here, assuming the value of resistor to be ideally constant , hence easily use Ohms Law to calculate the value of current based on the value of Voltage. This is the most basic Current to Voltage Converter, and since a resistor (Passive element) is used to accomplish the task it may be called as a Passive Current to Voltage Converter. Further, transimpedance amplifier is an active current to voltage converter since it uses an active component like Op-Amp to convert the input current to a proportional output voltage. It is also possible to build active I to V converters using other active components like BJTs, IGBTs, MOSFETs etc. The most commonly used Current to Voltage converter is the transimpedance Amplifier (TIA).

The “Interposer” may include a silicon chip that can be used as a bridge or a conduit that allows electrical signals to pass through it and onto another element. Interposers are normally very frequently used in multi die chips or boards. The job of an interposer is to either spread the signal to a wider pitch or take the connection to a different socket on the board. The major benefit of sign interposer as opposed to stacked die and wires is that it offers a larger conduit or bridge of the signal to flow through, ensuring that the distance between the IP blocks in the system has been shortened and that the resistance/capacitance delay has been reduced down to a minimum. Interposers can be made from silicon or organic material, but their purpose remains the same.

Silicon bridging is quickly becoming one of the most popular and frequently opted for choices when it comes to packaging. These are essentially links that are attached to the substrate by Through Silicon Vias or TSVs. The interposer can then be metalized from the top, bottom, and side to connect it to the surrounding components of the system. This makes interposers a versatile and adaptable packaging system. Further, Silicon interposers offer significant reduction in the size of your system as opposed to Printed Circuit Boards or PCBs as opposed to the 75/75 micron linewidth and space, interposers lie at a mere 5/5 micron. It also accounts for an improvement in the performance of the device as the interconnect are formed using semiconductor technology. With the reduction in size and the improvement in efficiency, your system starts to waste a lot less power. It is also extremely easy to pre-process TSV substrates and store them for later use whenever there is a need for rapid prototyping at a short time’s notice. As such, silicon interposers make for the perfect companion when it comes to heterogeneous systems and technologies.

In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).

Figure-1:

FIG. 1 illustrates network environment, for enabling an optics based compute system. Referring now to the drawings, FIG. 1 illustrates an environment (100) within which reconfigurable and flexible modular compute (M) (“LightCompute™ lego”) may be implemented. The environment (100) may include a first modular compute system (M1) , a second modular compute system (M2), one or more peripheral equipments (105), opto-electronic connector (107), a network (109), and optionally one or more remote user device (111), all interconnected by the said network (109).

In one embodiment, said modular compute (M) comprises plurality of Modular compute systems (Mn) which comprises two or more of modular system (M1, M2,….Mn), wherein “n” represents the total number of modular systems (Hexagonal legos) that can be connected and present in the system of the invention, wherein “n” is any integer number of the counting system.

However, only one modular system can also be used in an environment for computing and in that case “n” is 1.

Further in one embodiment, the modular compute (M) is provided in a special geometrical configuration such as clusters, each cluster comprising plurality of modular systems (as shown in Figure 6).

Further the first modular compute system (M1) may communicatively coupled to the second modular system (M2) through the opto electronic connector (107). In one embodiment, the opto electronic connector (107) involves an optical interconnect “LightKonnect™” System. In some example embodiments, the first modular system (M1) and the second modular system (M2) may also be referred as system. Further details regarding the modular compute (“LightCompute™ lego”) and optical interconnect system (“LightKonnect™” ) may be found in the later part of the disclosure.

In an example embodiment one or more peripheral equipment (105) may receive and/or send data through the opto-electronic connector (107) and/or the network (109). In some example embodiments I/O ports on the compute system (M1, M2) enabled communication via the network (109) and/or the opto-electronic controller (107). Peripheral devices may include but not limited to keyboard, mouse, touch screen, pen tablet, joystick, MIDI keyboard, scanner, digital, camera, video camera ,microphone monitor, projector, TV screen, printer, plotter, speakers, external hard drives, media card readers, digital, camcorders, digital mixers, MIDI equipment and the like.

The network (109) may include the Internet or any other network capable of communicating data between devices. Suitable networks may include or interface with any one or more of, for instance, a local intranet, a Personal Area Network (PAN), a Local Area Network (LAN), a Wide Area Network (WAN), a Metropolitan Area Network (MAN), a virtual private network (VPN), a storage area network (SAN), a frame relay connection, an Advanced Intelligent Network (AIN) connection, a synchronous optical network (SONET) connection, a digital T1, T3, E1 or E3 line, Digital Data Service (DDS) connection, Digital Subscriber Line (DSL) connection, an Ethernet connection, an Integrated Services Digital Network (ISDN) line, a dial-up port such as a V.90, V.34 or V.34bis analog modem connection, a cable modem, an Asynchronous Transfer Mode (ATM) connection, or Fiber Distributed Data Interface (FDDI) or Copper Distributed Data Interface (CDDI) connection. Furthermore, communications may also include links to any of a variety of wireless networks, including Wireless Application Protocol (WAP), General Packet Radio Service (GPRS), Global System for Mobile Communication (GSM), Code Division Multiple Access (CDMA) or Time Division Multiple Access (TDMA), cellular phone networks, Global Positioning System (GPS), cellular digital packet data (CDPD), Research in Motion, Limited (RIM) duplex paging network, Bluetooth radio, or an IEEE 802.11-based radio frequency network. The network (109) can further include or interface with any one or more of an RS-232 serial connection, an IEEE-1394 (Firewire) connection, a Fiber Channel connection, an IrDA (infrared) port, a SCSI (Small Computer Systems Interface) connection, a Universal Serial Bus (USB) connection or other wired or wireless, digital or analog interface or connection, mesh or Digi® networking. In some example embodiments, network may further include free space communications.

In an alternative embodiment, dedicated hardware implementations, such as application specific integrated circuits, programmable logic arrays and other hardware devices, can be constructed to implement one or more of the methods described herein. Applications that may include the apparatus of various embodiments can broadly include a variety of electronic and computer systems. One or more embodiments described herein may implement functions using two or more specific interconnected hardware modules or devices with related control and data signals that can be communicated between and through the modules, or as portions of an application-specific integrated circuit. Accordingly, the present system encompasses software, firmware, and hardware implementations.

In an example embodiment, one or more remote device (111) may be communicatively coupled to the compute system (M1 and/or M2 and/or …Mn) via the opto-electronic connector (107) and/or the network (109). The user device (111) may include mobile phone, laptops, desktops and the like. In some example embodiment, the remote device (111) may receive a plurality notifications based on one or more functions associated with the system (M2 and/or M1 and/or Mn). In some other example embodiment, the scenario may comprise one or more systems connected through at least one opto-electronic coupler and/or at least one network to enable construction of flexible computes in a at least one topology.

Figure-2:

FIG 2 illustrates a block diagram of an assembly system (200) that enables construction and configuration of the compute system (M1 and/or M2) is described herein. The assembly system (200) comprises one or more processor (201), one or more memory (203) and one or more communication interface (205).

In accordance with an embodiment, the processor (201) may be of any type of processor, such as “n-bit processors” . Where value of n may be 2 x, whereas values of x may range from 4 to 8. Processor types other than these, as well as processors that may be developed in the future, are also suitable. The processor may include general processor such as x86, x86-64, ARM, RISC-V, ISA based processors, Digital Signal Processing (DSP) chip, an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Arrays (FPGAs), microcontroller firmware , boot loader or a combination thereof. Mainly, the processor (201) be used for automating the constriction and assembly of the optics based compute system (M1 and/or M2 and/or Mn). Throughout the disclosure the compute system and the optics based compute system may interchangeably be used and may also be referred as the system (M1 and/or M2).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and anyone or more processors of any kind of digital computer. Generally, a processor receives instructions and data from a read only memory or a random-access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer also includes, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio player, a GPS receiver, to name just a few. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The memory may be a non-transitory medium such as a ROM, RAM, flash memory, etc. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

The processes and logic flows described in the specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

In accordance with an embodiment, the memory (203) includes both dynamic memory (e.g., RAM, magnetic disk, writable optical disk, NVMe, SSD etc.) and static memory (e.g., ROM, CD-ROM, etc.) for storing executable instructions that when executed perform the inventive steps described further in the document. Mainly, the memory (203) be used for storing set of instructions coupled to a hardware for enabling construction and assembly of an optics based compute system.

In accordance with an embodiment, network includes one or more networks such as a data network, a wireless network, a telephony network, or any combination thereof. In some example embodiment, the assembly system (200) may construct and configure the compute system (M1 and/or M2 and/or Mn) based on the processor (201), the memory (203) and the communication interface (205). In some example embodiment, the assembly system (200) may comprise one or more robots which have at least one processor (201) and which execute an assembly process based on a set of static instructions stored in memory and a set of dynamic information obtained from the one or more communication interfaces (205). In some example embodiment, the assembly system (200) may construct the compute system (M1 and/or M2 and/or Mn) in one stage or multiple stages of assembly process. The process of construction and assembly of the compute system (M1 and/or M2 and/or Mn) is further described through assembly of an optics based compute system (FIGS 3-6).

As stated above, the LightCompute™ system consists of lego-like optoelectronic processors (“LightCompute™” lego modular compute systems M1/M2/Mn) and chip-to-chip, module-to-module high bandwidth free-space interconnects achieved by optical engine “LightKonnect™” for HPC and datacenters.

Figure-3:

FIG. 3 illustrates a diagram for construction and assembly of an optics based compute system (M1 and/or M2 and/or Mn) which may be used in a HPC system involving free space optical interconnect for data and/or signal communication according to one embodiment of the invention. In one embodiment, this optics based compute system may involves the above said proprietary high speed, free space optical interconnect “LightKonnect™” which is closely integrated with reconfigurable compute engines (FPGAs)/other application processors. “LightCompute™” is the complete HPC system utilizing the capabilities of the optical engine (“LightKonnect™”).

The construction and assembly of an optics based compute system (M1 and/or M2 and/or Mn) of the HPC system involving free space optical (FSO) interconnect and FSO engine comprises a plurality of first components, plurality of second components, plurality of third components, electrical bumps (311a to 311o), interposer (317), glass block (321) as shown in FIG. 3. The plurality of first components includes a switch IC (301), associated with a LASER driver (303), a LASER (305), a trans-impedance amplifier i.e TIA (307) and a PIN diode (309). The plurality of first components is connected to a plurality of second components via one or more electrical bumps (311a to 311o). In some example embodiments, number of electrical bumps connecting the first plurality of components and the second plurality of components may vary dynamically based on applications.

The plurality of second components may comprise a plurality of alternative layers of Metal (313) and Redistribution Layer i.e RDL layers (315). In one embodiment the second plurality of components comprise four layers of metal (313) viz. METAL1 (313d), METAL2 (313c), METAL3 (313b), METAL4 (313a). In one embodiment the second plurality of components comprise four layers of RDL (315) viz. RDL1 (315d), RDL2 (315c), RDL3 (315b), RDL4 (315a). In some example embodiments, the layers of metal may be configured as shown in Fig. 3.

As shown the Fig. 3 indicates Metal layer4 (313a) of the second plurality of components is connected to the plurality of first components through the one or more electrical bumps (311a to 311o). Further, a RDL4 (315a) may be sandwiched between the metal layer4 (313a) and a metal layer 3 (313b). Similarly, a RDL3 (315b) is sandwiched between the metal layer3 (313b) and metal layer2 (313c), a RDL2 (315c) is sandwiched between the metal layer2 (313c) and a metal layer1 (313d). In some example embodiments, a RDL1 (315d) layer may be sandwiched between an interposer (317) and the metal layer1 (313d).

The interposer (317) may comprise one or more through silicon vias (i.e. TSV), for examples (319a – 319d). In some example embodiments, the interpose (317) is sandwiched between the RDL1 (315d) of the plurality of second component and a plurality of third component.

The plurality of third component comprises a glass block (321), signal optimizers (i.e. 323a and 323b), dynamic channel holders (i.e. 325a and 325b), inter-system channels (i.e. 327a and 327b), intra-system channels (i.e. 329a and 329b) and system holders (i.e. 331a and 331b).

Further, the construction and assembly of the compute systems ((M1 and/or M2 and/or Mn) of a HPC system involving free space optical interconnect comprises enablement of computational unit and communicational unit based on the first plurality of components, the second plurality of components and the third plurality of components. In some example embodiment, the switch IC (301) of the first plurality of components may be the computational unit. The switch IC (301) may include at least one processor, at least one memory and communication interface (Not shown). In some example embodiment, the at least one processor, memory and a communication interface associated with the switch IC (301) may be similar to the components of the system (200) as shown in fig. 2. In some example embodiments, the switch IC (301) may remotely be operated by users based on configuration of the user interface. The applications of this feature may be observed on data centers, which may reduce robust and complex architecture and application to a user friendly and simple modular architecture.

In some example embodiment, the functions of the communication unit are enabled by joint execution of the first plurality of components, the second plurality of components and the third plurality of components. The enabled communication may be divided into inter-system communication and intra-system communication. According to some example embodiments, intra-system communication comprises transmitting a signal from signal a laser driver (303) complemented LASER (305). The transmitted signal is passed through the second plurality of components and the third plurality of components, wherein the transmitted signal traverses from the intra-system channel (329b), through the glass block (321) and another intra-system channel (329a). Further, the transmitted signal is received by the PIN diode (309) and the received signal is amplified by the trans-impedance amplifier (TIA) (307). In some example embodiment, based on the received signals the switch IC (301) may execute some instructions.

In some example embodiments, the inter-system communication is enabled by co-coordinated action by the first plurality of components, the second plurality of components and the third plurality of components. The transmitted signal from the LASER (305) traverses the intra-system channel (329b) and reaches the inter-system channel (327b), through the glass block (321) after the transmitted signal has been configured by the optimizer (323b). In some example embodiments, the dynamic channel holder (325b) may be used to align the inter-system channel (327b) to a network that exists the compute system (M1 and/or M2 and/or Mn). In some other example embodiment, the transmitted signal may from any other compute system via the network may be received using the inter-system channel (327a) and the received signal may further be configured by the optimizer (323a) and sent to the PIN (309) via the glass block (321) and the intra-system channel (329a). In some example embodiments, the dynamic channel holder (325a) may be used to align the inter-system channel (327a) to the external network.

In some example embodiment, the modular compute system (M1 and/or M2 and/or Mn) is constructed based on multiple techniques of fabrication at different stages of assembly. The same may be observed in the first plurality of components, the second plurality of components and the first plurality of components. Further, the construction and assembly employs vertically stacking integrated circuits (ICs) or circuitry to achieve higher performance, increased functionality, lower power consumption, and a smaller footprint. Hence this construction and assembly may be referred as 3D hybrid model for construction and assembly. In some example embodiments, the modular compute system (M1 and/or M2 and/or Mn) may be attached to a network of circular using the system holders (331a and 331b).

In some example embodiments, the plurality of first components enables computation (i.e switch IC 301) and enables communication, wherein transmission may be initiated by the laser driver (303) and the laser (305) and the reception is executed by the PIN (309) and the TIA (307). Further, the second plurality of components complement the first plurality of components and the third plurality of components by providing electrical inter connects. The electrical bumps may be used to connect the first plurality of components and the second plurality of components. In some example embodiments, wire bonds may be used. The electrical inter connects are enabled by the alternate layers of metals (i.e. 313a-313d) and Redistribution Layer (i.e. 315a-315d). Further, the through silicon via (i.e. TSV 319a-319d) placed in the interposer (317), electrically interconnects and provides structural strength to the construction and the assembly.

In some example embodiment, the glass block (321) may be attached to the second plurality of components and the dynamic channel holders (325a and 325b) may be attached to the glass block (321) based on the v-groves. The v-grooves are accurate fabricated structures, when a fiber cross section is fitted in, it provides exact point contact giving optical axis height constantly across no of fibers. The optimizers (323a and 323b) may be used to configure transmission and/or reception of signals through inter-system channels (i.e. 327a and 327b) and/or intra-system-channels (i.e. 329a and 329b). The optimizers (323a and 323b) may include precise assembly of micro lens array and prism. The dynamic channel holders (325a and 325b) configure the inter-system channels (327a and 327b) based on instructions provided by the processor associated with the switch IC (301). Further, inter-system channels (327a and 327b) may be optical fibers and intra-system channels (329a and 329b) may be a hollow space, for the transmission and reception of the optical signals through the second plurality of components, which is linked to the first plurality of components and the second plurality of components. The above mentioned construction and assembly of the modular compute system (M1 and/or M2 and/or Mn) may further be enabled in at least two configurations, as explained in FIG. 4 and Fig. 5.

Figure-4:

FIG. 4 illustrates a diagram for construction and assembly of an optics based compute system of the modular compute system (M1 and/or M2 and/or Mn) based on a first configuration (two-way configuration), according to one embodiment of the invention. The first configuration as shown in Fig. 4 illustrates dual plane communication. The first configuration includes a switch IC (401) coupled with a heat sink (406), may be placed on an interposer (417). Further, transmission of signals enabled by a laser driver (403) associated with a LASER (405), is transmitted through an intra-system channel (429b), further the transmitted signal is configured by an optimizer (423b), and transmitted to a network through an inter-system channel (427b). In some example embodiments, the inter-system channel (427b) may be controlled by a processor complemented dynamic channel holders (425c and 425d). Further, according to the first configuration, the interposer is considered as a reference to differentiate planes.

In some example embodiment, the modular compute system (M1 and/or M2 and/or Mn) may receive the transmitted signals from another compute system (not shown). Further, the received signal may be configured by dynamic channel holders (425a and 425b) at an inter-system channel (427a) stage and further configured by an optimizer (423a). The configured signal is delivered to a PIN diode (409) through an intra-system channel (429a) of the interposer (417) and the received signal by the PIN diode (409) may be amplified by the Trans-Impedance Amplifier (407). The Switch IC (401) may execute at least one instructions based on information obtained as output from the TIA (407). Further, a plurality of electrical bumps (i.e. 411a-411p) may be used to place the PIN (409), the TIA (407), the Switch (401), the LASER driver (403) and the LASER (405) on the interposer (417) and system holders (431a and 431b) may be used to place the compute system (M1 and/or M2 and/or Mn) on a network.

In some example embodiments, most of optics based communication set up may be observed in a first plane (i.e. lower plane) of the dual plane. The optics based communication set may include V-groves and Single Mode Fiber (SMF) enabled dynamic channel holders (i.e. 425a-425d) inter-system channels (427a and 427b) (i.e. optical fiber), the optimizers (423a and 423b) (i.e. combination of lens and prism). Further, compute and electronic based communication set may be observed in a second plane (i.e. upper plane). The compute set may include the heat sink (406) enabled switch IC (401), wherein the heat sink (406) is used to boost computational capacity of the switch IC (401) by eliminating the thermal stress and other hindrances. Further, the electronics based communication set may include the PIN (409), the TIA (407), the LASER driver (403), the LASER (405), the electrical bumps (411a-411p). Through the disclosure the disclosure the electrical bumps may include solder bumps. The plane of reference, the interposer (417) may include embedded interconnects as shown in the FIG. 4 and hollow intra-system channels (429a and 429b). In some example embodiments, the system holders (431a and 431b) may be present in the second plane, however based on requirements the system holders (431a and 431b) may be placed on the first plane or reference plane and any combination of thereof.

Figure-5:

FIG. 5 illustrates a diagram for construction and assembly of an optics based compute system of the compute system (M1 and/or M2 and/or Mn) based on a second configuration (one-way), according to one embodiment of the invention. The second configuration illustrates a single plane communication and computation. A heat sink (506) enabled switch IC (501), a LASER driver (503), carriers (510a and 510b), a LASER (505), a TIA (507), a PIN (509), optimizers (523a and 523b), inter system channels (527a and 527b), intra system channels (529a and 529b), dynamic channel holders (525a-525d) are placed on an interposer (517) through a plurality of solder bumps (511a-511p) as shown in the Fig. 5. In some example embodiments, the interposer (517) may be conserved as reference plane.

The optic based and electric based communication set may be placed on any side of the reference plane. In some example embodiments, electric based set employs solder bump based interconnections and whereas the optics based set employs wire-bound inter connections. In addition of the carrier circuits (510a and 510b) electrically connected via solder bumps (511a-511p) to the PIN (509) and the LASER (505) enables single planar communication and computation. In some example embodiments, the carriers (510a and 510b) overcome the need for a hollow inter-system channels shown in FIGS. 3-4. The carriers (510a) enable perpendicular reception of optical signals by the PIN (509) and the carriers (510b) enable perpendicular transmission of optical signals by the LASER (505). In some example embodiments, the system holders (531a and 531b) may be present in the second plane, however based on requirements the system holders (531a and 531b) may be placed on the first plane or reference plane and any combination of thereof.

In some example embodiments, the reference plane may be considered as a platform for placing various elements of assembly. Referring to Fig. 4, the elements are distributed on both planes of the platform, whereas Referring to Fig. 5, the elements are distributed on one of the planes of the platform. Further, according to some example embodiment, a zero-polymer circuit board (PCB) like structured may be constructed, following the construction and assembly methodology observed in the Fig. 3. In the zero-PCB like structures optical interconnects and channels would be pre-determined and compute systems may be assembled in a modular fashion, to create a network of an optics based compute systems. This concept is further enabled in the Fig. 6.

Figure-6:

FIG. 6 illustrates a diagram for implementing an optics based compute system comprising of a plurality of modular compute systems (M1 and/or M2 and/or Mn), according to one embodiment of the invention. In an example embodiment, one or more clusters are placed on a platform, whereas each cluster may have one or more pre-determined slots for the compute system (M1and/or M2 and/or Mn). Further, each slot may be pre-configured to enable inter system optic based communication. For example, cluster A comprises seven slots (601a, 603a, 605a, 607a, 609a, 611a, and613a) and each slot may be interconnected using the optics based communication channel (615a) as shown in the Fig.6. Similarly, cluster B comprises seven slots (601b, 603b, 605b, 607b, 609b, 611b, and 613b) and each slot may be interconnected using the optics based communication channel (615b) as shown in the Fig.6. In some example embodiments, inter cluster communication may be enabled based on the same optic based communication channels. For example, the compute system slot (611a) of cluster A may be connected to the compute system slot (603b) of the cluster B are connected based on the pre-determined optics based communication channel (i.e. 615a and/or 615b).

In the above shown slots of each Cluster A and Cluster B, modular compute systems M1, M2,……..M7) can be assembled. For example, cluster A may comprise seven modular systems (legos) viz. (M1, M2, M3, M4, M5, M6, and M7) placed on seven slots (601a, 603a, 605a, 607a, 609a, 611a, and 613a) respectively. Similarly, cluster B comprises may comprise seven modular systems (legos) viz. (M1, M2, M3, M4, M5, M6, and M7) placed on seven slots (601b, 603b, 605b, 607b, 609b, 611b, and 613b) respectively.

In some example embodiment, the Fig. 6 may be explained with reference to Fig. 3-6. Referring to Fig. 3, consider the first plurality of components and the second plurality of components as modular unit and the third plurality of unit as static unit. In such a case, the third plurality of components are represented by the pre-determined optics based communication channels and the compute system slots refer to pouches or slots which enabled plug and play feature to the modular unit comprising the first plurality of components and the second plurality of components. Referring to Fig. 3 the platform may be referred as the reference plane and the optics based communication set may be placed under the compute system slots and in Fig. 4 the optics based communication set may be placed along the compute system slots. Throughout the disclosure the word ‘set’ and ‘unit, may interchangeably be used.

In some example embodiments, the network of modular compute systems associated with a mega-system enhance the computational ability of the mega system ‘n’ times and the optic based communication enabled through inter-system channels and intra-system channels cater data at a required rate to, increase number of instructions executed per cycle by the mega system and further provide an efficient resource utilization for the mega system. In some example embodiments, mega systems may be servers of a data centers and Fig. 6 may indicate a rack of the server.

In some example embodiments, in one slot more than one modular unit may be placed co-axial to the vertical axis. For example, consider the slot (601a). The slot (601a) may hold one or more modular unit, whereas each modular unit may execute different operations. In case say the slot (601a) has three modular units. In some example embodiment, based on requirement the slot (601a) may comprise a centra processing unit (CPU), a graphic processing unit (GPU), a Field Programmable Gate Arrays (FPGA) or other related units. Placing of multiple modular units in a single slot may be referred as ‘3D stacking’.

Further, in some example embodiments, the modular units may be placed in a network such that at least two modular units communicate through free space optical (FSO) coupling. For example, the slot (601a and 603a) are configured to have any one side of the slot (i.e. any edge of 601a) parallel and co-axial to any one side of the slot (i.e. any edge of 603a). In such cases, the free-space coupling enabled at the edges may be used for communication.

The slots may be configured based on requirement of topologies. The platform comprising the slots may have vertical stacking of modular units in each of the slots, supported by edges based free-space coupling for communication. Further, multiple slots on the platform enable horizontal stacking of the modular units enabled by the static unit (i.e. free space coupling and/or opto-electronic coupling) as shown in Fig. 6.

Total number of tasks associated with a process may be distributed to multiple modular units. The multiple modular units are associated with free space coupling for communication. Thereby, performance centric modular units execute assigned tasks and two way communications for the same is enabled by the free-space coupling. This method ensures compute distribution, hence better heat distribution throughout the system. In some example embodiments, the multiple modular units connected through free-space coupling functions as a single unit. Lego compute blocks can be assembled and rearranged in various topologies and configurations as per computational complexity and the requirement of the topology.

Figure-7:

In another aspect the invention provides a process (method) for enabling high-performance computing systems (HPC Systems) based on construction and assembly of an optics based compute system as described above with reference to FIGS 1-6. The communication of signal and/or data between the compute systems (M1, M2,….Mn) and/or between the clusters A and B, each cluster comprising compute systems (M1, M2,….Mn) as described above in FIG. 6 can be achieved by free space optical communication using opto-electrical connector (107) and/or a transceiver module. The transceiver module may comprise one or more optical engine.

In one embodiment the above method is performed according the method steps (701-707) as illustrated in the flow chart of FIG. 7. FIG. 7 illustrates a flow chart for enabling construction and assembly of an optics based compute system. In accordance with an embodiment, at step 701 the method includes transmitting one or more signals from at least one of a plurality of components placed on an interposer of a hybrid 3D transceiving module.

In accordance with an embodiment, at step 703 the method includes configuring and/or controlling, by a processor, an optical channel based on the transmitted one or more signals.

In accordance with an embodiment, at step 705 the method includes enabling inter module and intra module, reception of the one or more transmitted signals.

In accordance with an embodiment, at step 707 the method includes providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module.

The method comprises transmitting one or more signals from at least one of a plurality of components placed on an interposer (317) of a hybrid 3D transceiving module, controlling, by a processor, an optical channel based on the transmitted one or more signals, enabling inter module and intra module, reception of the one or more transmitted signals and providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module. The above method is performed in the optics based compute system as described above which comprises electrical bumps (311a to 311o), interposer (317), glass block (321), a switch IC (301), associated with a LASER driver (303), a LASER (305), TIA (307) and a PIN diode (309) [FIGS 3-6].

The application of above modular compute system, the construction and assembly, communication and the method as described above in a computing environment such as environment (100) such as datacenter enables high speed data transfer and enable high performance making the system a HPC system.

In one aspect the invention discloses and provides a “modular distributed computing system” interconnected with high speed chip-to-chip, module-to-module optical interconnects.

In one embodiment, the optical interconnect acts as a replacement for on-chip/on-board highspeed data bus. Optical interconnect between the processors can be communicating in free space, through waveguides, buried in a PCB or on system-in-package, on-chip or through fiber-optic cables.

In one embodiment, the optical interconnect may be packaged along with the bare die of the compute engine on the same package, interposer or the PCB.

Figure-8:

Referring FIG. 8 it shows and illustrate 3D Stacking of LightCompute™ Processor Legos in a server blade. In one embodiment, the said LightCompute™ Processor Legos is the optics based compute system of present invention as described above with reference to FIGS 3-6. In one embodiment, the said LightCompute™ Processor Legos is a modular compute system (M1 or M2, or …..Mn). Lego compute blocks can be assembled and rearranged in various topologies and configurations as per computational complexity and the requirement of the topology.

LightCompute™ system consists of lego-like optoelectronic processors and chip-to-chip, module-to-module high bandwidth free-space interconnects for HPC & datacenters. At the heart of this system, the proprietary high speed, free space optical interconnect “LightKonnect™” is developed which is closely integrated with reconfigurable compute engines (FPGAs)/other application processors. The FPGA, multiple Optical Engines, and peripherals are reflow soldered on an Organic Interposer (FIG.8) as a SIP module. These modules can be configured in a 3D array with predefined orientation to enable free space optical coupling between SIPs. Data transfer rate between them is only limited by the on-chip SerDes of the logic devices.

Design & Assembly of Legos
In addition to the design, construction, and assembly of optics based compute systems (Legos) as described above, further the compute system are presented in a complete system termed as LightCompute™ system, which is a high performance, low power, optically interconnected array of System-in-Package (SIP) modules that can be scaled up for future computing needs. LightCompute™ system combines an FPGA/custom application processor (of compute systems) with “LightKonnect™” multi-Terabit free space optical IO bus to obtain high performance/watt efficiency. By packaging optoelectronics with FPGAs, the present invention develops and provides a highly power-efficient distributed computing system.

The Applicant has developed an unique hexagonal package/board designs (patent pending) which enables the system of the present invention to achieve high bi-section bandwidth and higher low-latency redundancy channels between the processors in comparison to 2D-tile arrays, linear, ring or torus arrays.

The LightCompute™ system can be scaled by assembling self-similar (low-cost of manufacturing) SIPs. Each SIP comes pre-loaded with application libraries for AI/HPC example use-cases demonstrating compute-distribution among the legos achieving acceleration and power efficiency. These can be used as templates for building customer applications for standalone or array of legos.

Now referring FIG.8, it shows the arrangement of LightCompute™ Processor legos in forming a complete LightCompute™ system (800), which may be packaged as a SIP module. Basically, the LightCompute™ system (800) comprises:
- plurality of modular LightCompute™ legos (801),
- each lego comprising one or more FSO Optical Engine(s) (802),
- said plurality of legos arranged in a cluster (803) in a modular arrangement as shown in FIG. 8 (also FIG. 6).

In one embodiment, the each lego is designed in an unique shape i.e. hexagonal shape and is a modular computing system (M) which is the “optics based compute system” as described in paragraphs above with reference to FIGS 1-6. The said compute systems (M) comprises first compute system (M1), second compute system (M2),…….upto “n” numbers of such compute systems. In one embodiment each compute system (M1 or M2,….or Mn) is a hexagonal modular compute system which is like a hexagonal “lego”. In one embodiment the above said lego like hexagonal modular compute system (M1 or M2,….or Mn) are termed as “LightCompute™ lego” (801). In one embodiment the said hexagonal modular compute system (lego 801) comprises one or more processor and/or one or more memory, communication interfaces, peripherals equipments and devices all connected in a network which are outline in Figures 1-2 and further described in paragraphs above. In one embodiment each modular computing system (each lego) comprises reconfigurable processor such as FPGA and memory. In some example embodiment, each lego may include at least one processor, at least one memory and communication interface. In some example embodiment, the at least one processor, memory and a communication interface associated with the LightCompute lego may be similar to the components of the system (200) as shown in FIG. 2 and thus each “LightCompute™ lego” (801) may comprise one or more processor (201), one or more memory (203) and one or more communication interface (205), wherein the exemplary processor (201), memory (203) and communication interface (205) are as defined above. In some example embodiments, the LightCompute lego may remotely be operated by users based on configuration of the user interface. In one embodiment the processor may comprise a CPU, a GPU or a FPGA.

The FSO Optical Engine(s) (802) communicates High speed optical signals in free-space as an optical bus. It will be a transmitting or receiving module or both depending on the de-sign or configuration. It may contain laser drivers, lasers, photo detectors and signal ampli-fiers, lens and/or prism assemblies to send signals in free-space.

In one embodiment the said plurality of legos are arranged in a cluster (803) in a modular arrangement as shown in FIG. 8 wherein the communication between the lego to lego, module to module and also between the cluster to cluster for the transmission and receiving of data and signals from one processor to another processor may be achieved by free space communication with the help of optical interconnect component and 3D transceiver module. In one embodiment the said communication may be achieved by the communication mechanism as described above with reference to FIGS 3-6. In one embodiment the said communication also uses “LightKonnect™” optical interconnect.

In one embodiment, the above said legos arranged in a cluster (803) are further arranged in an array (804) i.e. an array of legos connected in three dimension (3D) by micro-optic free-space connectors. Here the communication happens between the logos in a cluster and also between the cluster to cluster arranged in a stack forming the array. The unique design and assembly of modular lego of present invention allow this communication efficiently in high speed.

The above array (804) of multiple clusters of legos may be placed in a server blade (805) and thus a HPC server blade (806) can be designed and constructed which is configured with free-space optical communication system of the invention as described above.

Figure-9:

FIG 9: Shows and illustrate cross-section view of the hexagon assembly (900). Optical Engines reflowed on interposer transmitting/receiving via prisms and glass cap. As can be seen n figure, the lego module at center comprises the processor (FPGA, 201), which also comprises memory. The module also comprises a prism (901) for modulation of signals. The module also comprises micro lens array (902). The module also comprises a free space optics (FSO) which may be a surface mounted device (SMD). The FSO SMD (903) allow communication of the lego module with other legos and within the logo. The FPGA, multiple Optical Engines, and peripherals are reflow soldered on an Organic Interposer as a SIP module. These modules can be configured in a 3D array with predefined orientation to enable free space optical coupling between SIPs.

Figure-10:

FIG 10: Shows and illustrate Processor-to-Processor interconnect possibilities with one embodiment vs. traditional rack-to-rack distributed computing system. As can be seen in the figure, in the LightCompute distributed computing system in the integrated racks the communication and signal exchange can be happened between processor to processor of the plurality of compute modules present on a single rack; and also communication and signal exchange can be happened between processor to processor of compute modules present in one rack to compute modules present in another rack. In contrast, in the traditional existing distributed computing system the communication is only possible between compute systems present in a single rack, wherein processor to processor between multiple racks is not possible.

BENEFITS & ADVANTAGES:

In summary, reconfigurable electronics provides the computing power and optics provides the interconnect and together, the 3D-System-in-Package (3D-SIP) provides up-to 20x performance1 at half the power in a small form factor offering high compute density needed in the data centers with increased flexibility in system design, topologies, architecture. This is a true heterogeneous integration of photonics and logic blocks that allows low-cost integration and mass fabrication.

Traditionally, multiple processors in a server blade, fixed on a PCB, connect with other processors through SFP “pluggable” board-to-board connectors that are bulky one-to-one active optical cables. The present invention provides a solution which offers a possibility of various topologies and communication networks between the processors with FSO optical bus as shown in Fig. 6 in an example embodiment of present invention. The optical technology disclosed in the present invention has three distinct differentiators:
(1) Creating a free space optical bus that connects to multiple processors simultaneously.
(2) Optics design in such a way that traditional semiconductor assembly processes can be followed.
(3) Modular design that can be scalable and configurable for processing and interconnects. Offers flexible/reconfigurable computing with multi Tbps interconnect (only limited by the on-chip SerDes, can be linearly scaled with more SerDes), in a compact form factor.

This type of system of legos can find huge applications in 5G edge computing, data centers, Internet Service Providers and Telecoms. LightCompute™ can help process huge volumes of data with real-time AI on video streams, AR/VR data streams, and provide intelligent switching capabilities, network packet security analysis, etc., all at low-power edge clouds. These low-power legos can also offer flexibility and easier reconfigurability of deployment of the computing infrastructure to adapt as per the changing needs at the customer-end.

The many features and advantages of the invention are apparent from the detailed specification, and thus, it is intended by the appended claims to cover all such features and advantages of the invention which fall within the true spirit and scope of the invention. Further, since numerous modifications and variations will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.
,CLAIMS:1. A system for enabling high-performance computing based on construction and assembly of an optics-based compute system (M1 or M2,…or Mn), wherein the said optics-based com-pute system comprises:
- one or more processor (201) which is reconfigurable,
- one or more memory (203) to store instructions, and
- one or more communication interface (205),
all assembled in an assembly and configured to enable chip-to-chip, module-to-module high bandwidth free-space interconnects and free-space optical communication;
wherein the said processor (201) executes the stored instructions of memory (203) in order to enable the compute system and automate the process of construction, assembly, and communication,
- an interposer (317);
- a plurality of first components which comprises a switch IC (301) associated with a LASER driver (303), a LASER (305), a trans-impedance amplifier (TIA 307) and a PIN diode (309);
- a plurality of second components which comprises a plurality of alternative layers of Metal (313) and Redistribution Layer i.e RDL layers (315);
- a plurality of third component which comprises a glass block (321), signal optimizers (323a and 323b), dynamic channel holders (325a and 325b), inter-system channels (327a and 327b), intra-system channels (329a and 329b) and system holders (331a and 331b),
wherein the plurality of first components is connected to a plurality of second components via one or more electrical bumps (311a to 311o); and
wherein co-coordinated action of said plurality of first components, plurality of second components, and plurality of third components enables inter-system and intra-system free-space communication of the said optics-based compute system (M1 or M2,…or Mn).

2. The system as claimed in claim 1, wherein the said alternative layering of Metal layers (313) and RDL layers (315) comprises:
- four layers of metal (313) viz. METAL1 (313d), METAL2 (313c), METAL3 (313b), METAL4 (313a), and
- four layers of RDL (315) viz. RDL1 (315d), RDL2 (315c), RDL3 (315b), RDL4 (315a),
wherein the layering is done by placing one layer of metal followed by one layer of RDL in alternative fashion.

3. The system as claimed in claim 2, wherein the in the said layering,
- RDL4 (315a) is sandwiched between the metal layer4 (313a) and the metal layer 3 (313b),
- RDL3 (315b) is sandwiched between the metal layer3 (313b) and the metal layer2 (313c),
- RDL2 (315c) is sandwiched between the metal layer2 (313c) and the metal layer1 (313d), and
- RDL1 (315d) is sandwiched between the metal layer1 (313d) and the interposer (317).

4. The system as claimed in claim 1, wherein the interposer (317) may comprise one or more through silicon vias (319a – 319d), and wherein the interpose (317) is sandwiched between the RDL1 (315d) of the plurality of second component and glass block (321) of a plurality of third component.

5. The system as claimed in claim 1, wherein the switch IC (301) of the first plurality of components is the computational unit which may include at least one processor (201), at least one memory (203) and communication interface (205), wherein the switch IC (301) is reconfigurable and may remotely be operated by users based on configuration of the user interface.

6. The system as claimed in claim 1, wherein the said intra-system communication comprises transmitting a signal from signal a laser driver (303) complemented by LASER (305), where-in the transmitted signal is passed through the second plurality of components and the third plurality of components, wherein the transmitted signal traverses from the intra-system channel (329b), through the glass block (321) and another intra-system channel (329a), and wherein the transmitted signal is received by the PIN diode (309) and the received signal is amplified by the trans-impedance amplifier (TIA) (307).

7. The system as claimed in claim 1, wherein the inter-system communication is enabled by co-coordinated action by the first plurality of components, the second plurality of compo-nents and the third plurality of components, wherein signal from the LASER (305) traverses the intra-system channel (329b) and reaches the inter-system channel (327b), through the glass block (321) after the transmitted signal has been configured by the optimizer (323b), wherein the dynamic channel holder (325b) may be used to align the inter-system channel (327b) to a network that exists the compute system (M1 and/or M2 and/or Mn).

8. The system as claimed in claim 1, wherein the inter-system communication comprises the transmitted signal from any other compute system via the network may be received using the inter-system channel (327a) and the received signal may further be configured by the opti-mizer (323a) and sent to the PIN (309) via the glass block (321) and the intra-system channel (329a), wherein the dynamic channel holder (325a) may be used to align the inter-system channel (327a) to the external network.

9. The system as claimed in claim 1, wherein the modular compute system (M1 and/or M2 and/or Mn) is constructed in a 3D hybrid model based on multiple techniques of fabrication at different stages of assembly which involves layering and/or vertically stacking integrated circuits (ICs) or circuitry to achieve higher performance, increased functionality, lower pow-er consumption, and a smaller footprint, and the modular compute system (M1 and/or M2 and/or Mn) may be attached to a network of circular using the system holders (331a and 331b).

10. The system as claimed in claim 1, wherein the said construction and assembly of an optics based compute system (M1 and/or M2 and/or Mn) may be configured in a first configuration (two-way configuration) or a second configuration (one-way configuration).

11. The system as claimed in claim 10, wherein the first configuration (two-way configuration), includes a switch IC (401) coupled with a heat sink (406), may be placed on an interposer (417), wherein the transmission of signals enabled by a laser driver (403) associated with a LASER (405), is transmitted through an intra-system channel (429b), further the transmitted signal is configured by an optimizer (423b), and transmitted to a network through an inter-system channel (427b), and wherein the inter-system channel (427b) may be controlled by a processor complemented dynamic channel holders (425c and 425d).

12. The system as claimed in claim 11, wherein the modular compute system (M1 and/or M2 and/or Mn) may receive the transmitted signals from another compute system, and wherein the received signal may be configured by dynamic channel holders (425a and 425b) at an inter-system channel (427a) stage and further configured by an optimizer (423a), wherein the configured signal is delivered to a PIN diode (409) through an intra-system channel (429a) of the interposer (417) and the received signal by the PIN diode (409) may be amplified by the Trans-Impedance Amplifier (407), and the Switch IC (401) may execute at least one in-structions based on information obtained as output from the TIA (407).

13. The system as claimed in claim 11, wherein a plurality of electrical bumps (i.e. 411a-411p) may be used to place the PIN (409), the TIA (407), the Switch (401), the LASER driver (403) and the LASER (405) on the interposer (417) and system holders (431a and 431b) may be used to place the compute system (M1 and/or M2 and/or Mn) on a network.

14. The system as claimed in claim 11, wherein the optics based communication set up of the system may be observed in a first plane (i.e. lower plane) of the dual plane, wherein the op-tics based communication set of the system may include V-groves and Single Mode Fiber (SMF) enabled dynamic channel holders (425a-425d), inter-system channels (427a and 427b) (optical fiber), the optimizers (423a and 423b) (combination of lens and prism);
or
the compute and electronic based communication set of the system may be observed in a second plane (i.e. upper plane) wherein the compute set may include the heat sink (406) enabled switch IC (401), wherein the heat sink (406) is used to boost computational capacity of the switch IC (401) by eliminating the thermal stress and other hindrances, PIN (409), the TIA (407), the LASER driver (403), the LASER (405), the electrical bumps (411a-411p).

15. The system as claimed in claim 10, wherein the second configuration (one-way config-uration) involves a single plane communication and computation which comprises a heat sink (506) enabled switch IC (501), a LASER driver (503), carriers (510a and 510b), a LASER (505), a TIA (507), a PIN (509), optimizers (523a and 523b), inter system channels (527a and 527b), intra system channels (529a and 529b), dynamic channel holders (525a-525d) are placed on an interposer (517) through a plurality of solder bumps (511a-511p).

16. The system as claimed in claim 15, wherein the interposer (517) may be conserved as reference plane, and wherein the optic based and electric based communication set may be placed on any side of the reference plane, and wherein the electric based set employs solder bump based interconnections and whereas the optics based set employs wire-bound inter connections.

17. The system as claimed in claim 15, wherein the carrier circuits (510a and 510b) electrically connected via solder bumps (511a-511p) to the PIN (509) and the LASER (505) enables single planar communication and computation.

18. The system as claimed in claim 15, wherein the carrier (510a) enables perpendicular recep-tion of optical signals by the PIN (509) and the carrier (510b) enables perpendicular trans-mission of optical signals by the LASER (505).

19. The system as claimed in claim 15, wherein the system holders (531a and 531b) may be present in the second plane, or the first plane or reference plane and any combination of thereof.

20. The system as claimed in claim 1, wherein the reference plane may be considered as a platform for placing various elements of assembly, wherein the elements may be distributed on both planes of the platform, or the elements may be distributed on one of the planes of the platform.

21. The system as claimed in claim 1, wherein a zero-polymer circuit board (PCB) like structured may be constructed, wherein the optical interconnects and channels may be pre-determined and the compute systems may be assembled in a modular fashion, to create a network of an optics based compute systems (M1, M2,…Mn).

22. The system as claimed in claim 1, wherein the each of the optics based compute systems (M1, M2,…Mn) is designed in a modular hexagonal shape having six sides (Light-Compute™ Processor Lego), each side having for free-space optical communication, where-in plurality of modular hexagonal legos may be implemented one or more clusters placed on a platform, or clusters may be arranged in a array or array may be arranged in a 3D array stack, wherein the arrangement allows chip-to-chip, processor-to-processor, rack-to-rack sig-nals communication.

23. The system as claimed in claim 1, wherein the optics based compute systems (M1, M2,…Mn) is LightCompute™ Processor Lego which may be provided in a System-in-Package (SIP) for HPC to be used in a network environment (100) such as data center.

24. An optical interconnect for modular distributed computing system, wherein the optical interconnect acts as a replacement for on-chip/on-board highspeed data bus.

25. The optical interconnect as claimed in claim 24, wherein the optical interconnect between the processors can be communicating in free space, through waveguides, buried in a PCB or on system-in-package, on-chip or through fiber-optic cables, and wherein the optical intercon-nect may be packaged along with the bare die of the compute engine on the same package, interposer or the PCB.

26. A modular distributed computing system comprising optics based compute systems (M1, M2,…Mn) designed in a modular hexagonal shape having six sides (LightCompute™ Pro-cessor Lego), wherein the said each modular hexagonal lego comprises:
- one or more processor (201) which is reconfigurable,
- one or more memory (203) to store instructions, and
- one or more communication interface (205),
all assembled in an assembly and configured to enable chip-to-chip, module-to-module high bandwidth free-space interconnects and free-space optical communication;
wherein the said processor (201) executes the stored instructions of memory (203) in order to enable the compute system and automate the process of construction, assembly and communication,
wherein the logos are interconnected with high speed chip-to-chip, module-to-module optical interconnects, wherein the optical interconnect acts as a replacement for on-chip/on-board highspeed data bus.

27. The modular distributed computing system as claimed in claim 26, wherein the compute systems (legos) may be distributed in multiple clusters, wherein each cluster may have one or more pre-determined slots for the compute system (M1and/or M2 and/or Mn), wherein each slot may be pre-configured to enable inter system optic based communication, wherein fur-ther the cluster of legos may be arranged in array and arrays may be arranged in a 3D stack, which may be packaged in a server blade.

28. The modular distributed computing system as claimed in claim 26, wherein the cluster comprises two clusters (A and B) or more clusters, wherein cluster (A) comprises seven slots (601a, 603a, 605a, 607a, 609a, 611a, and 613a) and each slot may be interconnected using the optics based communication channel (615a), and cluster (B) comprises seven slots (601b, 603b, 605b, 607b, 609b, 611b, and 613b) and each slot may be interconnected using the op-tics based communication channel (615b).

29. The modular distributed computing system as claimed in claim 28, wherein the inter cluster communication may be enabled based on the same optic based communication channels, which comprises a communication, wherein the compute system slot (611a) of cluster (A) may be connected to the compute system slot (603b) of the cluster (B) are connected based on the pre-determined optics based communication channel.

30. The modular distributed computing system as claimed in claim 28, wherein in the slots of each Cluster (A) and Cluster (B), modular compute systems (M1, M2,……..M7) can be as-sembled such that cluster (A) may comprise seven modular systems (legos) viz. (M1, M2, M3, M4, M5, M6, and M7) placed on seven slots (601a, 603a, 605a, 607a, 609a, 611a, and 613a) respectively; and similarly cluster (B) may comprise seven modular systems (legos) viz. (M1, M2, M3, M4, M5, M6, and M7) placed on seven slots (601b, 603b, 605b, 607b, 609b, 611b, and 613b) respectively.

31. The modular distributed computing system as claimed in claim 28, wherein in one slot more than one modular unit may be placed co-axial to the vertical axis such as the slot (601a) may hold one or more modular unit, whereas each modular unit may execute different operations, and the slot (601a) may comprise a centra processing unit (CPU), a graphic processing unit (GPU), a Field Programmable Gate Arrays (FPGA) or other related units, wherein multiple modular units in a single slot may be placed (‘3D stacking’).

32. The modular distributed computing system as claimed in claim 28, wherein the modular units may be placed in a network such that at least two modular units communicate through free space optical (FSO) coupling, such as that the slots (601a and 603a) are configured to have any one side of the slot (i.e. any edge of 601a) parallel and co-axial to any one side of the slot (i.e. any edge of 603a), and wherein the free-space coupling is enabled at the edges which may be used for communication.

33. The optics based compute system (M1, M2,…Mn) and the modular distributed computing system as claimed in claims 1 and 28, wherein the said systems are used for enabling high-performance computing systems (HPC Systems) and as a SIP in a network environment, wherein the compute system is executed by one or more processor involving the method steps (701-707).

34. The optics based compute system (M1, M2,…Mn) and the modular distributed computing system as claimed in claims 1 and 28, wherein he system is performed by a method for en-abling high-performance computing systems (HPC Systems) based on construction and as-sembly of an optics based compute system wherein the communication of signal and/or data between the compute systems (M1, M2,….Mn) and/or between the multiple clusters, each cluster comprising compute systems (M1, M2,….Mn) can be achieved by free space optical communication using opto-electrical connector (107) and/or a 3D transceiver module, wherein the transceiver module may comprise one or more optical engine.

35. A method for enabling high-performance computing systems (HPC Systems) based on construction and assembly of an optics based compute system (M1, M2,….Mn) wherein method involves one or more processor which is performed according the method steps (701-707) which comprises:
- step 701 which includes enabling construction and assembly of an optics based compute system, which comprises transmitting one or more signals from at least one of a plurality of components placed on an interposer of a hybrid 3D transceiving module;
- step 703 which includes configuring and/or controlling, by a processor, an optical channel based on the transmitted one or more signals;
- step 705 which includes enabling inter module and intra module, reception of the one or more transmitted signals; and
- step 707 which includes providing, a high data rate computing performance based on the optical channel enabled inter module and intra module reception of the one or more transmitted signals associated with a hybrid 3D transceiving module.