A SYSTEM AND METHOD FOR FAST RE-LOCKING OF PHASE LOCKED LOOP (PLL)
Field of the Invention
The present invention relates to frequency circuits and more specifically to a system and method for enhancing re-locking of a phase locked loop (PLL) system, i.e., through this methodology the PLL will be locked almost instantly.
Background of the Invention
In the field of frequency synthesis, phase lock loops (PLLs) are employed to act as wide frequency range tracking filters and as wide frequency range frequency translators. When thus used, the phase lock loop is designed to lock a synthesized signal of a first oscillator at a first frequency and at a first phase to the phase of an incoming reference signal at another frequency. Once the frequency of the synthesized signal developed in the phase lock loop (PLL) is matched to that of the incoming reference signal, steady state is said to exist However, when the PLL is powered down and then switched on, the phase lock loop experiences a transient state before the loop locks on and settles to the correct reference frequency. For many applications, where the PLL is switched on and off in the same configuration frequently, it is important to reduce the time spent in this transient state.
U.S. Patent No: 4937536 discloses a phase lock loop frequency synthesizer for providing a synthesized frequency signal employing a modified adaptive loop construction having parallel feedback paths about a loop amplifier. A normal feedback path having a narrow bandwidth characteristic includes a feedback capacitor having one end connected to electrical ground via a controlled switch and a second feedback path having a wide bandwidth characteristic with a capacitor also connected across the amplifier. Upon the variation of an incoming reference signal, the controlled switch connects the normal feedback capacitor to ground permitting the wide bandwidth feedback path to rapidly

settle the loop while charging the feedback capacitor of the normal feedback path. Upon opening the controlled switch, the narrow bandwidth feedback path completes the charging of the feedback capacitor of the normal feedback loop settling the loop to the steady state condition while enhancing the settling time.
U.S. Patent No: 4559505 discloses a frequency synthesizer is provided including a reference frequency generator coupled to one input of a phase detector. The output of the phase detector is coupled via a pah* of alternately connected filters through a voltage controlled oscillator and a divider circuit to the remaining input of the phase detector to form a phase locked loop. The first filter of the pair is designated for operation on a main channel frequency while the remaining filter is designated for operation on a priority channel frequency. The capacitive elements of each respective filter remain fully charged up for operation on their respective frequencies and thus when such filters are alternately switched between to change frequency from the main channel to the priority channel, the capacitive elements need not be charged to new levels to accommodate such frequency change. Thus, switching between a main channel and a priority channel is accomplished in a minimal amount of time with a significant reduction in frequency synthesizer energy requirements.
The prior arts as described above lack in providing a fast, reliable and efficient mechanism for the fast relocking of the PLL. In the first prior art the reduction in lock time is small enough. Whereas the second prior art uses multiple loop filters for a fast frequency acquisition, but this methodology causes an increased PLL area.
Therefore, there is a need for a novel methodology which can improve re-locking time of a PLL system by locking the PLL instantaneously.
Summary of the Invention
It is an object of the present invention to provide a methodology which can improve re-locking capabilities of a PLL system.
To achieve the aforementioned objective, the present invention provides a circuit for reducing a re-lock time of a phase locked loop (PLL) comprising:
a pattern generator helping in serializing data (pre-defined voltage levels) signals;
a capture control voltage module using the serialized data (predefined voltage levels) signals for capturing a control voltage, when said PLL is in a lock mode;
a force control voltage module operatively coupled to said capture control voltage module for instantaneously passing a voltage from a node corresponding to said control voltage, when the PLL is turned on from a powered off state;
a plurality of serial resistances operatively coupled to the capture control voltage module and the force control voltage module, the plurality of serial resistances being connected between a reference voltage and a ground voltage;
a loop filter module operatively coupled to said force control voltage module for stabilizing and storing the control voltage; and
a timer module operatively coupled to force control voltage module for turning off said force control voltage module after a pre-defined number of input cycles.
Further the present invention provides a circuit for reducing a re-lock tune of a phase locked loop (PLL) comprising:
a capture control voltage module using parallel signals for capturing a control voltage, when said PLL is in a lock mode;
a force control voltage module operatively coupled to said capture control voltage module for instantaneously passing a voltage from a node corresponding to said control voltage, when the PLL is turned on from a powered off state;
a plurality of serial resistances operatively coupled to the capture control voltage module and the force control voltage module, the plurality of serial resistances being connected between a reference voltage and a ground voltage;
a loop filter module operatively coupled to said force control voltage module for stabilizing and storing the control voltage; and
a tuner module operatively coupled to force control voltage module for turning off said force control voltage module after a pre-defined number of input cycles.
Further the present invention provides a method for reducing a relock time of a phase locked loop (PLL) comprising:
providing patterns to a capture control voltage module through a pattern generator;
capturing a control voltage using the capture control voltage module, when said PLL being in a lock state;
forcing the control voltage using a force control voltage module, when said PLL being turned on from a powered down state;
switching off the force control voltage module after receiving a time out signal from a tuner; and
resuming a phase locking by the PLL.
Further the present invention provides a method for reducing a relock tune of a phase locked loop (PLL) comprising:
capturing a control voltage using a capture control voltage module, when said PLL being in a lock state;
forcing the control voltage using a force control voltage module, when said PLL being turned on from a powered down state;
switching off the force control voltage module after receiving a tune out signal from a tuner; and
resuming a phase locking by the PLL.
Brief Description of the Drawings
The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
FIGURE 1 illustrates a circuit for reducing a re-lock time of a phase locked loop (PLL) according to the present invention.
FIGURE 2 illustrates a capture control voltage module according to the present invention.
FIGURE 3 illustrates a force control voltage module according to the present invention.
FIGURE 4 illustrates a graph describing the patterns generation from a pattern generator according to the present invention.
FIGURE 5 illustrates a flow diagram of a method for reducing a re-lock time of a phase locked loop (PLL) according to an embodiment of the present invention.
FIGURE 6 illustrates a flow diagram of a method for reducing a re-lock time of a phase locked loop (PLL) according to another embodiment of the present invention.
Detailed Description of the Invention
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the preferred embodiments. The present invention can be modified in various forms. The preferred embodiments of the present invention are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components.
This invention reduces the re-lock time of the PLL by cutting down on the time the loop filter capacitor takes to get charged/discharged to the desired control voltage. The term 'relock' is used because the aim of the invention is to reduce the lock time of a PLL which has previously gone into a normal lock.
FIGURE 1 illustrates a circuit 100 for reducing a re-lock time of a phase locked loop (PLL) according to the present invention. The circuit 100 includes a pattern generator 102, a capture control voltage module 104, a force control voltage module 106, a series of resistances 108, a loop filter module 110, and a timer 112. The pattern generator 102 generates clock pulses in a fixed pattern, which helps in serializing the pre-defined voltage levels. In another embodiment of the present invention the pattern generator 102 is in a de-active mode (excluded from the circuit) when the pre-defined voltage levels are coming in parallel patterns. The capture control voltage module 104 uses serialized data (pre-defined voltages) signals for capturing a control voltage, when the PLL is in a lock mode. The force control voltage module 106 is operatively coupled to the capture control voltage module 104 for instantaneously passing a voltage from a node corresponding to the control voltage, when the PLL is turned on from a powered off state. The series of resistances such as 1, 2, 3, to N are operatively coupled to the capture control voltage module 104 and the force control voltage module 106 to provide variable voltage nodes, and these resistances are connected between a reference voltage (VREF) and the ground voltage (GND). The loop filter module 110 is operatively coupled to the force control voltage module 106 for stabilizing and storing the control voltage, hi an embodiment of the present invention the loop filter module 110 is a low pass filter (LPF) for stabilizing the control voltage. The timer module 112 is operatively coupled to the force control voltage module 106 for turning off the force control voltage module 106 after a predefined number of input cycles. The timer module 112 passes a timeout signal to turn off the force control voltage module 106.
FIGURE 2 illustrates the capture control voltage module 104 according to the present invention. The capture control voltage module 104 includes a comparator 202, a combinational logic 204 and the sequential logic 204. The capture control voltage module 104 compares the control voltage (voltage on loop filter, voltage input of VCO) with predefined voltage levels during the lock time of the PLL. The predefined voltage levels (lines 1 to N in FIGURE 1) are generated using a series of resistances 108 placed in series between the reference voltage (VREF) and the ground voltage (GND). The
difference between two consecutive voltage levels is decided by the number of resistances used in series. The comparator 202 compares the control voltage with some voltage on lines 1 to N either serially or hi parallel, hi serial detection, switches P[l], P[2], ...P[N] (FIGURE 2) are turned on according to the output of the pattern generator 102, P [N: 1] (FIGURE 4). A sequential block 204 comprising of D flip-flops latches on to the compared data and subsequently, the combinational logic 204 indicates (SW [N: 1]) the closest of the N lines to the control voltage. The flip-flops are not powered down along with the PLL so that the stored data is not lost.
FIGURE 3 illustrates the force control voltage module 106 according to the present invention. The module 106 is activated just after the PLL is turned on from a 'power-down' state. The force control voltage module 106 contains N switches shown in block 306 and an operational amplifier 302. The operational amplifier 302 is configured as a voltage follower mode. The operational amplifier 302 is the same as is used in the comparator 202 hi the capture control voltage module 104 so that the input offset gets effectively cancelled. One of the switches from the block 306 (FIGURE 3) is turned on according to SW [N: 1], connecting the appropriate voltage level to the positive input of the operational amplifier 302. The operational amplifier 302, configured as a voltage follower, brings the voltage on the loop filter (control voltage of VCO) capacitor 304 to the voltage on its positive input Hence, the VCO reaches the desired frequency in a very small time. The timer 112 turns off the operational amplifier 302 after a pre-defined number of input cycles.
The time the system takes to achieve re-lock depends of the following factors,
1. The startup tune of the current reference, the current of which is used in the
comparator 202 and the operational amplifier 302.
2. The bandwidth of the operational amplifier 302 configured as a voltage follower.
FIGURE 4 illustrates a graph describing the patterns generation according to the present invention.
FIGURE 5 illustrates a flow diagram of a method for reducing a re-lock time of a phase locked loop (PLL) according to an embodiment of the present invention. At step 502, patterns are provided to a capture control voltage module through a pattern generator. At step 504, a control voltage is captured using the capture control voltage module, when said PLL being in a lock state. At step 506, the control voltage is forced using a force control voltage module, when said PLL being turned on from a powered down state. At step 508, the force control voltage module is switched off after receiving a tune out signal from a timer. At step 510, a phase locking is resumed by the PLL.
FIGURE 6 illustrates a flow diagram of a method for reducing a re-lock time of a phase locked loop (PLL) according to another embodiment of the present invention. At step 602, a control voltage is captured using the capture control voltage module, when said PLL being hi a lock state. At step 604, the control voltage is forced using a force control voltage module, when said PLL being turned on from a powered down state. At step 606, the force control voltage module is switched off after receiving a time out signal from a timer. At step 608, a phase locking is resumed by the PLL.
The present invention provides a circuit for reducing a re-lock time of a phase locked
(
loop (PLL) system offers various advantages. First, the present methodology has been implemented with simple digital structures for reducing the re-lock time of the phase locked loop systems. Second, the novel methodology is very cost effective as it utilizes simple comparators, resistors, operational amplifiers for its operation.
Although the disclosure of circuit and method has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We Claim:
1. A circuit for reducing a re-lock time of a phase locked loop (PLL) comprising:
a pattern generator helping in serializing data (pre-defined voltage levels) signals;
a capture control voltage module using the serialized data (predefined voltage levels) signals for capturing a control voltage, when said PLL is in a lock mode;
a force control voltage module operatively coupled to said capture control voltage module for instantaneously passing a voltage from a node corresponding to said control voltage, when the PLL is turned on from a powered off state;
a plurality of serial resistances operatively coupled to the capture control voltage module and the force control voltage module, the plurality of serial resistances being connected between a reference voltage and a ground voltage;
a loop filter module operatively coupled to said force control voltage module for stabilizing and storing the control voltage; and
a timer module operatively coupled to the force control voltage module for turning off said force control voltage module after a predefined number of input cycles.

2. The circuit as claimed in claim 1, wherein said loop filter comprises a low
pass filter.
3. The circuit as claimed in claim 1, wherein said force control voltage module
comprises an operation amplifier in a voltage follower mode.
4. A circuit for reducing a re-lock time of a phase locked loop (PLL)
comprising:
a capture control voltage module using parallel signals for capturing a control voltage, when said PLL is in a lock mode;
a force control voltage module operatively coupled to said capture control voltage module for instantaneously passing a voltage from a node corresponding to said control voltage, when the PLL is turned on from a powered off state;
a plurality of serial resistances operatively coupled to the capture control voltage module and the force control voltage module, the plurality of serial resistances being connected between a reference voltage and a ground voltage;
a loop filter module operatively coupled to said force control voltage module for stabilizing and storing the control voltage; and
a timer module operatively coupled to the force control voltage module for turning off said force control voltage module after a predefined number of input cycles.
5. The circuit as claimed in claim 4, wherein said loop filter comprises a low
pass filter.

6. The circuit as claimed in claim 4, wherein said force control voltage module
comprising an operation amplifier in a voltage follower mode.
7. A method for reducing a relock tune of a phase locked loop (PLL)
comprising:
providing patterns to a capture control voltage module through a pattern generator;
capturing a control voltage using the capture control voltage module, when said PLL being in a lock state;
forcing the control voltage using a force control voltage module, when said PLL being turned on from a powered down state;
switching off the force control voltage module after receiving a tune out signal from a timer; and
resuming a phase locking by the PLL.
8. A method for reducing a relock time of a phase locked loop (PLL)
comprising:
capturing a control voltage using a capture control voltage module, when said PLL being in a lock state;
forcing the control voltage using a force control voltage module, when said PLL being turned on from a powered down state;
switching off the force control voltage module after receiving a time out signal from a timer; and

resuming a phase locking by the PLL.
9. A circuit for reducing a re-lock time of a phase locked loop (PLL) substantially as
herein described with reference to and as illustrated in the accompanying
drawings.
10. A method for reducing a relock time of a phase locked loop (PLL) substantially as
herein described with reference to and as illustrated in the accompanying
drawings.