A SYSTEM AND METHOD FOR ON-CHIP DUTY CYCLE MEASUREMENT
Field of the Invention
The present invention relates to the field of integrated circuits, and more specifically to a system and method for on-chip duty cycle measurement.
Background of the Invention
Continuous, developments in the fields of analog and digital circuits (such as microprocessors and high speed communications) need efficient electronic components. Compatibility and the integrity of clock signals within the circuits is one of the important requirements. System clock performance that was previously acceptable is now insufficient to support the high clock speeds of today's circuits.
Duty cycle of high speed clocks is very critical in certain applications like DDR2 (Double Data Rate 2), where read/write operation is performed on both rising and falling edges of the clock. Measuring duty cycle of high speed clocks is thus very critical in these applications. Off chip duty cycle measurement of high speed clocks is not feasible due to speed limitations of 10's and additional distortion caused by intermediate buffers. Hence an on-chip measurement scheme is required to accurately measure duty cycle of highspeed clock signals.
The measurement of duty-cycle of a clock signal is an important part of most on-chip PLL BIST solutions. Duty cycle is an important PLL clock specification for DDR2 kind of applications and its measurement is a vital part of any PLL BIST solution. The conventional approaches for measuring and correcting duty cycle can be categorized broadly into analog, digital and mixed-signal. Purely analog duty cycle corrector (DCC) circuits like the one proposed by Toru Ogawa, Kenji Taniguchi in ISCAS-2002, Volume 4 titled as "A 50% Duty-Cycle Correction Circuit for PLL Output", consist of a voltage controlled oscillator (VCO), operational amplifiers (OPAMP), phase detectors and
frequency filters that makes the design extremely resource-hungry. These circuits are obviously not a good choice when die area is the most important constraint. Moreover, in a typical digital BIST environment, purely analog approaches can not be used.
The vernier delay line (VDL) has been used extensively for measurement of time and time to digital conversion. The technique for measuring Time of Flight (TOF) of particles using VDL technique is proposed by Antonio H. Chan and Gordon W. Roberts in IEEE Trans. On VLSI Systems, Vol. 12, No. 1, Jan-2004 titled as "A Jitter Characterization System Using a Component-Invariant Vernier Delay Line". It measures the time between Start and Stop signal fed to the VDL with a resolution and requires a multi-stage pipelined asynchronous read out circuit. Both these features are unattractive for a BIST implementation due to the area overhead and need for characterization of the test-circuit. Thus, the conventional VDL based time-to-digital converters require an extensive calibration scheme and use two input clocks or start-stop signals. A common shortcoming for such systems is that they can not be used for very high frequencies.
Therefore, there is a need of a system and method for on-chip duty cycle measurement using a single clock signal that neither requires any reference signal for time-period measurement nor requires a calibration phase.
Summary of the Invention
To achieve the desired objective, one embodiment of the present disclosure describes a system comprising an apparatus for measuring the duty cycle of a clock signal. The apparatus comprises a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module. The first multi-tap delay module receives the input clock signal CLK and provides a first constant incremental delay at each tap. The second multi-tap delay module simultaneously receives the input clock signal CLK and provides a second constant incremental delay at each tap which is greater than the first constant incremental delay. Each element of the multi-element detecting module has a first input
operatively coupled to a selected tap of the first multi-tap delay module, and a second input operatively coupled to a corresponding tap of the second multi-tap delay module. The ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle, then determines the duty cycle of the clock signal.
This disclosure also describes an apparatus for measuring the duty cycle of a clock signal. The apparatus comprises a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module. The first multi-tap delay module receives the input clock signal CLK and provides a first constant incremental delay at each tap. The second multi-tap delay module simultaneously receives the input clock signal CLK and provides a second constant incremental delay at each tap which is greater than the first constant incremental delay. Each element of the multi-element detecting module has a first input operatively coupled to a selected tap of the first multi-tap delay module, and a second input operatively coupled to a corresponding tap of the second multi-tap delay module. The ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle, then determines the duty cycle of the clock signal.
This disclosure further teaches a method for measuring the duty cycle of a clock signal comprising providing a first constant incremental stepped delay to the clock signal, providing a second constant incremental stepped delay to the clock signal where the first constant incremental stepped delay is less than the second constant incremental delay, sampling the level of the first delayed clock signal using the second delayed clock signal at each step, and determining the ratio of the number of steps in which the sampled clock level being high with respect to the total number of steps covering one complete clock cycle.
Brief Description of the Drawings
The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
FIGURE 1 illustrates the block diagram of an apparatus for measuring the duty cycle of a clock signal according to the present invention.
FIGURE 2 illustrates the block diagram of an apparatus for measuring the duty cycle of a clock signal according to an embodiment of the present invention.
FIGURE 3 illustrates a block diagram of a system that uses an apparatus, which measures the duty cycle of a clock signal, according to an embodiment of the present invention.
FIGURE 4 illustrates a flow diagram of a method for measuring the duty cycle of a clock signal according to an embodiment of the present invention.
Detailed Description of the Invention
The embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments and can be modified in various forms. The embodiments of the present invention described herein are only provided to explain more clearly the present invention to the ordinarily skilled in the art of the present invention. In the accompanying drawings, like reference numerals are used to indicate like components.
FIGURE 1 illustrates the block diagram of an apparatus 100 for measuring the duty cycle of a clock signal according to the present invention. Apparatus 100 includes a first
multi-tap delay module 101, a second multi-tap delay module 102, and a multi-element detecting module 103. The input terminal of the first multi-tap delay module 101 is coupled to an input node IN. The input terminal of the second multi-tap delay module 102 is also coupled to input node IN. First multi-tap delay module 101 provides the input clock signal CLK a first constant incremental delay at each tap. The second multi-tap delay module 102 provides the input clock signal CLK a second constant incremental delay at each tap. The first constant incremental delay is less than the second constant incremental delay. Each element of the multi-element detecting module 103 has two input terminals. .The first input is coupled to a selected tap of the first multi-tap delay module 101 and the second input is coupled to a corresponding tap of the second multi-tap delay module 102. The clock duty cycle is determined by calculating the ratio of the number of outputs (Ql, Q2,—Qn) of the multi-element detecting module 103 in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.
FIGURE 2 illustrates the block diagram of an apparatus 200 for measuring the duty cycle of a clock signal according to an embodiment of the present invention. First multi-tap delay module 101 includes a plurality of buffers such as 101a, 101b, 101c,—lOln. Second multi-tap delay module 102 also includes a plurality of buffers such as 102a, 102b, 102c,—102n. Multi-element detecting module 103 includes a plurality of D flip-flops 103a, 103b, 103c---103n and a plurality of buffers bl, b2,~--bn.
The individual buffer such as 101a, 101b, 101c,—lOln of the first multi-tap delay module 101 is coupled to the D input of the respective Flip-Flop of the multi-element detecting module 103. The individual buffer 101a, 101b, 101c,—lOln are identical and have a propagation delay "Ts". The individual buffer such as 102a, 102b, 102c,—102n of the second multi-tap delay module 102 is coupled to the clock input (CK) of the respective D Flip-Flop of the multi-element detecting module 103. The individual buffer 102a, 102b, 102c,—102n are also identical but have a propagation "TF" which is less than the propagation delay Ts.
The first multi-tap delay module 101 is referred to as the "Fast Buffer Chain (FBC)" while the second multi-tap delay module 102 is called the "Slow Buffer Chain (SBC)". The D Flip-Flop is abbreviated as DFF. The difference in buffer delays is referred to as delta delay TD. Thus TD = TS-TF-
When rising edge of the clock signal is passed through the first buffer of the Fast Buffer Chain (FBC), the edge is delayed by TF while the same clock edge is delayed by Ts when passed through the Slow Buffer Chain (SBC). Thus the first D Flip-Flop (DFF) samples a point at an offset of To from the rising edge of the clock. The rising edge of the clock appears at the output of the second buffer in the Fast Buffer Chain (FBC) after a delay of 2 TF while it appears after a delay of 2 Ts at the output of the second buffer. Hence the relative movement of the clock as determined by the second D Flip-Flop (DFF) is 2 Ts -2 Tp = 2 Tp. Thus the second D Flip-Flop (DFF) samples a point on the clock at an offset of 2 TD from the rising edge. It can be deduced on continuing the process that the outputs of the D Flip-Flop (DFF) actually contain equally spaced samples of the clock under test, sampled at a resolution of To- By counting the number of "l"s (High-level of the clock) say N and the number of "0"s (Low-level of the clock) say M, the duty cycle (DC) of the clock under test is DC = N/ (N+M).
FIGURE 3 illustrates a block diagram that discloses an application for an apparatus 100, which measures the duty cycle of a clock signal, according to an embodiment of the present invention used in a system 300. System 300 includes the apparatus 100. Apparatus 100 includes a first multi-tap delay module 101, a second multi-tap delay module 102, and a multi-element detecting module 103.
FIGURE 4 illustrates a flow diagram of a method for measuring the duty cycle of a clock signal according to an embodiment of the present invention. At step 401, a first constant incremental stepped delay is provided to the clock signal. At step 402, a second constant incremental stepped delay is provided to the clock signal. At step 403, the level of the first delayed clock signal is sampled using the second delayed clock signal at each step.
At step 404, the ratio of the number of steps in which the sampled clock level being high with respect to the total number of steps covering one complete clock cycle is determined
The embodiment of the present invention is related to an apparatus for measuring the duty cycle of a clock signal and can be used in various applications, such as on-chip duty cycle measurement.
The present invention offers the following advantages:
1. It does not require a reference clock for measuring the duty cycle.
2. It provides sampling resolutions as low as 10 ps as its resolution is based on the difference between two buffer delays.
3. It doesn't require calibration of the buffer delays and uses standard cells from the library. Hence the circuit can be very easily synthesized and integrated in an all digital BIST environment for on-chip characterization of PLL clock.
4. It requires a test time which is equal to the time needed for the clock to propagate through the entire buffer chain. For a 400 MHz clock sampled at 10 ps resolution, the measurement time will be equal to 250*2.5ns = 625ns.
5. The process and supply variations affect both the delay chains equally and hence the sampling resolution is not affected by them.
6. It uses the average sampling resolution, which can be easily determined by dividing the known clock period (T) by total number of samples in one clock period (N+M).
Although the disclosure of system and method has been described in connection with an embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the disclosure.

We Claim:
1. A system comprising an apparatus 100 for measuring the duty cycle of a clock
signal, said apparatus 100 comprising:
a first multi-tap delay module 101 having its input receiving said input clock signal CLK and providing a first constant incremental delay at each tap;
a second multi-tap delay module 102 having its input receiving said input clock signal CLK and providing a second constant incremental delay at each tap where said first constant incremental delay is less than said second constant incremental delay; and
a multi-element detecting module 103 in which each element has a first
input operatively coupled to a selected tap of said first multi-tap delay
module, and a second input operatively coupled to a corresponding tap of
said second multi-tap delay module,
the ratio of the number of outputs of said multi-element detecting module 103 in
which the sampled clock level is high with respect to the total number of steps
covering one complete clock cycle, determining the duty cycle of said clock
signal.
2. The system as claimed in claim 1, wherein said first multi-tap delay module comprises a plurality of buffers.
3. The system as claimed in claim 1, wherein said second multi-tap delay module comprises a plurality of buffers.
4. The system as claimed in claim 1, wherein each element of said multi-element detecting module comprises a D-Flip-Flop.
5. An apparatus 100 for measuring the duty cycle of a clock signal, said apparatus 100 comprising:
a first multi-tap delay module 101 having its input receiving said input clock signal CLK and providing a first constant incremental delay at each tap;
a second multi-tap delay module 102 having its input receiving said input clock signal CLK and providing a second constant incremental delay at each tap where said first constant incremental delay is less than said second constant incremental delay; and
a multi-element detecting module 103 in which each element has a first
input operatively coupled to a selected tap of said first multi-tap delay
module, and a second input operatively coupled to a corresponding tap of
said second multi-tap delay module,
the ratio of the number of outputs of said multi-element detecting module 103 in
which the sampled clock level is high with respect to the total number of steps
covering one complete clock cycle, determining the duty cycle of said clock
signal.
6. The apparatus as claimed in claim 5, wherein said first multi-tap delay module comprises a plurality of buffers.
7. The apparatus as claimed in claim 5, wherein said second multi-tap delay module comprises a plurality of buffers.
8. The apparatus as claimed in claim 5, wherein each element of said multi-element detecting module comprises a D-Flip-Flop and a buffer element.
9. A method for measuring the duty cycle of a clock signal comprising:
providing a first constant incremental stepped delay to said clock signal; providing a second constant incremental stepped delay to said clock signal where said first constant incremental stepped delay is less than said second constant incremental delay;
sampling the level of said first delayed clock signal using said second delayed clock signal at each step; and
determining the ratio of the number of steps in which the sampled clock level being high with respect to the total number of steps covering one complete clock cycle.
10. A system comprising an apparatus 100 for measuring the duty cycle of a clock signal substantially as herein described with reference to and as illustrated in the accompanying drawings.
11. A method for measuring the duty cycle of a clock signal substantially as herein described with reference to and as illustrated in the accompanying drawings.