FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
As amended by the Patents (Amendment) Act, 2005
&
The Patents Rules, 2003
As amended by the Patents (Amendment) Rules, 2006
COMPLETE SPECIFICATION
(See section 10 and rule 13)
TITLE OF THE INVENTION
A system and method for over-current protection in a multi-level h-bridge inverter
APPLICANTS
Crompton Greaves Limited, CG House, Dr Annie Besant Road, Worli, Mumbai 400 030, Maharashtra, India, an Indian Company
INVENTORS
Dr Simi Paul Valsan and Hafiz Imtiaz Hassan, both of Crompton Greaves Limited, Electronics Design Center, CG Global R&D, Kanjurmarg(E), Mumbai 400042, Maharashtra, India, both Indian nationals
PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the nature of this invention and the manner in which it is to be performed.

FIELD OF THE INVENTION
The present invention relates to a system and method for over-current protection in a multi-level h-bridge inverter.
BACKGROUND OF THE INVENTION
An h-bridge multi-level inverter includes a plurality of h-bridge inverters connected in series to provide a multi-level voltage output to a load connected thereto. Each h-bridge inverter includes a plurality of diodes, a DC bus capacitor Cd for generating a DC source voltage V, and four switching devices connected in an H-bridge configuration across the DC bus capacitor. Example of switching devices, includes, but is not limited to, Insulated Gate Bipolar Transistors (IGBTs). Each switching device is operated by a unique PWM switching pulse which is generated by a conventional PWM switching pulse generator.
An h-bridge inverter is said to be active, when a corresponding PWM switching pulse changes state from high to low (or low to high) rapidly. Further, when an h-bridge inverter is active, corresponding higher voltage level h-bridge inverters are turned off and corresponding lower voltage level inverters are turned on. At any time, the final voltage output at A is contributed by an active inverter and corresponding lower voltage level inverters.
Over-current is a common problem in a multi-level inverter and may cause damage both to the load and the multi-level inverter if not corrected. Conventional systems employ D flip-flops to set the state of the PWM switching pulses as low whenever there is an over-current in the multi-level inverter. The setting of state of the PWM switching pulses as low reduces the output voltage and thus the load current,
In a D-flip flop, the D input is always kept as high, the original PWM signal is provided to clock input, the over-current information is given to the clear input. Whenever an over current occurs, the output of D flip-flop is set to zero. Further, the D flip-flop output is AND-ed with original PWM switching pulse. Thus, when the D flip-flop output is zero, the final PWM switching pulse is zero, and when the D flip-

flop output is one, the final PWM switching pulse is original PWM switching pulse itself.
However, there is a major limitation associated with such type of D flip-flop systems. The clock input of the D flip is connected to corresponding PWM switching pulse. And it is well known, that the D flip-flop changes its output at either rising or falling edge of the clock input. Therefore, even when the over-current ceases, the state of the corresponding PWM switching pulse is set as low till the next rising and falling edge of the clock signal.
The PWM switching pulse of an active inverter changes its state from low to high (or high to low) rapidly, therefore, the PWM switching pulse of an active inverter is quickly set to its original value, when the over-current ceases. However, the PWM switching pulses of lower voltage level inverters are at constant high. Therefore, once set to low, the PWM switching pulses of lower voltage level inverters are set to their original value only when they start changing states rapidly.
The above system works fine, when there is an over-current but fails to provide a correct output voltage and current at load when the over-current ceases. The above-mentioned problem could be overcome by modifying switching pulse of only an active inverter whenever there is an over-current. However, the problem of over-current may persist due to contribution of lower voltage level inverters.
In view of the above-mentioned problems, there is a need for an efficient system and method of over-current protection which can address and solve the aforementioned problems.
DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION
According to the invention, system for over-current protection in a multi-level h-bridge inverter is provided. The multi-level h-bridge inverter comprises a plurality of h-bridge inverters connected in series and operated by a plurality of PWM switching pulses to generate a multi-level PWM voltage output at a load, each h-bridge inverter contributing a distinct voltage level in the multi-level PWM voltage output. The system comprises a comparator configured to compare existing load current with a threshold current; a pulse modification module configured to modify a

PWM switching pulse of a currently active h-bridge inverter whenever the load current is greater than the threshold current; a timing variable generator configured to generate at least one timing variable, each indicating whether the load current is greater than the threshold current for at least one pre-defined period; and a pulse correction module configured to receive output PWM switching pulses from the pulse modification module and at least one timing variable from the timing variable generator; and modify received PWM switching pulse of at least one lower voltage level h-bridge inverter when the load current is greater than the threshold current for at least one pre-defined period even after modifying PWM switching pulse of at least one higher voltage level h-bridge inverter.
Preferably, modifying PWM switching pulse of an h-bridge inverter comprises setting state of the PWM switching pulse as low.
Preferably, the number of h-bridge inverters connected in series is equal to n.
Preferably the timing variable generator generates at least n-1 timing variables T1, T2 ...Tn_1 initialized to zero, assigns value '1' to a first timing variable T1 when the load current is greater than the threshold current for one pre-defined period, assigns value ' 1' to a next timing variable when a previous timing variable is high and the value of the load current is greater than the threshold current for a further pre-defined period.
Preferably, the pulse modification module comprises n sets of pulse modification logic, each pulse modification logic is configured to modify a PWM switching pulse of an h-bridge inverter. The pulse modification logic comprises a first AND gate for receiving a first binary input from the comparator and a second binary input as a level indicator indicating whether corresponding h-bridge inverter is currently active, a D flip-flop for receiving the output of the first AND gate at 'clear' input and PWM switching pulse of the corresponding h-bridge inverter at 'clock' input; and a second AND gate for receiving a first input from output of the D flip-flop and a second input as the PWM switching pulse.
Preferably, the pulse correction module comprises n-1 sets of pulse correction logic, each for modifying a PWM switching pulse of a lower voltage level h-bridge inverter, an 1th set of pulse correction logic, where i=l, 2..n-l, comprises i AND gates, each for receiving a first input as a level indicator indicating whether a corresponding higher level h-bridge inverter is active and a second input as a timing variable

indicating whether the load current is greater than the threshold current for at least one pre-defined period; an OR gate for receiving inputs from output of each of the i AND gates; a NOT gate for receiving an input from output of the OR gate; and another AND gate for receiving a first input from output of the NOT gate and a second input as a PWM switching pulse of corresponding h-bridge inverter.
Preferably, a first AND gate of i AND gates is configured to receive a first input as a level indicator indicating whether an immediately higher level h-bridge inverter is active and a second input as a timing variable indicating whether the load current is greater than the threshold current for one pre-defined period, and an i'h AND gate is configured to receive a first input as a level indicator indicating whether an i level higher h-bridge inverter is active and a second input as a timing variable indicating whether the load current is greater than the threshold current for i predefined periods.
A method for over-current protection in a multi-level h-bridge inverter is provided. The multi-level h-bridge inverter comprises a plurality of h-bridge inverters connected in series and operated by a plurality of PWM switching pulses to generate a multi-level PWM voltage output at a load, each h-bridge inverter contributing distinct voltage level in the multi-level PWM output. The method comprises the steps of comparing an existing load current with a threshold current; modifying a PWM switching pulse of a currently active h-bridge inverter whenever the load current is greater than the threshold current; generating at least one timing variable, each indicating whether the load current is greater than the threshold current for at least one pre-defined period; and receiving output PWM switching pulses from the pulse modification module and at least one timing variable from the timing variable generator; modifying received PWM switching pulse of at least one lower voltage level h-bridge inverter when the load current is greater than the threshold current for at least one pre-defined period even after modifying PWM switching pulse of at least one higher voltage level h-bridge inverter; and repeating steps a to e till the multilevel inverter is turned off.
Preferably, modifying a PWM switching pulse comprises setting state of the PWM switching pulse as low.
Preferably, received PWM switching pulse of a lower voltage level h-bridge inverter is modified when an i level higher h-bridge inverter is active and the load current is greater than the threshold current for i pre-defined periods.

These and other aspects, features and advantages of the invention will be better understood with reference to the following detailed description, accompanying drawings and appended claims, in which,
Fig. 1 illustrates a multi-level inverter wherein various embodiments of the invention can be performed;
Fig. 2 illustrates an exploded view of series connected h-bridge inverters of the multi-level inverter in accordance with an embodiment of the present invention;
Fig. 3 illustrates conventional PWM switching pulses for inputting to switching devices of the series connected h-bridge inverters in accordance with an embodiment of the present invention;
Fig. 4 illustrates an over-current protection system disposed between a PWM switching pulse generator and the multi-level inverter in accordance with an embodiment of the present invention;
Fig. 5 illustrates an exploded view of the pulse modification module in accordance with an embodiment of the present invention;
Fig. 6 illustrates modified PWM switching pulse of the highest voltage level inverter in accordance with an embodiment of the present invention;
Fig. 7 illustrates an exploded view of the pulse correction module in accordance with an embodiment of the present invention;
Fig. 8 illustrates modified PWM switching pulses of the highest and middle voltage level inverters in accordance with an embodiment of the present invention; and
Fig. 9 illustrates modified PWM switching pulses of the highest, middle and lowest voltage level inverters in accordance with an embodiment of the present invention.
Referring now to figures, and more particularly to Fig. 1, wherein various embodiments can be preformed. The h-bridge multi-level inverter 100 is a three phase

inverter having three-phase inverter outputs A, B, and C. The three-phase inverter outputs A, B and C are connected to a load M. An AC output signal is obtained on each phase output A, B and C by sets 10, 20 and 30 of series connected H-bridge inverters respectively. The sets 10, 20 and 30 of h-bridge inverters are connected together at a node N which forms the neutral point for the h-bridge inverter 100.
Each set 10, 20, and 30 includes three series-connected h-bridge inverters. For example, the set 10 includes series-connected h-bridge inverters 101, 102 and 103, the set 20 includes h-bridge inverters 201, 202 and 203 and the set 30 includes h-bridge inverters 301, 302 and 303.The circuit structure of each set 10, 20 and 30 is identical and they operate identically independent of each other. Therefore, in the foregoing description and drawings, the invention is explained only with respect to set 10 of series-connected H-bridge inverters.
Fig.2 illustrates an exploded view of the series-connected h-bridge inverters 101, 102 and 103 of the set 10 and a conventional PWM switching pulse generator 200 connected thereto. Each h-bridge inverter 101, 102 and 103 includes a plurality of diodes, a DC bus capacitor Cd for generating a DC source voltage V, and four switching devices connected in an H-bridge configuration across the DC bus capacitor. For example, the h-bridge inverter 101 includes switching devices S11, S21, S31 and S41 connected in an H-bridge configuration across the capacitor 21, the h-bridge inverter 102 includes switching devices S12, S22, S32 and S42 connected in an H-bridge configuration across the capacitor 22 and the -bridge inverter 103 includes switching devices S13, S23, S33 and S43 connected in an H-bridge configuration across the capacitor 23. Example of switching devices, includes, but is not limited to, Insulated Gate Bipolar Transistors (IGBTs).
The PWM switching pulse generator 200 generates unique PWM switching pulse for each switching device of the series-connected h-bridge inverters 101, 102 and 103. As a result, the PWM switching pulse generator 200 generates total twelve PWM switching pulses a11-a43 for inputting to the switching devices S11-S43 In an exemplary embodiment, the PWM switching pulse generator generates twelve PWM switching pulses by comparing a sinusoidal switching reference waveform with six level shifted carrier waveforms.

The switching devices S11-S13 are connected across a DC voltage source of value V, therefore, based on the PWM switching pulses a11-a43, each h-bridge inverter 103, 102 and 103 generates a PWM output ranging from 0 to +/-V at nodes 24, 25 and 26 respectively. The output at A is a summation of the PWM outputs at nodes 24, 25 and 26.
Fig.3 illustrates conventional PWM switching pulses a11, a12 and a13 generated for inputting to switching devices S11, S12, and S13 respectively. It may be noted that the output at nodes 24, 25 and 26 will have waveform similar to the waveform of the PWM switching pulses a11, a12, and a13 and voltage values ranging from 0 to +/-V. Thus, at output A, a multi-level sinusoidal PWM output is obtained which ranges from -3V to +3V with seven distinct voltage levels as 0, +/-V, +/-2V, and +/-3V.
It is apparent from the FIG.3, that at any time, only one PWM switching pulse changes state from high to low (or low to high) rapidly, and rest PWM switching pulses are at constant high, or at constant low. When a PWM switching pulse changes state from high to low (or low to high) rapidly, then corresponding switching inverter is said to be active. For example, when a11 changes its states rapidly, then for that duration, inverter 101 is said to be active and corresponding lower voltage level inverters 102 and 103 are constantly turned on. For example, when a12 changes its states rapidly, then for that duration, inverter 102 is said to be active, higher voltage level inverter 101 is turned off and lower voltage level inverter 103 is turned on. Further, when a13 changes its states rapidly, then for that duration, inverter 103 is said to be active and higher voltage level inverters 101 and 102 are turned off-
Thus, when an inverter is active, corresponding higher voltage level inverters are turned off and corresponding lower voltage level inverters are turned on. At any time, the final voltage output at A is contributed by an active inverter and corresponding lower voltage level inverters. The activity of an inverter is decided by the corresponding PWM switching pulse. Thus, PWM switching pulses are crucial in synthesizing the final output at A and thus the current at the load M.

Fig. 4 illustrates an over-current protection system 400 disposed between the PWM switching pulse generator 200 and the multi-level inverter 100 for modifying the PWM switching pulses a11-a1n when there is an over-current at the load M.
The over-current protection system 400 comprises a pulse modification module 402, a pulse correction module 403, a comparator 404, and a timing variable generator 405.
The PWM switching pulse generator 200 is shown to be generating PWM
switching pulses a11, a12, a1n where n is the number of h-bridge inverters
connected of the multi-level inverter 100 connected in series. For the multi-level inverter 100 of Fig. 1, the value of n=3.
In the foregoing drawings and description, the over-current protection system
400 has been explained with respect to modification of the PWM switching pulses a11,
a12...a1n of the switching devices S11, S12...S1n. However, a person of ordinary skilled
in the art will understand that the same system 400 can be used for modifying the
other sets of PWM switching pulses a21, a22, a2n and a31, a32, a3n of the multi-
level inverter 100.
The PWM switching pulse generator 200 also generates n level indicators L1 L2...Ln for representing activity status of each of the n inverters of the multi-level inverter 100. When an ith inverter is active, the value of corresponding level indicator Li is binary high, else low. Since, only one inverter is active at a time, in the set of level indicators L1 L2..Ln , only one level indicator will be at binary high and remaining will be at binary low.
The comparator 404 is configured to compare existing load current with a threshold current and generate a binary output represented by 'OC'. The OC takes value ' 1' when the load current is greater than the threshold current and the OC takes zero value when the load current is less than or equal to the threshold current. The value of OC is continuously updated by comparing the load current and the threshold current at regular intervals.

The pulse modification module 402 is configured to modify PWM switching pulse of a currently active h-bridge inverter whenever the load current is greater than the threshold current. The modification of a PWM switching pulse includes setting state of the PWM switching pulse as low.
Any time, the pulse modification module 402 receives the comparator output OC, the PWM switching pulses an, ai2-..ainand level indicators L| jL2...Ln generated by the PWM switching pulse generator 200. Based on the inputs, the pulse modification module 402 outputs PWM switching pulses referred to as a11, a12...a1n. However, at any time, only one switching pulse a11, a12, ...a1n will be modified and therefore, out of n switching signals a'11, a'12... a'1n only one will differ from corresponding input switching pulse and rest will be similar to corresponding input switching pulses.
The timing variable generator 405 is configured to generate at least one timing variable indicating whether the load current is greater than the threshold current for at least one pre-defined period. The timing variable generator 405 generates at least n-1
timing variables, T1, T2 Tn-1, which are initialized to zero. The timing variable
generator 405 assigns value ' 1' to T1 when the load current is greater than the threshold current for one pre-defined period and assigns value '1' to a next timing variable when a previous timing variable is high and the value of the load current is greater than the threshold current for a further pre-defined period.
For example, when T1 is high, the timing variable generator 405 observes the value of OC for a next predefined period and assigns value 1 to a second timing variable T2 when OC is high for two consecutive predefined periods. When T2 is high, the timing variable generator 405 observes the value of OC for a further next predefined period and assigns value 1 to a third timing variable T3 when OC is high for three consecutive predefined periods. This process continues for all the (n-1) timing variables.
The pulse correction module 403 is configured to modify PWM switching pulse of at least one lower voltage level h-bridge inverter when the load current is greater than the threshold current for at least one pre-defined period even after modifying PWM switching pulse of at least one higher voltage level h-bridge inverter.

The modification of a PWM switching pulse includes setting state of the PWM switching pulse as low.
The pulse correction module 403 receives output PWM switching pulses a'n, a'12 ■■■ a'1n , timing variables T1 T2 ... Tn.1 and level indicators L1, L2 ... Ln and generates PWM switching pulses referred to as a" 11, a" 12...a" 1n. The switching pulse a" 11 will always be similar to switching pulse a'n as a'n is the switching pulse of the highest voltage level inverter and need not be modified by the pulse correction module 403.
Further, the switching pulse a'12 a'1n may be modified based on current
values of L1...Lnand T1,T2.. Tn. The configuration of the pulse correction module 403 and its operation will be explained in detail in Fig.7.
Fig. 5 illustrates an exploded view of the pulse modification module 402 in accordance with an embodiment of the present invention.
The pulse modification module 402 comprises total n sets of pulse modification logic 40(1), 40(2).. .40(n), each for modifying one PWM switching pulse of the n PWM switching pulses a11 , a12.... a1n of the multi-level inverter 100.
Each pulse modification logic 40 comprises a first AND gate 41, a D flip-flop
42 and a second AND gate 43.
Each first AND gate 41 is configured to receive a first binary input from the comparator 404 and a second binary input as a level indicator indicating whether corresponding h-bridge inverter is currently active. Each D flip-flop 42 is configured to receive the output of the first AND gate 41 at 'clear' input and PWM switching pulse of the corresponding h-bridge inverter at 'clock' input. Each second AND gate
43 is configured to receive a first input from output of the D flip-flop 42 and a second
input as the PWM switching pulse.
When the value of n=3, the pulse modification module 403 comprises total three pulse modification logic 40(1), 40(2) and 40(3) for modifying PWM switching pulses a11 , a12 and a13 respectively. The configuration of all pulse modification logic 40(1), 40(2) and 40(3) is identical. Therefore, in the foregoing description, only the configuration of the pulse modification logic 40(1) is explained.

The pulse modification logic 40(1) comprises a first AND gate 41(1), a D flip-flop 42(1) and second AND gate 43(1). The first AND gate 41(1) receives the current value of OC and current value of level indicator L1. The output of the AND gate 41(1) is connected to CLR of the D flip-flop 42(1). In the D flip-flop, the CLK is connected to the PWM switching pulse a11, and D is always kept as high. The output Q of the D flip flop is connected to the second AND gate 43(1), whose second input is PWM switching pulse a11 itself. The output of the AND gate 43(1) is the modified PWM switching pulse a' 11
Operationally, when the values of both 'OC and 'L|' are high, the first AND gate 41(1) generates a value '1', else '0'. The CLR of the D flip flop 42(1) is enabled by the output of the AND gate 41(1). Therefore, when the output of AND gate is 1, then only the output Q of the D flip-flop 42(1) is zero, else high. Thus when the value of 'Q' is zero, then the output of the AND gate 43(1) is also zero. Thus, when the load current exceeds the threshold current and the inverter 101 is active, the state of the PWM switching pulse a11 is set to low.
At any time, only one inverter is active, therefore, when L1 is high, L2 and L3 are low. Therefore, output of AND gates 41(2) and 41(3) will be low, 'CLR' of respective D-flip flops 42(2) and 42(n) will not be enabled and outputs 'Q' will be high. Thus, outputs a'12 and a'13 of the pulse modification logic 40(2) and 40(3) will be similar to switching signals a12and a13
The modified value a'u of the PWM switching pulse a11 and unchanged values of a12 and a13 are illustrated with reference to Fig. 6.
When 'OC is low, it means that the load current does not exceed the threshold current and thus there is no requirement of modifying the switching signals generated by the pulse signal generator 200. When OC is low. the pulse modification module 402 automatically generates switching pulses a'11 , a'12 and a'13 which are similar to a11 , a12 and a13 respectively.
Fig. 7 illustrates an exploded view of the pulse-correction module 403 in accordance with an embodiment of the present invention.
The pulse-correction module 403 comprises total (n-1) sets of pulse correction logic 90(2), 90(3)..90(n), each for modifying one PWM switching pulse of (n-1)

PWM switching pulses a'12 ■•■■ a'ln generated by the pulse modification module 402. A pulse correction logic essentially modifies a corresponding switching signal, when the load current exceeds the threshold current for at least one pre-defined period even after modifying switching signal of at least one higher voltage level inverter.
The pulse correction module 403 essentially modifies the switching signals of lower voltage level inverters only, therefore, a pulse correction logic is not required for modification of switching signal a'11 of the highest voltage level inverter.
Each ith set 90(i) of the n-1 sets, where i=l, 2. ..n-1 comprise i AND gates, one OR gate, one NOT gate, and another AND gate.
For example, set 90(2) includes one AND gate 91(2), OR gate 92(2), NOT gate 93(2) and another AND gate 94(2) and the set 90(3) includes two AND gates 91(31) and 91(32), OR gate 92(3), NOT gate 93(3) and another AND gate 94(3). The set 90(n) comprises (n-1) AND gates, one OR gate, a NOT gate and another AND gate.
When the value of n=3, the pulse correction module 403 comprises only two sets of pulse correction logic 90(2) and 90(3) for modifying PWM switching pulses a'12and a'13 of inverters 101 and 102 respectively.
In the set 90(2), the AND gate 91(2) receives a first input as a level indicator L| of a higher level inverter 101 and a second input as first timing variable T1. The OR gate 92(2) receive input from output of the AND gate 91(2). The NOT gate 93(2) receives an input from output of the OR gate 92(2). The AND gate 94(2) receives a first input from output of the NOT gate 93(2) and a second input as PWM switching pulse a'12 itself.
Operationally, the PWM switching pulse a'12 is modified when both a higher voltage level inverter 101 is active and the load current exceeds the threshold current for one pre-defined period. When both L1 and T1 are high, the output of AND gate 91(2) and OR gate 92(2) are high, and the output of NOT gate 93(2) is low. Thus, the signal a'12 is assigned a value 0.
In the set 90(3), the AND gate 91(31) receives a first input as a level indicator L2 of a one level higher h-bridge inverter 102 and a second input as first timing variable T1. The AND gate 91(32) receives a first input as a level indicator L1 of a two level higher inverter 101 and a second input as second timing variable T2, The OR gate 92(3) receive input from output of the AND gates 91(31) and 91(32). The NOT gate 93(2) receives an input from output of the OR gate 92(3). The AND gate 94(3)

receives a first input from output of the NOT gate 93(3) and a second input as PWM switching pulse a'13 itself.
Operationally, the PWM switching pulse a'13 is modified when an immediate higher voltage level inverter 102 is active and the load current exceeds the threshold current for one pre-defined period. When L2 and T1 are high, the output of AND gate 91(31) and OR gate 92(3) is high, and the output of NOT gate 93(3) is low. Thus, the signal a'12 is assigned a value 0.
The PWM switching pulse a'13 may also be modified when a two level higher inverter 101 is active and the load current exceeds the threshold current for two consecutive pre-defined periods. Thus, when L1 and T2 are high, the output of AND gate 91(32) and OR gate 92(3) is high, and the output of NOT gate 93(3) is low. Thus, the signal a'13 is assigned a value 0. The modified values of the PWM switching pulses a" 11, a" 12 and unchanged value of a"13 are illustrated with reference to Fig. 8. Further, the modified values of the PWM switching pulse a"11 , a" 12 and a" 13 are illustrated with reference to Fig. 9.
Various embodiments of the present invention solve the problem of over-current in a multi-level inverter. It solves the problem by first modifying the PWM switching pulse of an active inverter and then checking whether the problem of over-current persists even after modifying the PWM switching pulse of the active inverter. When the problem of over-current persists even after modifying the PWM switching pulse of the active inverter, then the PWM switching pulses of one or more lower voltage level inverters are modified.
Although the invention has been described with reference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the scope of the invention as defined in the appended claims.

We claim:
1. A system for over-current protection in a multi-level h-bridge inverter which comprises a plurality of h-bridge inverters connected in series and operated by a plurality of PWM switching pulses to generate a multi-level PWM voltage output at a load, each h-bridge inverter contributing a distinct voltage level in the multi-level PWM voltage output, the system comprising:
a comparator configured to compare existing load current with a threshold current;
a pulse modification module configured to modify a PWM switching pulse of a currently active h-bridge inverter whenever the load current is greater than the threshold current;
a timing variable generator configured to generate at least one timing variable, each indicating whether the load current is greater than the threshold current for at least one pre-defined period; and
a pulse correction module configured to
receive output PWM switching pulses from the pulse modification
module and at least one timing variable from the timing variable generator;
and
modify received PWM switching pulse of at least one lower voltage
level h-bridge inverter when the load current is greater than the thresholdcurrent for at least one pre-defined period even after modifying PWM switching pulse of at least one higher voltage level h-bridge inverter.
2. The system as claimed in claim 1, wherein modifying PWM switching pulse of an h-bridge inverter comprises setting state of the PWM switching pulse as low.
3. The system as claimed in claim 1, wherein the number of h-bridge inverters connected in series is equal to n.
4. The system as claimed in claim 3, wherein the timing variable generator generates at least n-1 timing variables T1, T2 .. .Tn.1 initialized to zero, assigns value ' 1' to a first timing variable T1 when the load current is greater than the threshold current for one pre-defined period, assigns value ' 1' to a next timing variable when a previous timing variable is high and the value of the load current is greater than the threshold current for a further pre-defined period.

5. The system as claimed in claim 3, wherein the pulse modification module
comprises n sets of pulse modification logic, each pulse modification logic is
configured to modify a PWM switching pulse of an h-bridge inverter, the pulse
modification logic comprises:
a first AND gate for receiving a first binary input from the comparator and a second binary input as a level indicator indicating whether corresponding h-bridge inverter is currently active;
a D flip-flop for receiving the output of the first AND gate at 'clear' input and PWM switching pulse of the corresponding h-bridge inverter at 'clock' input; and
a second AND gate for receiving a first input from output of the D flip-flop and a second input as the PWM switching pulse.
6. The system as claimed in claim 3, wherein the pulse correction module
comprises n-1 sets of pulse correction logic, each for modifying a PWM switching
pulse of a lower voltage level h-bridge inverter, an ith set of pulse correction logic,
where i=l, 2..n-l, comprises:
i AND gates, each for receiving a first input as a level indicator indicating whether a corresponding higher level h-bridge inverter is active and a second input as a timing variable indicating whether the load current is greater than the threshold current for at least one pre-defined period;
an OR gate for receiving inputs from output of each of the i AND gates;
a NOT gate for receiving an input from output of the OR gate; and
another AND gate for receiving a first input from output of the NOT gate and a second input as a PWM switching pulse of corresponding h-bridge inverter.
7. The system as claimed in claim 6, wherein a first AND gate of i AND gates is
configured to receive a first input as a level indicator indicating whether an
immediately higher level h-bridge inverter is active and a second input as a timing
variable indicating whether the load current is greater than the threshold current for
one pre-defined period, and an i' AND gate is configured to receive a first input as a
level indicator indicating whether an i level higher h-bridge inverter is active and a
second input as a timing variable indicating whether the load current is greater than
the threshold current for i pre-defined periods.

8. A method for over-current protection in a multi-level h-bridge inverter which
comprises a plurality of h-bridge inverters connected in series and operated by a
plurality of PWM switching pulses to generate a multi-level PWM voltage output at a
load, each h-bridge inverter contributing distinct voltage level in the multi-level PWM
output, the method comprising the steps of:
a. comparing an existing load current with a threshold current;
b. modifying a PWM switching pulse of a currently active h-bridge inverter
whenever the load current is greater than the threshold current;
c. generating at least one timing variable, each indicating whether the load
current is greater than the threshold current for at least one pre-defined
period;
d. receiving output PWM switching pulses from the pulse modification
module and at least one timing variable from the timing variable generator;
e. modifying received PWM switching pulse of at least one lower voltage
level h-bridge inverter when the load current is greater than the threshold
current for at least one pre-defined period even after modifying PWM
switching pulse of at least one higher voltage level h-bridge inverter; and
f. repeating steps a to e till the multi-level inverter is turned off.
9. The method as claimed in claim 8, wherein modifying a PWM switching pulse comprises setting state of the PWM switching pulse as low.
10. The method as claimed in claim 8, wherein the received PWM switching pulse of a lower voltage level h-bridge inverter is modified when an i level higher h-bridge inverter is active and the load current is greater than the threshold current for i pre-defined periods.