Description:FORM 2
THE PATENTS ACT,1970
(39OF 1970)
&
THE PATENTS RULES,2003

COMPLETESPECIFICATION
[See Section 10, Rule 13]

A SYSTEM AND METHOD FOR REALIZING ULTRA-LOW PHASE NOISE, FAST SETTLING, COMPACT PHASE COHERENT AND ENERGY EFFICIENT DIGITAL SOURCE GENERATOR

BHARAT ELECTRONICS LIMITED

WITH ADDRESS:

OUTER RING ROAD, NAGAVARA, BANGALORE 560045, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

 
Field Of Invention
The present invention relates generally to digital source generator and more particularly to a system and method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator.

Background
Frequency source is one of the core components in sensor networks. Moreover, the performance of radio frequency system is closely related to the performance of the source generator source used.

Innovation and emerging technologies have resulted in the development of wireless networks and increased the demand for RF technologies for many end-use applications. Ultra-low phase noise RF signal generators play a pivotal role in circuit designing and electrical signal testing. They produce electrical signals in the form of a wave which can be used for transmission as well stimulus for the electronic component being tested. It is necessary to have a wave with known specifications to get the desired output with minimum distortion and greater accuracy.

The paper titled “A Fast-Settling PLL Frequency Synthesizer with Direct Frequency Pre-setting” describes a system where a fast-settling PLL synthesizer is realized using dynamic loop bandwidth control. It includes synthesizer with a direct frequency pre-setting function. It has a mixed-signal voltage-controlled oscillator (VCO) whose frequency can be directly and accurately preset by a digital signal depending on the divider ratio. The frequency-presetting method greatly reduces the settling time and avoids the trade-off between settling time and phase noise or spurs. It needs temperature compensating circuitry to operate correctly over a wide range of chip temperatures.

The Paper titled “On the Energy-Efficiency of Hybrid Analog-Digital Transceivers for Single- and Multi-carrier Large Antenna Array Systems” describes a method to realize Hybrid Analog-Digital transceivers to reduce hardware complexity and the energy consumption in millimetre wave/large antenna array systems by reducing the number of their Radio Frequency (RF) chains. This architecture is applied to systems with limited number of RF chains and achieve performance close to the one of a fully digital approach under some conditions.

The US Patent No. 10,404,261B1 titled “Radar Target Detection System For Autonomous Vehicles With Ultra Low Phase Noise Frequency Synthesizer” describes a method which includes analog transceiver, low phase noise synthesizer and a processing unit. The low phase noise synthesizer is generated using dual loop PLL which derives the sampling clock and helps to reduce the clutter so small Radar Cross Sectional (RCS) targets can be detected. The processing unit is used to determine the properties of target interims of Doppler or signature.

The US Patent no. 7792510 B2 titled “MULTI-BAND FREQUENCY SYNTHESIZER” describes the field of multiband frequency synthesizer architectures, which can advantageously be applied to wireless multi-mode transceivers in a cellular telecommunication system. It includes dual-loop architecture. Dual-band synthesizer utilizes a multiplicity of phase-locked loops with narrowband voltage-controlled oscillators that operate at different centre frequencies.

The US Patent no. 7701299 titled “LOW PHASE NOISE PLL SYNTHESIZER” describes that phase noise is a manifestation of instability of the output frequency of a PLL synthesizer and is observed as random frequency fluctuations around the desired output frequency. It is a limiting factor in the sensitivity of radio frequency receivers. The level of phase noise near the desired carrier frequency depends on phase noise in the reference signal and on the PLL synthesizer circuit design. It includes dual loop, one loop is used for initial tuning, while another provides low phase noise performance by removing all frequency dividers from the loop.

However, it has been observed that the phase noise in the reference of high-speed clock generation and additive phase noise from frequency translation circuits deteriorates the performance of the circuit.

For the reasons stated above, which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art for a system and method thereof that realizes ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator that is useable, scalable and independent of complicated technological mechanism and is portable and can be deployed anywhere in very little time.

Summary

The present invention is a system and method thereof to realize ultra-low phase noise and fast settling digital source generation for frequency agile sensors. To improve and simplify the sensor network architecture, conventional source generator is getting replaced by RF data convertors which work in higher Nyquist zone. Sampling clock for high speed RF-DACs (Digital to analog convertor) is generated using ultra-low phase noise Phase locked loop (PLL). Phase coherence in digitally generated source generator is achieved using digital Numerical Controlled Oscillator (NCO) and PLL with jitter cleaner.

According to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator comprising connecting at least one programmable logic device to at least one RF digital to analog converter (RF-DAC), connecting at least one oscillator to at least one phase locked loop(PLL) to provide reference clock to phase locked loop (PLL), connecting the at least one phase locked loop(PLL) to at least one programmable logic device and at least one RF digital to analog converter (RF-DAC) to provide reference Clock, connecting the at least one RF digital to analog converter (RF-DAC) to a plurality of signal conditioning . The method includes receiving, by the at least one programmable logic device digital base band signal and processing received digital base band signal through JESD204B protocol. The method includes providing, by the at least one programmable logic device digital baseband signal through high speed communication using JESD204B protocol to the at least one RF digital to analog converter (RF-DAC). The method includes generating, by the at least one RF digital to analog converter (RF-DAC) reference derived from synchronized multi-clock signal using and phase locked loop (PLL) with clock divider and jitter cleaner, by processing the received signal through at least one numerical control oscillator (NCO). Further, the method includes processing by the plurality of signal conditioning digital logic using the multi-clock signal generated and at least one RF digital to analog converter (RF-DAC) to generate RF out Signals.

According to one of the embodiments of the present invention a system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator, comprising at least one programmable logic device, the at least one programmable logic device is configured to receive digital baseband signal and provide an output digital baseband signal through high speed communication using JESD204B protocol. The system comprises at least one oscillator configured to generate reference clock. The system comprises at least one phase locked loop, at least one phase lock loop is configured to generate sampling clock. The system comprises at least one RF digital to analog converter (RF-DAC). The at least one RF circuitry is configured to generate on board clock in X-Band frequency range using Phase Locked Loop (PLL) and generate synchronized multi-clock signals. RF out signals are generated using RF-DAC as a resultant of baseband I/Q of the digital baseband signal given through high speed communication using JESD204B protocol. Further, the system comprises a plurality of signal conditioning digital logic modules to condition the synchronized multi-clock RF out signal.

Brief Description Of Accompanying Drawings

The embodiments can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, the emphasis instead being placed upon illustrating the principals of the embodiments. Moreover, the figures, like reference numerals designate corresponding parts throughout the different views.

Reference will be made to embodiments of the invention, example of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.

The above and other objects, features, and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

Figure 1 illustrates a generic block diagram of a system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator according to an exemplary implementation of one of the embodiments of the present invention.
Figure 2 illustrates a block diagram to generate on board clock in X-Band frequency range using Phased Locked Loop (PLL)according to an exemplary implementation of one of the embodiments of the present invention.
Figure 3 illustrates the phase noise of generated signal in L-Band frequency range according to an exemplary implementation of one of the embodiments of the present invention.
Figure 4 illustrates the measurement of settling time according to an exemplary implementation of one of the embodiments of the present invention.
Figure 5 illustrates the pulse-to-pulse phase difference when source generator is used in pulse mode of operation according to various embodiments of the present invention.
Figure 6 illustrates the rise time and fall time of generated signal according to an exemplary implementation of one of the embodiments of the present invention.
Figure 7 illustrates the flatness of source generator over the band according to an exemplary implementation of one of the embodiments of the present invention.

Detailed Description Of The Invention
The present invention is a system and method thereof to realize ultra-low phase noise and fast settling digital source generation for frequency agile sensors. To improve and simplify the sensor network architecture, conventional source generator is getting replaced by RF data convertors which work in higher Nyquist zone. Sampling clock for high speed RF-DACs (Digital to analog convertor) is generated using ultra-low phase noise Phase locked loop (PLL). Phase coherence in digitally generated source generator is achieved using digital Numerical Controlled Oscillator (NCO) and PLL with jitter cleaner.

In the following description, for the purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.

The various embodiments of the present invention provide a system and method thereof for realize ultra-low phase noise and fast settling digital source generation that is universal, inexpensive, robust, and simple in operation and control.

Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.

The systems/devices and methods described herein are explained using examples with specific details for better understanding. However, the disclosed embodiments can be worked on by a person skilled in the art without the use of these specific details.

Throughout this application, with respect to all reasonable derivatives of such terms, and unless otherwise specified (and/or unless the particular context clearly dictates otherwise), each usage of:
“a” or “an” is meant to read as “at least one.”
“the” is meant to be read as “the at least one.”

References in the present invention to “one embodiment” or “an embodiment” mean that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

Embodiments of the present invention include various steps, which will be described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special purpose processor programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, firmware and/or by human operators.

If the specification states a component or feature "may' can", "could", or "might" be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.

As used in the description herein and throughout the claims that follow, the meaning of "a, an," and "the" includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.

Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this invention will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).

Hereinafter, embodiments will be described in detail. For clarity of the description, known constructions and functions will be omitted. Parts of the description may be presented in terms of operations performed by a mechanical and/or an Electrical/Electronic system, using terms such as state, link, rotor, electronic counter, and the like, consistent with the manner commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.

Active sensor performance is decided by the parameters of the main signal source. A stable and accurate source generator is required in usage of active sensors deployed in clutter environment. High-speed switching of spot frequency is a critical parameter for ECCM requirements. With the advancement in VLSI technology, and programmability benefits, direct sampling-based digital source generators with low phase noise and low settling time being used to meet this requirement.

According to one of the embodiments of a system and method of the present invention realize ultra-low phase noise, fast settling, compact phase coherent digital source generator for frequency agile sensors. The system and method thereof of the present invention provides energy efficient digital source generator which can generate wide band Radio Frequency (RF) signals from digital I/Q data. The system and method thereof of the present invention provides generation of low phase noise synchronized multi-clock signals to reduce clutter in processing of active sensors, fast hopping carrier generation for multi-band operation, and reduction in rise time and fall time in generation of pulsed wide band Radio Frequency (RF). The system and method thereof of the present invention provides single board solution for high-speed digital interface between programmable logic device and data convertor using high speed serialize/de-serializer. Multi-layer PCB with mixed material has been used to realize the digital source generator, which enables utilization of same PCB to generate high frequency analog clocks, high speed digital data and power supplies in compact form factor.

The technological advancement and usage of active sensors in clutter environment, demands for ultra-low phase noise signal sources. Programmable digital to analog transmit modules being used to convert digital baseband signal to Radio Frequency (RF) signals. There are two main sources contributing the phase noise of the active sensors which are,
a. The phase noise in the reference of high-speed clock generation
b. Additive phase noise from frequency translation circuits such as Phase-Locked Loops (PLLs) and RF-DAC.

Figure 1 illustrates a generic block diagram of a system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator according to an exemplary implementation of one of the embodiments of the present invention. The system of the present invention as depicted in the figure 1 comprising of at least one programable logic device configured to receive digital baseband signal through high speed communication using JESD204B protocol, at least one oscillator configured to generate reference clock, at least one phase locked loop configured to generate sampling clock in X-Band frequency, at least one RF digital to analog converter (RF-DAC) configured to generate RF out signal a resultant of baseband I/Q of the digital baseband signal given through high speed communication using JESD204B protocol, and a plurality of RF signal conditioning, and synchronized multi-clock RF out signal. According to the system of the present invention in the transmit path, digital baseband signal is given to RF-DAC through high speed communication using JESD204B protocol.

An RF-sampling DAC system experience considerable impact of clock noise in its performance. The sampling clock of RF-DAC plays a major role in waveform generation. DAC output generates current noise caused by the sampling clock jitters. The generated output noise degrades its spurious free dynamic range (SFDR). Zero crossing of a periodic signal in the time domain is the measure of phase noise. Consider a sine wave with phase fluctuations.

x(t)=sin⁡(2πft+φ(t))⁡ (1)

Where f is frequency, φ(t)is the random fluctuating phase in radians with affects the phase noise.

Impact of high-speed clock noise on RF-DAC performance can be shown as
〖SNR〗_SIG (dB)=〖SNR〗_CLK (dB)+20log(π/sin((πf_SIG)/f_CLK ) ) (2)

where fSIG is the signal frequency and fCLK is the sampling frequency of the RF-DAC.

Figure 2 illustrates a block diagram to generate on board clock in X-Band frequency range using Phased Locked Loop (PLL) according to an exemplary implementation of one of the embodiments of the present invention. The RF digital to analog converter (RF-DAC) as depicted in figure 2 comprising of at least one interpolation module configured to receive a digital baseband signal provided through high speed communication using JESD204B protocol and output an interpolated signal. The RF digital to analog converter (RF-DAC) comprises at least one numerical control oscillator (NCO) configured to achieve phase coherence in digitally generated source generator by mixing at a frequency mixer the output interpolated signal with output of the at least one numerical control oscillator (NCO) in digital domain. The RF digital to analog converter (RF-DAC) comprises at least one frequency mixer configured to generate phase coherent digitally generated source signal by mixing output interpolated signal with output of the at least one numerical control oscillator (NCO). Synchronized multi clock signal generation comprises of at least one phase locked loop with clock divider and jitter cleaner configured to receive a clock input from the phase locked loop (PLL) generating sampling clock and generate and provide jitter free RF Clock. The RF digital to analog converter (RF-DAC) comprises at least one DAC core configured to generate compact phase coherent, and energy efficient digital source synchronized to multi-clock by receiving a RF Clock from the multiplexer output and processing phase coherent digitally generated source signal received from frequency mixer.

According to one of the embodiments of the present invention the system and method thereof determines/calculates and update switching time for agility mode of operation. The 48-bit dual modulation mode uses an NCO, a phase shifter, and a complex modulator to modulate the signal by a programmable RF signal. The update rate of frequency tuning word (FTW) of NCOs depends on the device capability. Figure 4 illustrates the measurement of settling time using this approach according to an exemplary implementation of one of the embodiments of the present invention.

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator comprising connecting at least one programmable logic device to at least one RF digital to analog converter (RF-DAC), connecting at least one oscillator to at least one phase locked loop(PLL) to provide reference clock to phase locked loop(PLL), connecting the at least one phase locked loop(PLL) to at least one programmable logic device and at least one RF digital to analog converter (RF-DAC) to provide digital source , connecting the at least signal conditioning digital logic. The method includes receiving, by the at least one programmable logic device digital base band signal and processing received digital base band signal through JESD204B protocol. The method includes providing, by the at least one programmable logic device digital baseband signal through high speed communication using JESD204B protocol to the at least one RF digital to analog converter (RF-DAC). The method includes generating, synchronized multi-clock signal using phase locked loop (PLL) with clock divider and jitter cleaner. Further, the method includes processing by the plurality of signal conditioning of signal generated using RF-DAC
In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator includes ultra-low phase noise synchronized multi-clock signal, RF DAC, and signal conditioning.
In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator includes on-board generation of X-band clock using phase locked loop (PLL) with clock divider and jitter cleaner.

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein the step of generating, by the at least one RF digital to analog converter (RF-DAC) receiving, by at least one interpolation module digital baseband signal through JESD204B protocol and outputting interpolated signa, synchronized multi-clock. The step of generating digital source, by the at least one using RF digital to analog converter (RF-DAC) includes achieving phase coherence in digitally generated source generator by mixing at a frequency mixer the output interpolated signal with output of the at least one numerical control oscillator (NCO). The step of generating digital source, by the synchronized multi-clock signal includes generating jitter free RF Clock by at least one phase locked loop with clock divider and jitter cleaner. The step of generating digital source, by the at least one numerical control oscillator (NCO) and interpolation circuitry. Further, the step of generating digital source, by processing phase coherent digitally generated source signal received from frequency mixer.

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator includes achieving phase coherence in digitally generated source generator includes generating fast hopping carrier frequency using high speed programming clock and preloaded frequency tuning word (FTW) of numerical control oscillator (NCO).

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein generating fast hopping carrier frequency takes single clock latency to update parameters.

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator provides a single board solution for high-speed digital interface between programmable logic device and RF-DAC using high speed serializer/de-serializer.

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein providing a single board solution for high-speed digital interface between programmable logic device and RF-DAC using high speed serializer/de-serializer making it energy efficient design by greater than 15 percentage.

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein generation of frequency source generator using RF-DAC results in faster rise time and fall time in nano seconds(ns)

In an implementation according to one of the embodiments of the present invention a method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein over the wide band of operation, digital logic is implemented to achieve source power variation within 1dB.

In an implementation according to one of the embodiments of the present invention a system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator, comprising at least one programmable logic device, the at least one programmable logic device is configured to receive digital baseband signal through high speed communication using JESD204B protocol. The system comprises at least one oscillator configured to generate reference clock. The system comprises at least one phase lock loop, the at least one phase lock loop is configured to generate sampling clock board clock in X-Band frequency range. The system comprises at least one RF digital to analog converter (RF-DAC). The at least one RF digital to analog converter (RF-DAC) is configured to digital source generate from baseband I/Q. Further, the system comprises a plurality of signal conditioning to condition the synchronized digital source.

In an implementation according to one of the embodiments of the present invention the RF digital to analog converter (RF-DAC) of the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator comprises at least one interpolation module. The at least one interpolation module is configured to receive a digital baseband signal provided through high speed communication using JESD204B protocol and output an interpolated signal. The RF digital to analog converter (RF-DAC) comprises at least one numerical control oscillator (NCO). The at least one numerical control oscillator (NCO) is configured to achieve phase coherence in digitally generated source generator by mixing at a frequency mixer the output interpolated signal with output of the at least one numerical control oscillator (NCO). The RF digital to analog converter (RF-DAC) comprises at least one frequency mixer. The at least one frequency mixer is configured to generate phase coherent digitally generated source signal by mixing output interpolated signal with output of the at least one numerical control oscillator (NCO). The synchronised multi clock generation comprises at least one phase locked loop with clock divider and jitter cleaner. The at least one phase locked loop with clock divider and jitter cleaner is configured to receive a clock output from the phase locked loop (PLL) generating sampling clock and generate and provide jitter free sampling clock.
In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator is configured to generate using high speed RF-DAC.

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator is configured to on-board generation of X-band clock using phase locked loop (PLL) with clock divider and jitter cleaner.

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator is configured to achieve phase coherence in digitally generated source generator by generating fast hopping carrier frequency using high speed programming clock and preloaded frequency tuning word (FTW) of numerical control oscillator (NCO).

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein generating fast hopping carrier frequency takes single clock latency to update parameters.

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator is configured to provide a single board solution for high-speed digital interface between programmable logic device and RF-DAC using high speed serializer/de-serializer.

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein providing a single board solution for high-speed digital interface between programmable logic device and RF-DAC using high speed serializer/de-serializer make it energy efficient design by greater than 15 percentage.

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein generation of frequency source generator using RF-DAC results in faster rise time and fall time in nano seconds(ns)

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein over the wide band of operation, digital logic is implemented to achieve source power variation within 1dB over the frequency band of operation.

In an implementation according to one of the embodiments of the present invention the system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator wherein the at least one programmable logic device can be FPGA, CPLD, an ASIC logic or any other programable logic device including microprocessor or microcontroller.

Figure 5 illustrates the pulse-to-pulse phase difference when digital source generator is used in pulse mode of operation according to various embodiments of the present invention. Lesser phase difference between adjacent pulses helps in reduction of clutter in processing.

Figure 6 illustrates the rise time and fall time of generated signal according to an exemplary implementation of one of the embodiments of the present invention. Using the higher sampling clock for RF-DAC, it helps in reducing rise/fall time which enables generation of narrower pulse.

Figure 7 illustrates the flatness of source generator over the band according to an exemplary implementation of one of the embodiments of the present invention. Using the digital algorithms, flatness over the band is achieved which is limited in hybrid architecture.

The present invention as implemented through various embodiments is economically viable and can be adopted by the businesses easily as it provides the higher graded security in economical plans.

Further, while one or more operations have been described as being performed by or otherwise related to certain modules, devices or entities, the operations may be performed by or otherwise related to any module, device, or entity.
Further, the operations need not be performed in the disclosed order, although in some examples, an order may be preferred. Also, not all functions need to be performed to achieve the desired advantages of the disclosed system and method, and therefore not all functions are required.
While selected examples of the disclosed system and method have been described, alterations and permutations of these examples will be apparent to those of ordinary skill in the art. Other changes, substitutions, and alterations are also possible without departing from the disclosed system and method in its broader aspects.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present invention and its practical application, to thereby enable others skilled in the art to best utilize the present invention and various embodiments with various modifications as are suited to the particular use contemplated. It is understood that various omission and substitutions of equivalents are contemplated as circumstance may suggest or render expedient, but such are intended to cover the application or implementation without departing from the scope of the present invention.
, Claims:
1. A method for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator, the method comprising:
connecting at least one programmable logic device to at least one RF digital to analog converter (RF-DAC);
connecting at least one oscillator to at least one phase locked loop (PLL) to provide reference clock to phase locked loop (PLL);
connecting at least one phase locked loop (PLL) to at least one programmable logic device;
connecting at least one RF digital to analog converter (RF-DAC) to signal conditioning;
providing, by the at least one programmable logic device digital baseband signal through high speed communication using JESD204B protocol to the at least one RF digital to analog converter (RF-DAC);
generating, synchronized multi-clock signal by using phase locked loop (PLL) with clock divider and jitter cleaner; and
processing by the plurality of signal conditioning digital logic, multi-clock signal generating digital by the at least one RF digital to analog converter (RF-DAC) to generate RF out Signals.

2. The method as claimed in claim 1 wherein the method includes step of ultra-low phase noise digital source generation using high speed RF-DAC which takes on board sampling clock in X-band using phase locked loop (PLL) with clock divider and jitter cleaner.

3. The method as claimed in claim 1 wherein the step of generating, by the at least one RF digital to analog converter (RF-DAC) digital source generation includes:
receiving, by at least one interpolation module digital baseband signal through JESD204B protocol and outputting interpolated signal
achieving phase coherence in digitally generated source generator by mixing at a frequency mixer the output interpolated signal with output of the at least one numerical control oscillator (NCO);
generating jitter free sampling clock by at least one phase locked loop with clock divider and jitter cleaner;
generating by at least one DAC core compact phase coherent and energy efficient synchronized multi-clock RF out signal by processing phase coherent digitally generated source signal received from frequency mixer in digital domain using Numerical Controlled Oscillator (NCO) withing DAC core.

4. The method as claimed in claim 1 wherein step of achieving phase coherence in digitally generated source generator includes generating fast hopping carrier frequency using high speed programming clock and preloaded frequency tuning word (FTW) of numerical control oscillator (NCO) which takes single clock latency to update parameters.

5. The method as claimed in claim 1 wherein providing a single board solution for high-speed digital interface between programmable logic device and RF-DAC using high speed serializer/de-serializer making it energy efficient design by greater than 15 percentage.

6. The method as claimed in claim1 wherein generation of frequency source generator using RF-DAC results in faster rise time and fall time in nano seconds(ns)

7. The method as claimed in claim 1 wherein over the wide band of operation, digital logic is implemented to achieve source power variation within 1dB.

8. A system for realizing ultra-low phase noise, fast settling, compact phase coherent and energy efficient digital source generator, the system comprising:
at least one programmable logic device, the at least one programmable logic device configured to receive digital baseband signal and provide an output digital baseband signal through high speed communication using JESD204B protocol;
at least one oscillator configured to generate reference clock;
at least one phase locked loop, the at least one phase lock loop configured to generate sampling clock in X-Band frequency range;
at least one RF digital to analog converter (RF-DAC), the at least one RF digital to analog converter (RF-DAC) configured to generate digital source from baseband I/Q of the digital baseband signal given through high speed communication using JESD204B protocol; and
a plurality of signal conditioning to condition the digital source generated using RF-DAC.

9. The system as claimed in claim 8 wherein the RF digital to analog converter (RF-DAC) comprises:
at least one interpolation module, the at least one interpolation module configured to receive a digital baseband signal provided through high speed communication using JESD204B protocol and output an interpolated signal;
at least one numerical control oscillator (NCO), the at least one numerical control oscillator (NCO) configured to achieve phase coherence in digitally generated source generator by mixing at a frequency mixer the output interpolated signal with output of the at least one numerical control oscillator (NCO);
at least one frequency mixer, the at least one frequency mixer configured to generate phase coherent digitally generated source signal by mixing output interpolated signal with output of the at least one numerical control oscillator (NCO);
at least one phase locked loop with clock divider and jitter cleaner, generating sampling clock;
at least one DAC core, the at least one DAC core configured to generate compact phase coherent and energy efficient digital source.

10. The system as claimed in claim 8 wherein the system is configured to generate ultra-low phase digital source using high speed RF-DAC which takes on-board sampling clock in X_Band using phase locked loop (PLL) with clock divider and jitter cleaner.

11. The system as claimed in claim 8 wherein the system is configured to achieve phase coherence in digitally generated source generator by generating fast hopping carrier frequency using high speed programming clock and preloaded frequency tuning word (FTW) of numerical control oscillator (NCO) which takes single clock latency to update parameters.

12. The system as claimed in claim 8 wherein providing a single board solution for high-speed digital interface between programmable logic device and RF-DAC using high speed serializer/de-serializer make it energy efficient design by greater than 15 percentage.

13. The system as claimed in claim 8 wherein generation of frequency source generator using RF-DAC results in faster rise time and fall time in nano seconds(ns)

14. The system as claimed in claim 8 wherein over the wide band of operation, digital logic is implemented to achieve source power variation within 1dB.