Claims:We Claim:
1. A method for selective packet processing comprising:
receiving, by a data processor (101), a first packet from a first radio signal processor (103) and a second packet from a second radio signal processor (108), wherein the first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path, and wherein the second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path;
checking, by the data processor (101), the first CRC status and the second CRC status to identify an error in the first packet and the second packet, wherein if the first packet and the second packet comprise the error, the data processor (101) comprising:
comparing the first RSSI and the second RSSI; and
applying an error correction method to one of the first packet and the second packet based on the comparison;
and wherein if one of the first packet and the second packet is error-free, the data processor (101) comprising:
validating the buffer data associated with the error-free packet based on a data integrity check; and
sending the buffer data to an external user interface based on the validation of the buffer data.
2. The method as claimed in claim 1, wherein the first packet is generated by the first radio signal processor (103) based on reading a data frame.

3. The method as claimed in claim 1, wherein the second packet is generated by the second radio signal processor (108) based on reading the data frame.

4. The method as claimed in claim 1, wherein the data frame is received by the first radio signal processor (103) and the second radio signal processor (108) upon reception of a receive interrupt.

5. The method as claimed in claim 1, further comprising:
validating the buffer data associated with one of the first packet and the second packet upon performing the error correction method, wherein the data is validated based the data integrity check; and
sending the buffer data to an external user interface based on the validation of the buffer data.

6. A system for selective packet processing comprising:
a first radio signal processor (103);
a second radio signal processor (108); and
a data processor (101), wherein the data processor (101) is coupled to the first radio signal processor (103) and the second radio signal processor (108), and wherein the data processor (101) comprising:
a receiving module (304) to receive a first packet from the first radio signal processor (103) and a second packet from a second radio signal processor (108), wherein the first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path, and wherein the second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path;
a checking module (306) to check the first CRC status and the second CRC status to identify an error in the first packet and the second packet, wherein if the first packet and the second packet comprise the error, the data processor (101) comprising:
a comparing module (308) compare the first RSSI and the second RSSI; and
an applying module (310) to apply an error correction method on one of the first packet and the second packet based on the comparison;
and wherein if one of the first packet and the second packet is error-free, the data processor (101) comprising:
a validation module (312) to validate the buffer data associated with the error-free packet based on a data integrity check; and
a sending module (314) to send the buffer data to an external user interface based on the validation of the buffer data.
7. The system as claimed in claim 6, wherein the first packet is generated by the first radio signal processor (103) based on reading a data frame.

8. The system as claimed in claim 6, wherein the second packet is generated by the second radio signal processor (108) based on reading the data frame.

9. The system as claimed in claim 6, further comprising:
the validation module (312) to validate the buffer data associated with one of the first packet and the second packet upon performing the error correction method, wherein the data is validated based the data integrity check; and
the sending module (314) to send the buffer data to an

external user interface based on the validation of the buffer data.

Dated this 11th January, 2021

FOR BHARAT ELECTRONICS LIMITED
(By their Agent)

D. MANOJ KUMAR (IN/PA-2110)
KRISHNA & SAURASTRI ASSOCIATES LLP
, Description: FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
[SEE SECTION 10, RULE 13]

A SYSTEM AND METHOD FOR SELECTIVE PACKET PROCESSING

BHARAT ELECTRONICS LIMITED
WITH ADDRESS:
OUTER RING ROAD, NAGAVARA, BANGALORE 560045, KARNATAKA, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
TECHNICAL FIELD
[0001] The present invention relates generally to systems and methods for selective packet processing.
BACKGROUND
[0002] Various diversity-based schemes are used to improve performance of a wireless receiver. The implementation of two receive paths with discrete based components are widely used. The discrete based approach uses RF conditioning devices for Filters, LNA, down conversion for RF to IF/Low IF using mixer devices followed by mixed signal devices to convert the IF or Low IF RF modulated signals to baseband symbols. Further, complex base band signal processors are used to decode the data. Hence, more space is required for discrete components and more power is required for signal processor devices. The diversity by combining of two or more RF/IF receivers requires highly intensive signal processing methods which increases the power consumption and system complexity.
[0003] US20040053526A1 discloses a receiver diversity based on receive signal energy. The system disclosed in US20050181752A1 uses more discrete based components by using combination of RF conditioning device, mixed signal devices and complex signal processors which is complex solution.
[0004] Therefore, there is a need of a system and method which solves the above defined problems and can provide an efficient system and method for selective packet processing.
SUMMARY
[0005] This summary is provided to introduce concepts related to systems and methods for selective packet processing. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0006] In an embodiment of the present invention, a method for selective packet processing is provided. The method includes receiving, by a data processor, a first packet from a first radio signal processor and a second packet from a second radio signal processor. The first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path. The second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path. The data processor checks the first CRC status and the second CRC status to identify an error in the first packet and the second packet. If the first packet and the second packet comprise the error, the data processor includes comparing the first RSSI and the second RSSI and applying an error correction method to one of the first packet and the second packet based on the comparison. If one of the first packet and the second packet is error-free, the data processor includes validating the buffer data associated with the error-free packet based on a data integrity check and sending the buffer data to an external user interface based on the validation of the buffer data.
[0007] In another embodiment of the present invention, a system for selective packet processing is provided. The system includes a first radio signal processor, a second radio signal processor and a data processor. The data processor is coupled to the first radio signal processor and the second radio signal processor. The data processor comprises a receiving module to receive a first packet from the first radio signal processor and a second packet from a second radio signal processor. The first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path. The second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path. The data processor includes a checking module to check the first CRC status and the second CRC status to identify an error in the first packet and the second packet. If the first packet and the second packet comprise the error, a comparing module compares the first RSSI and the second RSSI, and an applying module applies an error correction method on one of the first packet and the second packet based on the comparison. If one of the first packet and the second packet is error-free, a validation module validates the buffer data associated with the error-free packet based on a data integrity check, and a sending module sends the buffer data to an external user interface based on the validation of the buffer data.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0008] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0009] Figure 1 illustrates a block diagram depicting a system for selective packet processing, according to an embodiment of the present invention.
[0010] Figure 2 illustrates a block diagram depicting an internal processing of radio signal processors, according to an embodiment of the present invention.
[0011] Figure 3 illustrates a system for selective packet processing, according to an embodiment of the present invention.
[0012] Figure 4 illustrates a flow diagram depicting a sequence of events upon reception of a receive interrupt, according to an embodiment of the present invention.
[0013] Figure 5 illustrates a flowchart depicting a method for selective packet processing, according to an embodiment of the present invention.
[0014] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
[0015] The various embodiments of the present invention provide a system and method for selective packet processing.
[0016] In the following description, for purpose of explanation, specific details are set forth to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into several systems.
[0017] The systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.
[0018] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[0019] References in the present invention to “an embodiment” or “another embodiment” mean that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment. The phrase “embodiment of the present invention” used in the present invention may refer to various embodiments of the present invention.
[0020] The present invention provides a system and method for selective packet processing.
[0021] In an embodiment of the present invention, a method for selective packet processing is provided. The method includes receiving, by a data processor, a first packet from a first radio signal processor and a second packet from a second radio signal processor. The first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path. The second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path. The data processor checks the first CRC status and the second CRC status to identify an error in the first packet and the second packet. If the first packet and the second packet comprise the error, the data processor includes comparing the first RSSI and the second RSSI and applying an error correction method to one of the first packet and the second packet based on the comparison. If one of the first packet and the second packet is error-free, the data processor includes validating the buffer data associated with the error-free packet based on a data integrity check and sending the buffer data to an external user interface based on the validation of the buffer data.
[0022] In an exemplary embodiment of the present invention, the first packet is generated by the first radio signal processor based on reading a data frame.
[0023] In another exemplary embodiment of the present invention, the second packet is generated by the second radio signal processor based on reading the data frame.
[0024] In yet another exemplary embodiment of the present invention, the data frame is received by the first radio signal processor and the second radio signal processor upon reception of a receive interrupt.
[0025] In yet another exemplary embodiment of the present invention, the data processor comprising validating the buffer data associated with one of the first packet and the second packet upon performing the error correction method, wherein the data is validated based the data integrity check; and sending the buffer data to an external user interface based on the validation of the buffer data.
[0026] In another embodiment of the present invention, a system for selective packet processing is provided. The system includes a first radio signal processor, a second radio signal processor and a data processor. The data processor is coupled to the first radio signal processor and the second radio signal processor. The data processor comprises a receiving module to receive a first packet from the first radio signal processor and a second packet from a second radio signal processor. The first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path. The second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path. The data processor includes a checking module to check the first CRC status and the second CRC status to identify an error in the first packet and the second packet. If the first packet and the second packet comprise the error, a comparing module compares the first RSSI and the second RSSI, and an applying module applies an error correction method on one of the first packet and the second packet based on the comparison. If one of the first packet and the second packet is error-free, a validation module validates the buffer data associated with the error-free packet based on a data integrity check, and a sending module sends the buffer data to an external user interface based on the validation of the buffer data.
[0027] In an exemplary embodiment of the present invention, the first packet is generated by the first radio signal processor based on reading a data frame.
[0028] In another exemplary embodiment of the present invention, the second packet is generated by the second radio signal processor based on reading the data frame.
[0029] In yet another exemplary embodiment of the present invention, the system comprising the validation module to validate the buffer data associated with one of the first packet and the second packet upon performing the error correction method, wherein the data is validated based the data integrity check; and the sending module to send the buffer data to an external user interface based on the validation of the buffer data.
[0030] Referring to Figure 1, a block diagram depicting a system (100) for selective packet processing is shown according to an embodiment of the present invention. In an embodiment, figure 1 depicts a first RF signal conditioner (105) and a second RF signal conditioner (110).
[0031] The first RF signal conditioner (105) and the second RF signal conditioner (110) comprise one or more elements from RF signal gain and attenuation blocks, RF signal impedance matching circuit for receives RF signals frequency band. In an example, the second RF signal conditioner (110) comprise an additional transmit/receive RF switching device along with a RF amplifier and post filters, optional frequency conversion block etc.,
[0032] The first RF signal conditioner (105) is interfaced with a first antenna (106). The second RF signal conditioner (110) is interfaced with a second antenna (111). In one aspect, any one from the first antenna (106) and the second antenna (111) can be configured to transmit and both antennas to receive the radio frequency waveform signals.
[0033] The first RF signal conditioner (105) is controlled by a data processor (101) via control interface signal (113), and the second RF signal conditioner (111) is controlled by the data processor (101) via control interface signal (115). The control interface signals (113) and (115) may be, but is not limited to, hardwired GPIO signals and serial port signals.
[0034] In an aspect, one or more applications running in the data processor (101) configure and control the first RF signal conditioner (105) and the second RF signal conditioner (111) for gain adjustment, a transmit mode or a receive mode via the control interface signals (113) and (115).
[0035] In one embodiment, the data processor (101) is a microcontroller-based device with an internal memory or an external memory, peripheral interfaces, and an interrupt-based processing capability. The data processor (101) acts as a host processor with user interfaces to interface an external system or users using an interface (112) such as a serial port, an Ethernet interface, and the like.
[0036] Further, the first RF signal conditioner (105) is interfaced with a first radio signal processor (103) via a RF path (104). The second RF signal conditioner (111) is interfaced with a second radio signal processor (108) via a RF path (109). The first radio signal processor (103) and the second radio signal processor (108) are radio waveform processing devices capable of transmitting and receiving the radio waveforms of specific RF frequency.
[0037] In the transmit mode of operation, the second radio signal processor (108) transmits the conditioned waveform via the second antenna (111). In the receive mode of operation, the first radio signal processor (103) and the second radio signal processor (108) receives the conditioned radio waveform signals via the first antenna (106) and the second antenna (111) respectively. In the receive mode, the first radio signal processor (103) and the second radio signal processor (108) receives radio signal waveforms via the respective RF path (104) and RF path (109) from the first RF signal conditioner (105) and the second RF signal conditioner (110) respectively.
[0038] In one aspect, in an event of a burst transmission one radio processor will act as a transmitter while the other radio processor is kept is idle mode in order to avoid the data decoding using self-reception radio signal. The total control of transmit and receive events are controlled by the data processor (101).
[0039] In one example, the system is initialized by the data processor (101) for configuration of transmit or receive waveform properties and transmit or receive data buffers. In an embodiment, only one data packet is received from any one of the channels, then the corresponding packet will be processed and validated by the data processor (101).
[0040] Based on programmed frame parameters and radio waveform settings, both the first radio signal processor (103) and the second radio signal processor (108) decode and process the received waveforms. The first radio signal processor (103) communicates with the data processor (101) using an interface (102), and the second radio signal processor (108) communicates with the data processor (101) using an interface (107). The first radio signal processor (103) and the second radio signal processor (108) handshake with the data processor (101) using the interface such GPIO’s for transmit or receive event indications. The interfaces (102) and (107) may be a serial interface for exchanging data packet or control packets. The data packets may be in a format as shown in Table 1.
Table 1: Data Packet Format
Start of packet Payload Type
(Control/Data) Payload Length Payload CRC

[0041] In one embodiment, the data packet comprises, but is not limited to, a start of packet, a payload type, a payload length, a payload and a Cyclic Redundancy Check (CRC) status.
[0042] Referring to Figure 2, a block diagram depicting an internal processing of radio signal processors is shown, according to an embodiment of the present invention.
[0043] In one embodiment, the first radio processor (103) and the second radio signal processor (108) are mixed signal devices with inbuilt embedded controller for executing instructions. The first radio signal processor (103) and the second radio signal processor (108) are programmable with transmit and receive waveform parameters and frame transmit and receive formats which converts a data packet into RF waveform and vice-versa.
[0044] The first radio signal processor (103) and the second radio signal processor (108) receive the RF conditioned waveform signals via the hardwired RF paths (208) and (209) respectively from the RF signal conditioners (105) and (110).
[0045] The applications in (204) uses its internal memory mapped registers (207) to configure radio waveform parameters such as modulation, symbol rate, radiation frequency and the like. These programmable waveform parameters are received from the data processor via interfaces (210,211) during system initialization or later based on requirements. These interfaces are for instance serial port or other suitable interfaces. The application executes frame receive/ transmit, receive data packet formation, receive or transmit interrupt service processing and data buffer management etc.
[0046] In one embodiment, the first radio signal processor (103) and the second radio signal processor (108) exchange commands or data with the data processor (101). The first radio signal processor (103) and the second radio signal processor (108) will receive and process the commands for configuration of transmit/receive waveform properties by writing the memory mapped resisters.
[0047] Referring to figure 3, a system for selective packet processing is shown, according to an embodiment of the present invention.
[0048] The system includes a data processor (101), a first radio signal processor (103), and a second radio signal processor (108). The data processor (101) is coupled to the first radio signal processor (103) and the second radio signal processor (108). The data processor (101) is coupled to a memory (316).
[0049] The memory (316) is configured to store pre-determined parameters and rules related to selective packet processing. In an embodiment, the memory (316) can include any computer-readable medium known in the art including, for example, volatile memory, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), and/or non-volatile memory, such as read only memory (ROM), erasable programmable ROM, flash memories etc. The memory (316) also includes a cache memory to work with the system more effectively. In one aspect, for low complexity preferably internal memory or external for other complex applications with data base processing of received messages.
[0050] The system further includes a database (318). The database (318) is configured to store packets. In an embodiment, the database (318) can be implemented as, but is not limited to, an enterprise database, a remote database, a local database, and the like. In one embodiment, the database (318) may themselves be located either within the vicinity of each other or may be located at different geographic locations. In another embodiment, the database (318) can be implemented as a single database.
[0051] The data processor (101) includes a receiving module (304), a checking module (306), a comparing module (308), an applying module (310), a validation module (312), and a sending module (314).
[0052] The data processor (101) executes, controls, and monitors the functioning of the blocks (304-314). In an embodiment, the data processor (101) performs a method for selective packet processing.
[0053] In one embodiment, the receiving module (304) is configured to receive a first packet and a second packet. The first packet is received from a first radio signal processor (103) via a first receive path, and the second packet is received from a second radio signal processor (108) via a second receive path. The first packet and the second packet may be in a format as shown in the Table 1.
[0054] In an aspect, the first radio signal processor (103) and the second radio signal processor (108) receive RF waveforms via respective antennas (106) and (111), decode the data based on preconfigured receive data frame parameters. The decoded data is stored upon reception of a receive interrupt event. The data frame may be, but is not limited to, in a format as shown in Table 2. Further, the received data is packetized by including other status information and sent to the data processor for validation and processing.
Table 2: Format of Data Frame
Preamble Sync Word Header/Length Data Payload CRC

[0055] Referring to the Table 2, the preamble field is used for received signal gain or timing adjustment. Sync word is used for packet synchronization. The payload will be stored in the buffer for further processing by the embedded controller. The data payload as defined in the length field will be stored in a buffer for further processing.
[0056] The first radio signal processor (103) and the second radio signal processor (111) read the data frame. Based on reading, the first radio signal processor (103) generates the first packet, and the second radio signal processor (108) generates the second packet. The first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with the first receive path. The second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with the second receive path. The first packet and the second packet may be in a format as shown in the Table 1.
[0057] In one exemplary embodiment, a time out based packet reception processing may be used. The receiving module (304) may receive only one packet from the first radio signal processor (103) or the second radio signal processor (108) because of adverse conditions effects in one channel.
[0058] Upon receiving the first packet and the second packet, the checking module (306) is configured to check the first CRC status and the second CRC status to identify an error in the first packet and the second packet. In other words, the checking of the CRC status helps to identify if there is any error in the received packets.
[0059] In an exemplary embodiment, one of the first packet and the second packet may comprise the error. In another exemplary embodiment, both the first packet and the second packet may comprise the error. In yet another exemplary embodiment, none of the first packet and the second packet comprise the error.
[0060] In one embodiment, if the first packet and the second packet comprise the error, the comparing module (308) compares the first RSSI and the second RSSI. In other words, a signal strength of the packets may be compared. Based on the comparison, a packet having better signal strength is further processed.
[0061] Upon comparison, the applying module (310) applies an error correction method to one of the first packet and the second packet. The error correction method is one of, but not limited to, a Forward Error Correction (FEC) burst decoding or a Reed-Solomon (RS) decoding and the like.
[0062] In one exemplary embodiment, if the first RSSI is better than the second RSSI, then the error correction method is applied on the first packet. In another embodiment, if the second RSSI is better than the first RSSI, then the error correction method is applied on the second packet.
[0063] Upon applying the error correction method, the validation module (312) validates the buffer data associated with the packet on which the error correction method is applied. The buffer data is validated based on a data integrity check. The data integrity check is configured to determine whether valid data is received or not. In one aspect, the CRC status of the packet may be used for the data integrity check.
[0064] In another embodiment, if one of the first packet and the second packet comprises the error, then the packet without error may be referred as an error-free packet. If the first packet comprises the error, the second packet may be referred as the error-free packet. If the second packet comprises the error, the first packet may be referred as the error-free packet.
[0065] Further, the validation module (312) validates the buffer data associated with the error-free packet. The buffer data is validated based on a data integrity check. The data integrity check helps to determine whether valid data is received or not. In one aspect, the CRC status of the packet may be used for the data integrity check.
[0066] Based on the validation, the sending module (314) is configured to send the buffer data to an external user interface. The external user interface may be, but is not limited to, an Ethernet, a serial port and the like.
[0067] In an embodiment, the system is configured to identify best path among the first receive path and the second receive path based on checking the RSSI. Further, the packet associated with the best path is processed and sent to the external user interface.
[0068] Referring now to Figure 4, a flow diagram depicting a sequence of events upon reception of a receive interrupt is shown, according to an embodiment of the present invention.
[0069] In an embodiment, a data processor (101) performs a selective diversity processing (403) of the both channel packets by packet analysis to select an error-free packet.
[0070] At step (401), a first radio signal processor (103) is configured to generate a first packet based on reading a data frame. At step (402), a second radio signal processor (108) is configured to generate a second packet based on reading the data frame.
[0071] At step (403), the data processor (101) is configured to analyse and process the first packet and the second packet to determine the best received path and its data will be used for further decoding and data extraction.
[0072] At step (404), the data processor (101) receives the first packet from the first radio signal processor (103) via the first receive path. At step (405), the data processor (101) receives the second packet from the second radio signal processor (108) via the second receive path.
[0073] At step (406), the first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path. At step (407), the second packet comprises buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path.
[0074] At step (408), the first CRC status and the second CRC status are checked to identify an error in the first packet and the second packet.
[0075] If both the first packet and the second packet comprise the error, then at step (409), the first RSSI and the second RSSI are compared.
[0076] If one of the first packet and the second packet is error-free, then at step (411), the error-free packet is validated. In an embodiment, the buffer data associated with the error-free packet is validated using a data integrity check. Once the buffer data is validated, at step (413), the validated buffer data is sent to an external user interface.
[0077] At step (410), an error correction method is applied to one of the first packet and the second packet based on the comparison of the RSSI. In one embodiment, the error correction method is applied on the packet having better RSSI. The error correction method may be, but is not limited to, a FEC decoding method.
[0078] Upon applying the error correction method, at step (411), the buffer data associated with the packet is validated using a data integrity check. Further to validation, at step (413), the validated buffer data is sent to an external user interface.
[0079] If the validation of the buffer data fails at step (411), then at step (412), the buffer data is ignored.
[0080] Referring to Figure 5, a flow chart (500) depicting a method for selective packet processing is shown, according to an embodiment of the present invention.
[0081] At a step (502), receiving a first packet from a first radio signal processor (103) and a second packet from a second radio signal processor (108). The first packet comprises buffer data, a first Cyclic Redundancy Check (CRC) status and a first Received Signal Strength Indicator (RSSI) associated with a first receive path. The second packet comprises the buffer data, a second Cyclic Redundancy Check (CRC) status and a second Received Signal Strength Indicator (RSSI) associated with a second receive path. In an embodiment, the data processor (101) is configured to receive the first packet from the first radio signal processor (103) and the second packet from the second radio signal processor (108).
[0082] In one embodiment, because of the RF channel impairments or other reason, the data processor (101) may receive only one packet from one of the channels. Hence, a timeout module implemented which ensures the receiving of data packets in a stipulated time after receiving one data packet., other wise to proceed with validation of available data packet. The timeout period is set based on over air burst length, a propagation delay, multipath scenario etc., to account maximum delay between two RF signal paths.
[0083] In one aspect, the first packet is generated by the first radio signal processor (103) based on reding a data frame. The second packet is generated by the second radio signal processor (108) based on reding the data frame. The data frame is received by the first radio signal processor (103) and the second radio signal processor (108) upon reception of a receive interrupt.
[0084] At a step (504), checking the first CRC status and the second CRC status to identify an error in the first packet and the second packet. In an embodiment, the data processor (101) is configured to check the first CRC status and the second CRC status to identify the error.
[0085] At step (506), if the first packet and the second packet comprise the error, comparing the first RSSI and the second RSSI. In an embodiment, if the first packet and the second packet comprise the error, the data processor (101) is configured to compare the first RSSI and the second RSSI.
[0086] At step (508), applying an error correction method to one of the first packet and the second packet based on the comparison of the RSSI. In an embodiment, the data processor (101) is configured to apply the error correction method to one of the first packet and the second packet based on the comparison. The error correction method may be, but is not limited to, a Forward Error Correction (FEC) decoding and a Reed-Solomon (RS) decoding.
[0087] Upon applying the error correction method, the data processor (101) is configured to validate the buffer data associated with one of the first packet or the second packet based on a data integrity check. Based on the validation, the data processor (101) is configured to send the validated buffer data to an external user interface.
[0088] At block (510), if one of the first packet and the second packet is error-free, validating the buffer data associated with the error-free data packet based on the data integrity check. In an embodiment, if one of the first packet and the second packet is error-free, the data processor is configured to validate the buffer data associated with the error-free data packet based on the data integrity check.
[0089] At block (512), sending the buffer data to an external user interface based on the validation of the buffer data. In an embodiment, the data processor (101) is configured to send the buffer data to an external user interface based on the validation of the buffer data.
[0090] However, any number of steps of the above flowcharts may be implemented as a loop. Further, the steps of the above flowcharts may be implemented in any order.
[0091] It is also possible to implement the method for selective packet processing of the present invention by executing the above flowchart while skipping one or more steps or while implementing one or more steps multiple times.
[0092] Therefore, the system and the method for selective packet processing is not limited by the order of the steps in the flowchart.
[0093] In an advantageous embodiment, the system uses compact low power components for low packet error rate data receiver. The system is designed by utilizing low power radio signal processors and a low power data processor as main processing engine. The system is configured to perform selective diversity processing using packet analysis and processing utilizing the data processor and radio signal processors. The system is configured to determine best RF path, and a packet received via the best path is further processed.
[0094] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention.
[0095] Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions.
[0096] Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.