DESC:TECHNICAL FIELD

[001] The present subject matter described herein, in general, relates to analog-to-digital converters (ADC), employing a voltage reference and more particularly relates to a voltage reference monitoring system in ADC systems for monitoring any change in reference voltage.

BACKGROUND

[002] In microprocessor based protection relays, analog to digital convertor (ADC) is used for measurement of different parameters and ADC’s will have external reference voltage. The analog sensor signal is typically a voltage signal (i.e., sensor input VIN). The ADC converts the sensor input voltage (Vin) into an electric digital signal by comparing the sensor input (Vin) with a voltage reference (Vref). The voltage reference Vref may be externally provided to the ADC or may be internally generated by the ADC. Even the ADC module is used in a microcontroller, there is dedicated Vref input pins available in all microcontrollers. This Vref voltage is directly linked to ADC accuracy. As such, the voltage reference Vref has to be precise in order for the ADC to accurately convert a given sensor input voltage Vin into a digital signal. Any change in Vref will affect the ADC measurement and in resultant it will affect the product accuracy and performance.
ADC Conversion formula is as follows:
ADC Value = (VIN * 2n)/Vref
Wherein,
VIN is an input voltage to ADC;
N is a number of ADC bits;
Vref is a ADC reference voltage
To derive Vref, different techniques are used. These techniques can be listed as follows:
1] Using resistor divider network.
2] Using dedicated Reference IC.

[003] ADCs drift with aging. These drifts are directly proportional to the variation of the voltage reference Vref used by the ADC in the conversion process. Drifts due to aging are a relatively larger problem than absolute accuracy. Both the above techniques to derive Vref reference output have errors in form of offset and temperature drift. The internal error can be calibrated, but compensating for drift is difficult. Offset can be tackled using calibration and different software techniques. But in these software techniques or in calibration any damage or misbehavior of the Vref signal is not handled. If Vref signal is out off band then there is no technique used to indicate the error. The protection relay unit will trip or goes in to inhibit due to the fault. The protection relay will shows trip due to overload of electrical parameters but the actual cause of fault will not be logged.

[004] The prior art document, US8736469 B2 discloses a method and system for minimizing variation of converter voltage reference wherein a voltage reference generator generates a voltage reference from a supply voltage, wherein the voltage reference is fed to an analog to digital convertor which generates an output signal based on an input signal and the voltage reference from the voltage reference generator.

[005] The prior art document, WO2008042361 A1discloses an integrated energy metering system comprising an energy meter that includes a voltage ADC for sensing voltage, a current ADC for sensing current, a microcontroller; a first memory device for storing program data for the energy meter; and a plurality of circuit blocks; a voltage monitor for monitoring the primary power supply; a power supply switch circuit for selectively applying one of the primary and auxiliary power supplies to the energy meter.

[006] The prior art document, US20050240783 A1 discloses a method for monitoring a voltage level of a power supply for a disk drive thereby preventing a write operation of the disk drive and continuing one or more other operations of the disk drive when the operating voltage is at or lower than a write-preventing threshold voltage.

[007] The prior art document, US 20110150060 A1 discloses a method for Voltage Margin Monitoring for an ADC-Based Serializer/ Deserializer in Mission Mode for calculating voltage margin for the at least one of the bit values using the digital value from the ADC corresponding to the bit value and subtracting the determined ISI for the bit value.

[008] The prior art document, US7026824 B2 discloses a voltage reference generator with negative feedback for generating an output voltage at an output node.

[009] The prior art document, US20130162259 A1 discloses a system and method for developing highly accurate measurements by calibrating monitoring units with the known accurate measurements of reference voltages of an adjacent monitoring unit and further comparing the two measurements of the reference voltage and a correction factor is calculated to be used to correct subsequent measurements from the adjacent monitoring packs.

[0010] Thus, in view of the existing techniques to monitor a reference voltage in ADC systems, there exists a need to provide a more accurate system to monitor the reference voltage change and subsequently give indication of the event when the reference voltage is beyond a preset threshold limit.

SUMMARY OF THE INVENTION

[0011] The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the present invention. It is not intended to identify the key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concept of the invention in a simplified form as a prelude to a more detailed description of the invention presented later.

[0012] An object of the present invention is to provide an improved system for tracking variation of a voltage reference input to an analog-to-digital converter (ADC) for converting analog to digital signals.

[0013] Another object of the present invention is to provide an improved system for providing an indication of variation of the voltage reference so to protect a device in which ADC converter is employed.

[0014] Accordingly, the present invention provides a reference voltage monitoring system for monitoring variation in reference voltages (Vref) in an analog to digital convertors (ADCs) and indicating an event wherein Vref is greater than a preset threshold limit so as to protect a device against faults due variations in Vref.

[0015] In one implementation, the present invention provides a ADC system wherein said ADC system is configured to receiving a reference voltage (Vref) signal and an input voltage, comparing, said reference voltage (Vref) signal received, to a preset threshold limit and triggering , a Vref error flag in the event when said reference voltage (Vref) signal is greater that the preset limit

[0016] In one implementation, the present invention provides a method. The method includes receiving, at an ADC, a voltage reference (Vref) signal, sampling of said Vref signal, comparing the Vref channel offset with preset tolerance band, actuating a Vref error flag when the Vref offset channel out off the set tolerance band, indication using an alarm or trip to protect an electrical product against a fault due to variation in Vref.

[0017] A system as provided in the present invention enables to monitor the reference used for ADC conversion. Any error or shift in reference voltage can be monitored. Current ADC systems on have reference voltages they do not monitor the reference system and due to which error in linearity of the ADC is introduced which cannot be corrected by calibration. ADC’s are used in monitoring system and failure of ADC will result in malfunction of protection and in result it will damage the system. Hence, the present invention monitors reference voltage for error correction. Further, failure of reference voltage is monitored using this system and preventive action for failure will be taken without damaging the system.

[0018] Accordingly, in one implementation, a method for monitoring a drift in at least an analog-to-digital converter (ADC) sample, using a firmware, the method comprises:
• examining the voltage reference (Vref) component and a DC offset computed;
• comparing a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and
• generating at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

[0019] In one implementation, a voltage reference (Vref) monitoring system analog-to-digital converters (ADC) for monitoring a drift in at least an analog-to-digital converter (ADC) sample, the voltage reference (Vref) monitoring system comprises a mechanism configured to examine the voltage reference (Vref) component and a DC offset computed; compare a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and generate at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

[0020] In one implementation, a system comprises at least an analog-to-digital converter (ADC) channel connected to at least one electrical signal sensor configured to generate at least two output signals; at least an amplifier unit configured to receive the output signals generated and amply the signals to generate the amplified signals; and at least one mechanism configured to receive the amplified signals; examine the voltage reference (Vref) component and a DC offset computed; compare a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and generate at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

[0021] Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

[0022] Figure 1 illustrates a reference voltage (Vref) generation using a resistor divider, in accordance with an embodiment of the present subject matter.

[0023] Figure 2 illustrates Vref to analog to digital convertor (ADC) input, in accordance with an embodiment of the present subject matter.

[0024] Figure 3 illustrates a flow chart of a voltage monitoring system in analog to digital convertor, in accordance with an embodiment of the present subject matter.

[0025] Figure 4 illustrates the waveform generated after Vref drift showing the saturation for the voltage exceeding its maximum level.

[0026] Figure 5 illustrates the flowchart of the firmware, in accordance with an embodiment of the present subject matter.

[0027] Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0028] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary.

[0029] Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0030] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.

[0031] It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.

[0032] By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

[0033] Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.

[0034] It should be emphasized that the term “comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0035] Referring now to figure 1, in one implementation, the Vref generated using a resistor divider network. This circuit is normally used in most of the protections relay devices to step up the AC signal for measurement using single ended ADC. Single ended ADC will provide advantages like cost saving, simple hardware etc.

[0036] Referring now to figure 2, in one implementation, to monitor Vref variation it is given as an additional input to the ADC system wherein said ADC is configured to monitor voltage reference variation. The system as disclosed in the present invention is preferably under in relay systems or relay devices.

[0037] Referring now to figure 3, in one implementation, all ADC channels takes average of ADC readings and used them as offset value. The offset value is a Vref value for ADC. During other channel sampling Vref channel is sampled and it is compared with other channel offset computation. A tolerance band is preset which compares the measured offset (through Vref Channel) and preset threshold limit. If the measured offset is out off the set tolerance band then Vref error flag is actuated which is a part of self-Monitoring system. Using this flag user configured decision is taken like trip or alarm.

[0038] In order to understand the working of the present invention, a well known scenario of the CT (Current transformer) and PT (Potential transformer) are considered. The ADC channels are connected to electrical signal sensors like CT (Current transformer) and PT (Potential transformer). The output signals generated by the ADC channels of these sensors are amplified using operation amplifiers (OPAMP’S). It may be understood by the person skilled in the art that, as the systems ground is connected to the neutral sensors, the output swings equally in positive and negative potential side. Most of the ADC chips only support signals above ground level. If dual sided ADC’s can be used but they may increase the cost of the system dramatically.

[0039] In order to measure the signal correctly it may be shifted by the DC voltage which is normally half of the ADC input range to get the equal resolution for positive and negative signal. This DC level is called “Offset” of the system. As average of AC signal is zero, if an average of ADC input signal is taken then the DC level count present in the signal may be obtained. This DC signal is derived from the Vref. Any change in Vref may change the offset signal. The movement of the offset will imbalance the measurement as for positive and negative signal equal signal level may not be present. The figure 4 illustrates the waveform generated after Vref drift showing the saturation for the voltage exceeding its maximum level. As shown in the figure 4, due to the drift in the Vref the waveform goes out of ADC maximum measurable voltage hence the measurement will not be accurate as ADC will goes in to saturation for the voltage exceeding its maximum level.

[0040] In order to monitor the drift in the Vref, in the firmware, the AC samples average will be monitored. If this value exceeds the given band then Vref error will be declared. This is a monitoring implementation. To correct this issue an additional system will be required. Hence a new mechanism as as shown in the Figure 5 illustrates the flowchart of the firmware, in accordance with an embodiment of the present subject matter. In one implementation, as shown in the figure 5, electrical parameter monitoring is performed through ADC and the average value of the ADC will be monitored every cycle as an “Offset” for offset correction in next cycle measurement. In every cycle “Offset” value limits are monitored. If the value is out of set limits then Vref error is reported to user as per user configuration for an example if user has set an alarm on Vref error then and alarm indication will be generated and alarm event will be recorded for future diagnosis. Which channel has violated the limit will also be recorded in record for future diagnosis.

[0041] Accordingly, in one implementation, a method for monitoring a drift in at least an analog-to-digital converter (ADC) sample, using a firmware, the method comprises:
• examining the voltage reference (Vref) component and a DC offset computed;
• comparing a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and
• generating at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

[0042] In one implementation, a voltage reference (Vref) monitoring system analog-to-digital converters (ADC) for monitoring a drift in at least an analog-to-digital converter (ADC) sample, the voltage reference (Vref) monitoring system comprises a mechanism configured to examine the voltage reference (Vref) component and a DC offset computed; compare a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and generate at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

[0043] In one implementation, a system comprises at least an analog-to-digital converter (ADC) channel connected to at least one electrical signal sensor configured to generate at least two output signals; at least an amplifier unit configured to receive the output signals generated and amply the signals to generate the amplified signals; and at least one mechanism configured to receive the amplified signals; examine the voltage reference (Vref) component and a DC offset computed; compare a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and generate at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

[0044] Some of the important features of the present invention, considered to be noteworthy are mentioned below:
1. Vref Monitoring for temperature drift or any misbehavior with Vref.
2. Fault log for ADC reference shift.
3. Trip or alarm for Vref failure as per user configuration.
,CLAIMS:1. A method for monitoring a drift in at least an analog-to-digital converter (ADC) sample, using a firmware, preferably to be used in relay devices, the method comprising:
examining the voltage reference (Vref) component and a DC offset computed;
comparing a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and
generating at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

2. The method as claimed in claim 1, wherein on generation of the error, at least a mechanism is triggered as a security measure of at least one system connected to the ADC, the mechanism is at least one of a trip mechanism or an alarm mechanism or any combination thereof.

3. The method as claimed in claim 1, comprises maintaining at least a log of the DC offset computed and/ or the Vref.

4. A voltage reference (Vref) monitoring system analog-to-digital converters (ADC) for monitoring a drift in at least an analog-to-digital converter (ADC) sample, preferably to be used in relay devices, the voltage reference (Vref) monitoring system comprising:
a mechanism configured to:
examine the voltage reference (Vref) component and a DC offset computed;
compare a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and
generate at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

5. A system comprising:
at least an analog-to-digital converter (ADC) channel connected to at least one electrical signal sensor configured to generate at least output signals, the electrical signal sensor is preferably selected from a current transformer (CT) or a potential transformer (PT);
at least an amplifier unit configured to receive the output signals generated and amply the signals to generate the amplified signals; and
at least one mechanism configured to:
receive the amplified signals;
examine the voltage reference (Vref) component and a DC offset computed;
compare a minimum voltage reference (Vref) component limit and a maximum voltage reference (Vref) component limit with the DC offset computed; and
generate at least an error if the DC offset computed is less than the minimum Vref or is greater than the maximum Vref.

6. The system as claimed in claims 4 and 5, wherein on generation of the error, at least a mechanism is triggered as a security measure of at least one system connected to the ADC, the mechanism is at least one of a trip mechanism or an alarm mechanism or any combination thereof.

7. The system as claimed in claims 4 and 5, wherein at least a log of the DC offset computed and/ or the Vref is maintained in a memory of the ADC.