Claims:
1. A method for accelerating FPGA prototyping for SoC, said method comprising:
translating, by a RTL compiler (304), a plurality of signals of an ASIC RTL code for creating FPGA RTL using at least one of a FPGA resource corresponding with an ASIC resource;
extracting, by the RTL compiler (304), a plurality of constraints from the ASIC RTL code;
generating, by a parser (303), the FPGA RTL and the constraints as output files (305) in a required file format;
automating customization of the ASIC RTL to the FPGA compatible RTL by a plurality of input ASIC RTL files (302).

2. The method as claimed in claim 1, wherein the FPGA RTL and the constraints files comprise keywords as an inline comment for a module information along with the signals to be mapped for the suitable FPGA resource.

3. The method as claimed in claim 1, wherein the parser (303) is embedded within any generic RTL compiler (304).

4. The method as claimed in claim 1, wherein automating customization of the ASIC RTL to the FPGA compatible RTL further includes:
generating a plurality of design and timing constraints files by the input ASIC RTL files (302).

5. The method as claimed in claim 1, wherein generating the FPGA RTL and the constraints as output files (305) in a required file format is done by utilizing a plurality of keywords embedded in the RTL as directives.

6. The method as claimed in claim 1, wherein the generated FPGA RTL and the constraints files are further used for implementation on an FPGA board.

7. The method as claimed in claim 1, wherein the method for generating the FPGA RTL and the constraint files is extended to a plurality of FPGA logic families.

8. A system for accelerating FPGA prototyping using automated generation of design and constraints for SoC, said system comprising:
a RTL compiler (304) configured to translate a plurality of signals of an ASIC RTL code to create FPGA RTL using at least one of a FPGA resource corresponding with an ASIC resource;
the RTL compiler (304) configured to extract a plurality of constraints from the ASIC RTL code;
a parser (303) configured to generate the FPGA RTL and the constraints as output files (305) in a required file format;
a plurality of input ASIC RTL files (302) configured to automate the customization of the ASIC RTL to the FPGA compatible RTL.

9. The system as claimed in claim 8, wherein the system is further configured to generate a plurality of design and timing constraints files by the input ASIC RTL files (302).

10. The system as claimed in claim 8, wherein the parser (303) configured to generate the FPGA RTL and the constraints as output files (305) in a required file format wherein the generation is done by utilizing a plurality of keywords embedded in the RTL as directives.

11. The system as claimed in claim 8, wherein the parser (303) configured to generate the FPGA RTL and the constraints files is further used in FPGA design and implementation flow.

12. The system as claimed in claim 8, said system includes a processor, memory, operating system and a RTL compiler (304) which is a part of a computing environment (301) to generate the FPGA RTL (305) and constraints (306).

13. The system as claimed in claim 8, wherein the system to generate the FPGA RTL and the constraint files is extended to a plurality of FPGA logic families.
, Description:FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

A SYSTEM FOR ACCELERATING FPGA PROTOTYPING USING AUTOMATED GENERATION OF DESIGN AND CONSTRAINTS FOR SOC AND A METHOD THEREOF

BHARAT ELECTRONICS LIMITED

WITH ADDRESS:
OUTER RING ROAD, NAGAVARA, BANGALORE 560045, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED. 

TECHNICAL FIELD
[0001] The present invention relates generally to a system for Field Programmable Gate Arrays (FPGA) prototyping using automated generation of design and constraints for System on Chip (SoC) and a method thereof. The invention more specifically relates to a system and a method for performing customization for Application Specific Integrated Circuit (ASIC) Register Transfer Level (RTL) to obtain FPGA RTL and extraction of the constraints for customized FPGA RTL.

BACKGROUND
[0002] Most of the IC designs designed these days are complex in nature. A typical FPGA implementation includes integration of IP blocks for board activities and integrated chip prototyping before getting the product into market. The IP’s (Intellectual Properties) could be developed by own or procured from third party vendors for integration purpose. These IP’s are in standard Verilog format. The IP blocks are integrated to obtain subsystems and further subsystems are integrated to obtain top level design of SoC or an integrated chip.
[0003] Design is described in IP’s or blocks and sub-blocks using a high-level language (Verilog/VHDL). These designs are simulated by behavioural/gate-level Verilog/VHDL simulators. Before designs are being fabricated on to silicon it has to be simulated for proper functionality. Design validation is one of the most important and difficult tasks in SoC design because without full functional verification design errors are neither found nor removed. Because of the slow simulation speed and large size of SoC design, SoC level design validation is almost a very difficult task with methodologies and tools available in market today.
[0004] Further, manually changing the ASIC RTL is a tedious task and increases the timeline for FPGA prototyping activity.
[0005] US20050183055A1 discloses a design of programmable logic devices, such as FPGAs, may be automated to allow scripts, setup files, and other tool files to be created directly from hollowed and filled netlist, and data-path and design constraint files without extensive human intervention. This allows an FPGA design to be created directly from a logic file to accelerate the FPGA design process. Once hollowed and filled netlists, and data-path and design constraint files have been generated from a design in a standard fashion, the implementation of that design onto an FPGA in an optimized fashion is automated by providing a computer program that is capable of implementing the design, testing the design, evaluating the test results, and altering the design to arrive at a more optimal design. The process may include several steps, such as initial placement of logic groups, sizing of logic groups and FPGA selection, timing analysis, and filled netlist complete design review.
[0006] US6678645B1 discloses a method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The apparatus allows to use a method which includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches developed by an SoC designer and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of the overall SoC and application runs.
[0007] US9959379 relates to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.
[0008] In the above-mentioned prior arts, the programmable logic devices like FPGAs are automated to allow scripts, setup files, and other tool files to be created directly from hollowed and filled netlist, and data-path and design constraint file to accelerate FPGA design process. This approach involves lot of manual work before the automated process involving netlist. This leads to a delay in the earlier stages of FPGA development flow cycle.
[0009] Therefore, there is still a need of a technical solution which solves the above defined problems and provide a method and a system of automation to obtain customized FPGA RTL from ASIC RTL, extraction & generation of corresponding constraints for accelerating FPGA implementation.

SUMMARY
[0010] This summary is provided to introduce concepts related to a system for accelerating Field Programmable Gate Arrays (FPGA) prototyping using automated generation of design and constraints for System on Chip (SoC) and a method thereof. The invention more specifically relates to a system and a method for performing customization for Application Specific Integrated Circuit (ASIC) Register Transfer Level (RTL) to obtain FPGA RTL and extraction of the constraints for customized FPGA RTL.
[0011] In an embodiment of the present invention, a FPGA prototyping platform design for a system is disclosed which prototypes the SoC (System on Chip modules) for Integrated Chip design, wherein the prototyping has to give confidence on functionality of designed module with intended specification, where constraints applied on the design plays an important role in meeting those requirements.
[0012] For FPGA prototyping of a SoC, RTL needs to be configured manually for FPGA board implementation flow. There is a need for customization of the RTL before using it for FPGA prototyping. The proposed method of implementation provides a novel approach of ASIC RTL customization by including constructs and parsing through a parser/script for generating the FPGA RTL. It also maps them with a FPGA device resource by parsing the keywords provided in RTL for customization and constraints extraction. This reduces the complexity of manual customization and constraints creation in FPGA design cycle and brings out early implementation of integrating design IPs on a FPGA platform.
[0013] The advantage of the present invention includes early signoff design cycle, reducing manual work for ASIC RTL customization, constraints file generation and acceleration of FPGA Implementation cycle.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0014] The detailed description is described with reference to the accompanying figures.
[0015] Figure 1 illustrates a block diagram of a standard FPGA flow cycle, in accordance with an exemplary embodiment of the present invention.
[0016] Figure 2 illustrates a block diagram of standard manual FPGA RTL customization along with reading constraints during the FPGA implementation flow, in accordance with an exemplary embodiment of the present invention.
[0017] Figure 3 illustrates a block diagram of a system required for automating customization of ASIC RTL and generation of FPGA RTL with constraints, in accordance with an exemplary embodiment of the present invention.
[0018] Figure 4 illustrates a block diagram of the FPGA implementation flow using generated files, in accordance with an exemplary embodiment of the present invention.
[0019] Figure 5 illustrates a block diagram of the traditional ASIC and FPGA implementation flow, where novel approach for FPGA is needed, in accordance with an exemplary embodiment of the present invention.
[0020] Figure 6 illustrates a block diagram of a SoC 600 with memory and different peripherals, in accordance with an exemplary embodiment of the present invention.
[0021] Figure 7 illustrates a flowchart of a method for automating customization of the ASIC RTL and generation of the FPGA RTL with constraints, in accordance with an embodiment of the present invention.
[0022] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
[0023] The various embodiments of the present invention describe about a system for accelerated Field Programmable Gate Arrays (FPGA) prototyping using automated generation of design and constraints for System on Chip (SoC) and a method thereof.
[0024] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0025] However, the apparatuses and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.
[0026] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[0027] The appearances of the phrase “in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[0028] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0029] One or more IPs, subsystems or a top level design can be referred to as a design. Complexity of the design depends on the final product requirement. The FPGA prototyping of such design is carried out to give a tape-out confidence on SoC functionality. Integration of different IP blocks like Ethernet, USB, GPU, VPU etc. are done and the integrated designs are constrained to work based on specified design constraints, and the analysis of timing is done for the same to check if design is working for intended specification which is a process of multiple iterations and time consuming.
[0030] There are certain design attributes in ASIC RTL which require manual changes for prototyping in FPGA. Some of them can be used as guidelines for choosing appropriate FPGA and its resources. Gate count, clocks/resets, embedded processor, memories, number of IOs, PLLs/DLLs, and IO standards stands as main choosing criteria. Generic assumption on resources of the board should be at least 40% higher as part of initial FPGA prototype framework. There are some of the ASIC attributes to be changed in FPGA RTL such as Memories and Register arrays, Clock gating replacement, IO arrays (Pads in ASIC) and PLL replacement. Further, customizing the ASIC RTL to FPGA RTL demands the designer to include the above mentioned changes for various versions of the ASIC RTL that are obtained through multiple iterations during the design cycle.
[0031] The advantage of the present invention includes early signoff design cycle, reducing manual work for ASIC RTL customization, constraints file generation and acceleration of FPGA implementation cycle.
[0032] In an embodiment of the present invention, a method for accelerating FPGA prototyping for SoC is disclosed. This method comprises translating a plurality of signals of an ASIC RTL code for creating FPGA RTL using at least one of a FPGA resource corresponding with an ASIC resource and extracting a plurality of constraints from the ASIC RTL code. Further, the method includes generating the FPGA RTL and the constraints as output files (305) in a required file format and automating customization of the ASIC RTL to the FPGA compatible RTL by a plurality of input ASIC RTL files.

[0033] In another embodiment, the FPGA RTL and the constraints files comprise keywords as an inline comment for a module information along with the signals to be mapped for the suitable FPGA resource.

[0034] In another embodiment, the parser is embedded within any generic RTL compiler.

[0035] In another embodiment, the method for automating customization of the ASIC RTL to the FPGA compatible RTL further includes generating a plurality of design and timing constraints files by the input ASIC RTL files.
[0036] In another embodiment, the method for generating the FPGA RTL and the constraints as output files in a required file format is done by utilizing a plurality of keywords embedded in the RTL as directives.
[0037] In another embodiment, the generated FPGA RTL and the constraints files are further used for implementation on an FPGA board.
[0038] In another embodiment, the method for generating the FPGA RTL and the constraint files is extended to a plurality of FPGA logic families.
[0039] In another embodiment, a system for accelerating FPGA prototyping using automated generation of design and constraints for SoC is disclosed. The system comprises a RTL compiler configured to translate a plurality of signals of an ASIC RTL code to create FPGA RTL using at least one of a FPGA resource corresponding with an ASIC resource. The RTL compiler is further configured to extract a plurality of constraints from the ASIC RTL code. Further the system comprises a parser which is configured to generate the FPGA RTL and the constraints as output files in a required file format. A plurality of input ASIC RTL files are configured to automate the customization of the ASIC RTL to the FPGA compatible RTL.

[0040] In another embodiment, the system is further configured to generate a plurality of design and timing constraints files by the input ASIC RTL files.
[0041] In another embodiment, the parser configured to generate the FPGA RTL and the constraints as output files in a required file format wherein the generation is done by utilizing a plurality of keywords embedded in the RTL as directives.
[0042] In another embodiment, the parser configured to generate the FPGA RTL and the constraints files is further used in FPGA design and implementation flow to accelerate FPGA prototyping.
[0043] In another embodiment, the system includes a processor, memory, operating system and a RTL compiler which is a part of a computing environment to generate the FPGA RTL and the constraints.
[0044] In another embodiment, the system to generate the FPGA RTL and the constraint files is extended to a plurality of FPGA logic families.
[0045] Figure 1 illustrates a block diagram of a standard FPGA flow cycle, in accordance with an exemplary embodiment of the present invention. This is an exemplary FPGA implementation flow 100 for integration of different IP blocks which includes RTL Verilog code and design constraints. The IP blocks may be designed or procured from multiple third party vendors.
[0046] Figure 2 illustrates a block diagram of standard manual FPGA RTL customization along with reading constraints during the FPGA implementation flow, in accordance with an exemplary embodiment of the present invention. The prototyping begins with register-transfer level (RTL) integration of the IP blocks 202, 203. Verification is carried out for the integrated IP blocks. Synthesis 206 and design implementation 207, including translate, map, place and route, is carried out on the verified design. The logic is implemented within FPGA pre-defined blocks (LUT’s) which are inferred as registers to form a layout. Finally, bitmap file is generated and programmed on the FGPA which can be verified for its functionality.
[0047] Further, the design and timing constraints 205 differ widely for various IP blocks used at the time of integration 204for implementation purpose are received in separate file formats like ucf, xdc, sdc etc. These file formats are combined together to one single format for ease of implementation purpose which is done manually. A GUI interface in FPGA tools are used for manually creating constraints, which consumes more time and delays implementation process for prototyping.
[0048] As part of the integration 202, ASIC RTL design requires customization and has to be ensured from the designer perspective for functionality of top level design working at desired frequency post implementation. This is performed by developing design and timing constraints during FPGA integration 203.
[0049] Furthermore, the design and timing constraints, like creating clock frequency, defining MCP (multicycle path) and false paths, etc. are developed for performing static timing analysis (STA) during implementation to ensure the blocks are working at targeted frequencies. Generating these constraints and customized FPGA design through automation provides optimized approach of having less iteration compared to standard approach of implementing design and analysing results.
[0050] In FPGA prototyping, IP blocks are constrained for lenient frequency, whereas in ASIC implementation, the IP block constraints are very stringent. FPGA constraints (for both design & timing) development has reasonable significance in getting design functional and for such task to be performed by integrating IP blocks, the design and timing constraints 205 need to be taken properly from the different IP sources. There are problems with creating constraints for implementation; the first one being no standard method available for providing constraints. Secondly, the constraints are in different file formats which demands designer to develop custom constraint format. Lastly, designer encounters issues due to incorrect development of constraints, leading to errors and poor results during implementation phase.
[0051] In addition to the RTL design team, the implementation team also manually develop constraints. This manual approach might lead to incorrect generation of final constraints which results in multiple iterations and delaying the Implementation phase.
[0052] Figure 3 illustrates a block diagram of a system required for automating customization of ASIC RTL and generation of FPGA RTL with constraints, in accordance with an exemplary embodiment of the present invention. The system consists of required ASIC RTL input files 302 for customization, a RTL compilation tool 304, a script/parser 303 for generating customized FPGA RTL 305 and constraints 306 as output files in the required format. All these are included in a computing environment 301 which executes one or more instruction based on compiler directive.
[0053] Figure 4 illustrates a block diagram of the FPGA implementation flow using generated files through novel approach used in FPGA RTL integration 402, in accordance with an exemplary embodiment of the present invention. The standard RTL Verilog codes containing module information and constraints 401 are used as inputs 302 for processing and generating required file formats 305, 306. These files can be further used for synthesis 405 and implementation 406.
[0054] Figure 5 illustrates a block diagram of the traditional ASIC and FPGA implementation flow, in accordance with an exemplary embodiment of the present invention. The standard RTL Verilog codes after design stages 501 are used as inputs for processing and generating required file formats 305, 306. Once these files are obtained, subsequently they are used in read design 503 and synthesis 506 stages of FPGA implementation flow, the box represented with dashed lines.
[0055] Figure 6 illustrates a block diagram of a SoC 600 with memory and different peripherals, in accordance with an exemplary embodiment of the present invention. The SoC 600 consists of various masters like processor, DMA and graphics processor which will be interfacing with the slave interface. The processor will have access to peripherals through these serial interfaces, high speed interfaces, I/O interfaces and other memory interfaces all connected through a common bus interface i.e. the interconnect 602. The SOC can include a processor 601, which communicate through a interconnect 602 to various memory and peripheral devices such as I/O interfaces 606 serial interfaces 604, high speed interfaces 603 and other memory 605. Other memory can be conventional memories such as DRAM, SRAM or flash that can interface to processor 601 through a memory controller. The processor 601 generally can be a microprocessor, a digital signal processor, or other programmable digital logic devices.
[0056] Figure 7 illustrates a flowchart of a method for automating customization of the ASIC RTL and generation of the FPGA RTL with constraints, in accordance with an embodiment of the present invention.
[0057] At step 701, reading the ASIC RTL files into the developed system.
[0058] At step 702, extracting the design information such as the module information, clock, constraints from the ASIC RTL files.
[0059] At step 703, matching the FPGA Resource available on the board and generating the FPGA implementable RTL module for FPGA implementation.
[0060] At step 704, extracting the constraints from the ASIC RTL and generating the constraint file for FPGA implementation.
[0061] At step 705, using the generated FPGA RTL and constraints files further for design synthesis and implementation on an FPGA board.
[0062] At step 706, generating a bit stream file for FPGA validation.
[0063] In the present implementation, the generation of Verilog RTL files and constraints files using the disclosed method for any technology node will accelerate the process of validating the designs for functionality and gives high confidence to fabricate design on silicon. The disclosed method can be extended to any FPGA families and can be added as a common method in generating these files across all FPGA families and their corresponding flow. So to achieve this, the turnaround time might increase through conventional approach. Wherein with the present invention with less turnaround time it is possible to get good results. Also, this will help in avoiding emulation cycle.
[0064] In an exemplary implementation as given below, design 1 is a normal ASIC RTL code for fuse memory wrapper. The same code with required modification from ASIC to FPGA shown in Design 2. The Design 3 contains the fragment of the code that needs to be mapped from an ASIC memory module to available FPGA memory module. The Design 4 contains the mapped code fragment for FPGA memory module. The “ifdef” statement is used in RTL for choosing appropriate memory for FPGA RTL as shown in Design 4 of fuse memory wrapper. This memory instance is read as block from library in ASIC through a proper library setup. Similarly FPGA flow can have a resource library setup to map the resources with ASIC resource.
Design 1:
// * mod_mem* : *rom_1p*//
// *mod_fcm* : *clk_10Mhz* //
module fuse_wrap (
input reset_b, //reset
input fcm_clk;
input [12:0] A, //address
input READ_EN,
input CEB,
input CLE
input DLE
input WEB
input CPUMPEN
input DIN
output [7:0] D,
output LOCK
);
assign D = 0;
assign LOCK = 0;
end module
Design 2:
// * mod_mem* : *rom_1p*//
// *mod_fcm* : *clk_10Mhz* //
module fuse_wrap (
input reset_b, //reset
inputfcm_clk; //*I_S1
input [12:0] A, //*I_S2
input READ_EN, //*I_S3
input CEB, //*I_S4
input CLE
input DLE
input WEB
input CPUMPEN
input DIN
output [7:0] D, //*O_S5
output LOCK
);
assign D = 0;
assign LOCK = 0;
end module
Design 3: Fuse cell code fragment
fpga_fuse_mem rom_1p(.addra ({3’d0,I_S2}),
.clka (~I_S1),
.douta (O_S5),
.ena (~(!I_S4 & I_S3) )
);

Design 4 : Mapped fuse cell code fragment
`ifdef_fpga
fpga_fuse_mem rom_1p(.addra ({3’d0,A[12:3]}),
.clka (~fcm_clk),
.douta (D),
.ena (~(!CEB & READ_EN) )
);
`else
assign D = 0;
assign LOCK = 0;
`endif
end module
[0065] The fuse cell code fragment shown above is used in parser/script embedded in system which parses and maps the signals available original ASIC RTL. This is used for automation of customized FPGA RTL from ASIC RTL. In the mapped fuse code segment the signal I_S1 (Input Signal 1) mapped to fcm_clk, I_S2 (Input Signal 2) mapped to Address signal A, O_S5 (Output Signal) is mapped to signal D. I_S3 (Input Signal 3) is mapped to READ_EN and IS_4 (Input Signal 4) mapped to CEB.
[0066] Similarly, a FPGA implementation can have a flow setup which gives complete resource information available and can be enclosed in ready file formats as shown in fuse cell code fragment, script then parses and maps the signals available in board resource to create RTL of compatible FPGA device. The probability of functionality mismatch is also less. One approach is that these compiler directives are supposed to be added in ASIC RTL code only once in the beginning for FPGA prototyping and further it is obtained any number of times through script/parser. Further, the constructs of different devices like PLL, clock mux can also be inferred through this approach. After making these changes in the ASIC RTL code, running simulations give functionality confidence and guarantees the design sanity.
[0067] IP block-level constraints can comprise clock definitions (regular and generated), exceptions (false paths, multi cycle paths), operating modes and input/output (I/O) constraints. Any such keywords can be included in heading or comment section in the RTL code as shown above in Design 1. Developed script/compiler directive can extract clock constraint in separate file and can be used as ucf or xdc in FPGA implementation at the beginning of the comment, where “*fcm_clk:10Mhz*” can be a clock name or keyword that can be interpreted by an extraction script. The extraction script can extract the timing constraints from the IP block level to the FPGA top design. An example of create clock statement might be as follows:
//*fcm_clk:10Mhz*//
Create_clock [get_ports fcm_clk] –period 100 –waveform {0 50}
[0068] Here “*fcm_clk*” is of frequency 10 MHz, period and waveform defines can also be included or script can add the same in generated sdc file. Indication on main clock or generated clock has to be specified. In the below example code which contains no generated clock and with clock frequency of 100Mhz, having multi cycle path of 2 for setup can be represented with below keywords in commented heading section can be extracted for constraints with module named as generic for FPGA synthesis and implementation.
CODE 5: (Example on multicycle path constraint extraction)

//*clk_name* : *clk1_200Mhz* :*period* : *gen_clk* //
//*mod_generic* : *clk2_100Mhz*:*mcp_2_setup* //
process begin
if rising_edge(clk) then
enb_dly<= en;
if (en == '1')
A_reg<= A;
B_reg<= B;
endif
if (enb_dly == '1')
C <= A_reg * B_reg; // 2MCP
endif
set multi_cycle_path –{hold |setup} –from -to

[0069] In the above exemplary code the module C is assigned a value in two clock cycles where clock name, frequency are provided as *clk_name* *clk1_200Mhz* constructs respectively, multicycle path construct is provided as *mcp_2_setup* which represents 2 cycles for setup. The extractor can create FPGA constraints of clock creation, and multicycle path from above code shown as follows.
Create_clock [get_portsclk] –period 200 –waveform {0 100}
set multi_cycle_path 2 –{setup} –from {start_point} -to {End_point}
[0070] To conclude, generation of customized FPGA RTL and constraints files through the proposed automation method will speed up the implementation process and reduce the iterations involved in manual way of creating files.
[0071] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.