The present invention relates to a system for method for controlling compatibility levels of binary translations between instruction set architectures and an apparatus thereof. FIELD OF THE INVENTION [0001] The invention relates to computer processing. More specifically, the invention relates to translation of binaries across different instruction set architectures or different levels of optimizations with a same instruction set architecture. BACKGROUND OF THE INVENTION [0002] While current compilers of program code are designed to generate binaries that take advantage of the latest developments of current instruction set architectures (ISA), binaries generated based on a prior instruction set architecture are not able to employ these latest developments. Binary translation is a common method used to translate binaries of given program code/applications that are based on one instruction set architecture into binaries of given program code/applications that are based on a different instruction set architecture or a different subset of the same instruction set architecture. The different instruction set architecture may be a different architecture or an advanced version of the prior instruction set architecture. [0003] Typically, binary translated programs are expected to deliver precisely the same functionality as provided by the original binary translated program that was based on the prior instruction set architecture. In other words, binary translations are typically expected to fully preserve program semantics as defined by the previous instruction set architecture, thereby providing full backward compatibility. Accordingly, the requirements of the previous instruction set architecture can include those associated with normal instruction flow, data precision, behavior of exceptions and other side effects of program execution defined by this previous instruction set architecture. [0004] This semantic requirement typically confines the power of the binary translation — either by posing certain limitations on the translatable binaries or by restricting the amount of advantage the binary translation can take of the new instruction set architecture. For example, if the two different instruction set architectures do not support the same floating-point formats, widths or precisions, the binary translation between these instruction set architectures of floating-point operations maybe difficult and/or inefficient. BRIEF DESCRIPTION OF THE DRAWINGS [0005] Embodiments of the invention may be best understood by referring to the following description and accompanying drawings that illustrate such embodiments. The numbering scheme for the Figures included herein are such that the leading number for a given element in a Figure is associated with the number of the Figure. For example, system 100 can be located in Figure 1. However, element numbers are the same for those elements that are the same across different Figures. [0006] In the drawings: [0007] Figure 1 illustrates an exemplary system 100 comprising processors 102 and 104 for controlling compatibility levels of binary translations between instruction set architectures, according to embodiments of the present invention. [0008] Figure 2 illustrates a more detailed diagram of a processor and associated memory, according to embodiments of the present invention. [0009] Figure 3 illustrates a flow diagram for translation of instructions from a binary based on a first instruction set architecture to instructions from a second instruction set architecture that is partially compatible with the first instruction set architecture, according to embodiments of the present invention. [0010] Figure 4 illustrates source code and the generated assembly code wherein a register is and is not employed as part of the hardware stack, according to embodiments of the present invention. DETAILED DESCRIPTION [0011] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. [0012] Embodiments of the present invention allow for a partially compatible instruction set architecture, wherein a binary of a program code that is generated for a first instruction set architecture is translated into a binary that employs certain features of a second instruction set architecture while remaining partially compatible with the first instruction set architecture. In an embodiment, the level of compatibility is controlled by the program environment, including, but not limited to, the user, the compiler and operating system. In one such embodiment, a set of compatibility modes or switches is defined on top of the second instruction set architecture. Accordingly, the program environment can explicitly set the desired compatibihty mode. In one embodiment for hardware translation, the setting of the compatibility mode can be through a set of hardware instructions. In an embodiment for software translation, this setting of the compatibility mode can be through a number of command line flags used in conjunction with the initiation of the execution of the binary. [0013] Therefore, as will be described in more detail below, embodiments of the present invention allow for an improvement in performance (related to the second instruction set architecture) in exchange for some deviation from the precise program semantics (related to the first instruction set architecture). [0014] Additionally, in an embodiment, the different instruction set architectures on which the binaries (described herein) are based may be any of a number of different instruction set architectures, including, but not limited to, the different Complex-Instruction-Set-Computer (CISC) instruction sets as well as the different Reduced-Instruction-Set Computer (RISC) instruction sets. Examples of such instruction set architectures include Intel® IA-32 and Intel® IA-64. [0015] Figure 1 illustrates an exemplary system 100 comprising processors 102 and 104 for controlling compatibility levels of binary translations between instruction set architectures, according to embodiments of the present invention. Although described in the context of system 100, the present invention may be implemented in any suitable computer system comprising any suitable one or more integrated circuits. [0016] As illustrated in Figure 1, computer system 100 comprises processor 102 and processor 104. Computer system 100 also includes memory 132, processor bus 110 and input/output controller hub (ICH) 140. Processors 102 and 104, memory 132 and ICH 140 are coupled to processor bus 110. Processors 102 and 104 may each comprise any suitable processor architecture and for one embodiment comprise an Intel® Architecture used, for example, in the Pentium® family of processors available from Intel® Corporation of Santa Clara, California. Computer system 100 for other embodiments may comprise one, three, or more processors any of which may execute a set of instructions that are in accordance with embodiments of the present invention. [0017] Memory 132 stores data and/or instructions, for example, for computer system 100 and may comprise any suitable memory, such as a dynamic random access memory (DRAM) for example. Graphics controller 134 controls the display of information on a suitable display 136, such as a cathode ray tube (CRT) or liquid crystal display (LCD), for example, coupled to graphics controller 134. [0018] ICH 140 provides an interface to I/O devices or peripheral components for computer system 100. ICH 140 may comprise any suitable interface controllers to provide for any suitable communication link to processors 102/104, memory 132 and/or to any suitable device or component in communication with ICH 140. ICH 140 for one embodiment provides suitable arbitration and buffering for each interface. [0019] For one embodiment, ICH 140 provides an interface to one or more suitable integrated drive electronics (IDE) drives 142, such as a hard disk drive (HDD) or compact disc read only memory (CD ROM) drive for example, to store data and/or instructions for example, one or more suitable universal serial bus (USB) devices through one or more USB ports 144. ICH 140 for one embodiment also provides an interface to a keyboard 151, a mouse 152, one or more suitable devices, such as aprmter for example, through one or more parallel ports 153, one or more suitable devices through one or more serial ports 154, and a floppy disk drive 155. [0020] Additionally, computer system 100 includes translation unit 180. In an embodiment, translation unit 180 can be a process or task that can reside within main memory 132 and/or processors 102 and 104 and can be executed within processors 102 and 104. However, embodiments of the present invention are not so limited, as translation unit 180 can be different types of hardware (such as digital logic) executing the processing described therein (which is described in more detail below). [0021] Accordingly, computer system 100 includes a machine-readable medium on which is stored a set of instructions (i.e., software) embodying any one, or all, of the methodologies described herein. For example, software can reside, completely or at least partially, within memory 132 and/or within processors 102/104. For the purposes of this specification, the term "machine-readable medium" shall be taken to include any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc. [0022] Figure 2 illustrates a more detailed diagram of a processor, according to embodiments of the present invention. In particular, Figure 2 illustrates a more detailed diagram of one of processors 102/104 (hereinafter "processor 102"). As shown, memory interface unit 270 is coupled to cache buffers 256, register file 250 (that includes general purpose registers 252 and special purpose registers 254) and instruction buffer 202, such that memory interface unit 270 can retrieve macro instructions and associated operands and store such data into instruction buffer 202 and cache buffers 256, general purpose registers 252 and/or special purpose registers 254. Additionally, cache buffers 256 and register file 250 are coupled to decoder 204, functional units 212-218 and retirement logic 228. [0023] Decoder 204 is coupled to instruction buffer 202, such that decoder 204 retrieves the instructions from instruction buffer 202. Decoder 204 can receive these instructions and decode each of them to determine the given instruction and also to generate a number of instructions in an internal instruction set. For example, in one embodiment, the instructions received by decoder 204 are termed macro instructions, while the instructions that are generated by decoder 204 are termed micro instructions (or micro-operations). Decoder 204 is also coupled to instruction scheduler 208, such that instruction scheduler 208 can receive these micro-operations for scheduled execution by functional units 212-218. [0024] Instruction scheduler 208 is coupled to dispatch logic 226, such that the instruction scheduler 208 transmits the instructions to be executed by functional units 212-218. Dispatch logic 226 is coupled to functional units 212-218 such that dispatch logic 226 transmits the instructions to functional units 212-218 for execution. Functional units 212-218 can be one of a number of different execution units, including, but not limited to, an integer arithmetic logic unit (ALU), a floating-point unit, memory load/store unit, etc. Functional units 212-218 are also coupled to retirement logic 228, such that functional units 212-218 execute the instructions and transmit the results to retirement logic 228. Retirement logic 228 can transmit these results to memory that can be internal or external to processor 102, such as registers within register file 250 or cache buffers 256, or memory 132 (external to processor 102). [0025] The operations of computer system 100 will now be described in more detail in conjunction with the flow diagram of Figure 3. In particular, Figure 3 illustrates a flow diagram for translation of instructions from a binary based on a first instruction set architecture to instructions from a second instruction set architecture that is partially compatible with the first instruction set architecture, according to embodiments of the present invention. [0026] Flow diagram 300 of Figure 3 is described as part of the decode-execute flow of computer system 100. However, embodiments of the present invention are not so limited. For example, in another embodiment, the translation operations illustrated in flow diagram 300 could be performed independent of the decode-execute flow of computer system 100. In one such embodiment, the translated instructions could be stored in a special buffer (either internal or external to processor 102), such as a trace cache (not shown in Figure 1). Accordingly, such translated instructions could be retrieved from this special buffer and executed within processor 102. Therefore, in such an embodiment, the level of compatibility is optional, such that processor 102 may or may not execute the translated instructions depending on its current knowledge or resources. For example, the translated instructions may be executed in a first environment (wherein the translated instructions are fully exploited), while not being executed in a second environment (wherein the execution of the translated instructions does not increase performance execution). Moreover, in an embodiment, a subset of the translated instructions is incorporated into the execution of the binary. For example, a given instruction may be translated a number of times. However, in an embodiment, the number of times this translated instruction is incorporated into the execution of the binary is less than the total number of times the instruction is translated. [0027] At process block 302, a first binary of a program code based on a first instruction set architecture is received. In one embodiment, translation unit 180 receives this first binary of a program code based on a first instruction set architecture. In an embodiment, decoder 204 receives this first binary of a program code based on a first instruction set architecture. In one embodiment, both translation unit 180 and decoder 204 can receive this first binary of a program code based on the first instruction set architecture. [0028] In one embodiment, translation unit 1 SO is employed to perform a software translation of this first binary based on a first instruction set architecture into a second or different binary based on a combination of the first instruction set architecture and a second instruction set architecture. In an embodiment, decoder 204 is employed to perform a hardware translation of this first binary based on a first instruction set architecture into a second or different binary based on a combination of the first instruction set architecture and the second instruction set architecture. As will be described in more detail below, in one embodiment, software translation of a binary by translation unit 180 can be used in conjunction with hardware translation of a same binary by decoder 204. In another embodiment, software translation of a binary by translation unit 180 is exclusive of hardware translation of the same binary by decoder 204 and vice versa. [0029] At process block 304, instruction set architecture execution flags are checked to determine possible translations of the first binary. In one embodiment, translation unit 180 checks instruction set architecture execution flags to determine possible translation of the first binary. In an embodiment, decoder 204 checks instruction set architecture execution flags to determine possible translation of the first binary. Although translation unit 180 can determine possible translation of the first binary through different techniques, in an embodiment, translation unit 180 determines this possible translation of the first binary by checking command line flags that are accepted in conjunction with the command to begin execution (that can include this translation) of this first binary. For example, if the name of the first binary were