"A System For Maintaining The Integrity Of Data Transfers In Shared Memory Configuration"

Abstract: The instant invention describes a system for maintaining the integrity of data transfers in shared memory configuration by different processes to a data buffer located in the contiguous memory locations. The accesses by the different processes can be at the same time. The proposal has been developed for a system employing CISC CPU, a peripheral using Direct Memory Access (DMA) controller both of which has a 8-bit data bus. The Memory Interface is provided with a sequencer and registers coupled a to Random Access Memory (RAM). The sequencer controls the read and write operations of the RAM and ensures atomic transfer of multiple bytes to the RAM by one process invoking a special mode. This ensures that the other processes either read the old set of data or the new set of data with a minimum delay.

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