Claims:1. A system for protection of an electric circuit from high fault current, the system comprising:
a sensing unit operatively coupled to the electric circuit to be protected, the sensing unit configured to monitor current flowing through the electric circuit, and correspondingly generate a first set of signals;
a multiplier operatively coupled to the sensing unit, and configured to generate a second set of signals based on the first set of signals received from the sensing unit, wherein the second set of signals corresponds to square of the monitored current;
an averaging unit operatively coupled to the multiplier, and configured to generate a third set of signals based on the second set of signals received from the multiplier, wherein the third set of signals corresponds to square of a root mean square (RMS) value of the monitored current;
an integrator unit operatively coupled to the averaging unit, and configured to generate a fourth set of signals based on the third set of signals received from the averaging unit, wherein the fourth set of signals corresponds to thermal energy dissipated by the electric circuit due to the monitored current; and
a first comparator operatively coupled to the integrator unit, and configured to generate a first set of trip signals when the thermal energy corresponding to the fourth set of signals exceed a first threshold value, wherein the first comparator is configured to transmit the first set of trip signals to a switching unit of the electric circuit to restrict flow of current through the electric circuit after a predefined interval of time.
2. The system as claimed in claim 1, wherein the system comprises a second comparator operatively coupled to the sensing unit, and configured generate a second set of trip signals when the monitored current corresponding to the first set of signals exceeds a second threshold value.
3. The system as claimed in claim 2, wherein the second comparator is configured to transmit the second set of trip signals to the switching unit of the electric circuit to instantaneously restrict flow of current through the electric circuit.
4. The system as claimed in claim 2, wherein the first comparator and the second comparator are operatively coupled to the switch unit through an OR circuit.
5. The system as claimed in claim 4, wherein the system comprises a thermal memory unit configured between the OR circuit and the switching unit, wherein the thermal memory unit is configured to determine a second time interval required to be elapsed before resetting the switching unit.
6. The system as claimed in claim 1, wherein the predefined interval of time corresponds to a trip time of the first comparator, and wherein the trip time is inversely proportional to the square of the RMS value of the monitored current.
7. The system as claimed in claim 1, wherein the averaging unit comprises a low-pass RC filter.
8. The system as claimed in claim 1, wherein the switching unit comprises any or a combination of power electronics switch, circuit breaker, and solid-state power controller.
9. The system as claimed in claim 1, wherein the first threshold value of the first comparator is 140% of a nominal value of current of the electric circuit, and wherein the second threshold value of the second comparator is 1000% of the nominal value of current of the electric circuit.
10. The system as claimed in claim 1, wherein the system is configured to operate for any or a combination of a static load current condition and a dynamic load current condition.
, Description:TECHNICAL FIELD
[0001] The present disclosure relates to the field of electrical circuit protection system. More particularly, the present disclosure relates to electronic protection system that behaves as a conventional electrical fuse or a circuit breaker to protect electrical circuits of radar or other similar applications to quickly isolate the high fault current according to an I2T function.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Circuit protection devices like fuses and circuit breakers are designed to protect a conductor against over-current and short circuit incidents. To prevent over-heating and potential damage to the conductor and the electronic systems connected, an electronic protection device is conventionally configured to trip before a thermal capacity of the conductor is exceeded.
[0004] Solid state power controllers (SSPCs) behave like fuses and circuit breakers by monitoring the current passing through the conductor and calculating the amount of power (I2R) dissipated by the conductor over time. The trip time of the solid-state devices is inversely proportional to the dissipated power (i.e., the square of current). The trip characteristic of these devices, which determines the trip time, is often referred to as the I2t trip characteristic where I is the load current, and t is the elapsed time and may be mathematically expressed through the following equation:

[0005] The time delay for overcurrent shut-down is determined according to the amount by which the load current exceeds the limit of I2t. The first signal function is generated by squaring and averaging the current value and then integrating the sameover time, to achieve a true I2t trip characteristic. Conventional implementations of the above I2t trip characteristic involve the use of piece wise linear approximation for the multiplication of the current signal. However, the use of piece wise linear circuit may increase the size, complexity and power consumption due to a greater number of discrete devices.
[0006] Fuses and mechanical circuit breakers are well known protection devices that can provide instant tripping in case of high fault currents and delayed tripping in case of lower load currents. Although these functions are provided by these devices acceptably well, there are applications for which these conventional devices are not well suited. Replacement of blown fuses in certain applications is very inconvenient.
[0007] Advances in solid state and computer technology resulted in the development of Solid-State Power Controllers that include the performance characteristics of traditional thermal circuit breakers. One such approach is described in U.S. Pat. No. 5,723,915. In that protection mechanism, there is provided an I2RC section that produces an analog voltage proportional to the wire temperature rise or equivalently the energy stored in the wire and produces a trip signal when the maximum temperature rise of the wire, simulated by a reference voltage is reached. The circuit reads the current in the wire in the form of a voltage signal across a shunt resistor serially connected to the wire. The signal is scaled and converted to a current by an amplifier stage, then squared, with the resultant applied to an RC integrator. The output voltage from the RC integrator is monitored by a comparator which has a threshold set by the referenced voltage according to the energy equation. The comparator provides a signal to trip the controller when the output voltage of the RC integrator reaches the threshold level. Through this trip signal, the current flow within the wire is interrupted by turning off the MOSFETS.
[0008] While this approach is effective, the output of the RC integrator follows an accurate I2RC trip characteristic only for constant DC input signals. In case of pulsed DC inputs such as the ones that are employed in most Radar applications, the RC integrator fails to provide an accurate I2RC trip characteristic.
[0009] Another approach of getting an I2T trip characteristic using an analog circuit is discussed in the Patent US 2017/0117698 A1, which discusses a protection circuit for providing a close approximation of I2T trip characteristic by integrating the conductor current with respect to time without squaring the current value. The protection circuit is configured to provide a dynamic trip threshold which varies with change in load current (i.e., the protection circuit is configured to lower the trip threshold as the input current increases beyond a particular offset voltage). This trip threshold may be generally a low voltage value, which makes the protection circuit susceptible to noise. The noise can interfere with the functionality of the circuit and bring down the accuracy of the I2T trip characteristic produced by the circuit.
[0010] Another electronic circuit protection method using I2T function is shown in the patent US 7,619,865 B2. It discusses a circuit protective device that makes use of the piece-wise linear approximation for generating a limit-signal that represents the quantity I2T. The limit-signal is compared with the load current and the time delay for overcurrent shut-down is determined according to the amount by which the load current exceeds the limit-signal. For low voltages, this method may not produce an accurate I2T trip characteristic. Since the piece-wise linear approximation is not carried out throughout the entire range, the obtained approximation may not produce an accurate limit-signal value, and thereby not an accurate trip characteristic.
[0011] Therefore, there is a need in the art for a protection system that provides an accurate I2T trip characteristic for both constant and pulsed DC input signals and overcome the drawbacks of traditional protection mechanisms and the drawbacks of other protection circuits mentioned above.

OBJECTS OF THE PRESENT DISCLOSURE
[0012] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[0013] It is an object of the present disclosure to provide a protection system for electric circuits that provides an accurate I2T trip characteristic.
[0014] It is an object of the present disclosure to provide a protection system for electric circuits that provides an accurate I2T trip characteristicfor both constant and pulsed DC input signals.
[0015] It is an object of the present disclosure to provide a protection system for radar or other similar applications to quickly isolate the high fault current according to an I2T function.
[0016] It is an object of the present disclosure to provide a protection system for electric circuits having a low power, reliable, and low part count.
[0017] It is an object of the present disclosure to provide a protection system for electric circuits that provides an accurate I2T trip characteristic to provided delayed as well as instantaneous tripping of the electric circuits based on level of fault current.
SUMMARY
[0018] The present disclosure relates to the field of electrical circuit protection system. More particularly, the present disclosure relates to electronic protection system that behaves as a conventional electrical fuse or a circuit breaker to protect electrical circuits of radar or other similar applications to quickly isolate the high fault current according to an I2T function.
[0019] An aspect of the present disclosure pertains to a system for protection of an electric circuit from high fault current, the system may comprising: a sensing unit operatively coupled to the electric circuit to be protected, the sensing unit may be configured to monitor current flowing through the electric circuit, and correspondingly generate a first set of signals;a multiplier operatively coupled to the sensing unit, and may be configured to generate a second set of signals based on the first set of signals received from the sensing unit, wherein the second set of signals may correspond to square of the monitored current;an averaging unit operatively coupled to the multiplier, and may be configured to generate a third set of signals based on the second set of signals received from the multiplier, wherein the third set of signals may correspond to square of a root mean square (RMS) value of the monitored current; an integrator unit operatively coupled to the averaging unit, and may be configured to generate a fourth set of signals based on the third set of signals received from the averaging unit, wherein the fourth set of signals may correspond to thermal energy dissipated by the electric circuit due to the monitored current; anda first comparator operatively coupled to the integrator unit, and may be configured to generate a first set of trip signals when the thermal energy corresponding to the fourth set of signals exceed a first threshold value, wherein the first comparator may be configured to transmit the first set of trip signals to a switching unit of the electric circuit to restrict flow of current through the electric circuit after a predefined interval of time.
[0020] In an aspect, the system may comprise a second comparator operatively coupled to the sensing unit, and may be configured generate a second set of trip signals when the monitored current corresponding to the first set of signals exceeds a second threshold value.
[0021] In an aspect, the second comparator may be configured to transmit the second set of trip signals to the switching unit of the electric circuit to instantaneously restrict flow of current through the electric circuit.
[0022] In an aspect, the first comparator and the second comparator may be operatively coupled to the trip unit through an OR circuit.
[0023] In an aspect, the system may comprise a thermal memory unit configured between the OR circuit and the switching unit, wherein the thermal memory unit may beconfigured to determine a second time interval required to be elapsed before resetting the switching unit.
[0024] In an aspect, the predefined interval of time may correspond to a trip time of the first comparator, and wherein the trip time may be inversely proportional to the square of the RMS value of the monitored current.
[0025] In an aspect, the averaging unit may comprise a low-pass RC filter.
[0026] In an aspect, the switching unit may comprise any or a combination of power electronics switch, circuit breaker, and solid-state power controller.
[0027] In an aspect, the first threshold value of the first comparator may be 140% of a nominal value of current of the electric circuit, and wherein the second threshold value of the second comparator may be 1000% of the nominal value of current of the electric circuit.
[0028] In an aspect, the system may be configured to operate for any or a combination of a static load current condition and a dynamic load current condition.

BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0030] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[0031] FIG. 1 illustrate exemplary block diagram of the proposed protection system being configured with an electric circuit to be protected, in accordance with an exemplary embodiment of the present disclosure.
[0032] FIG. 2 illustrate block diagram of the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0033] FIG. 3 illustrate equivalent circuit diagram of the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0034] FIG. 4 illustrate an exemplary multiplier of the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0035] FIG. 5 illustrate an exemplary I2t characteristic provided by the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION
[0036] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0037] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0038] In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0039] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0040] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0041] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
[0042] The present disclosure relates to the field of electrical circuit protection system. More particularly, the present disclosure relates to electronic protection system that behaves as a conventional electrical fuse or a circuit breaker to protect electrical circuits of radar or other similar applications to quickly isolate the high fault current according to an I2T function.
[0043] According to an aspect, the present disclosure elaborates upona system for protection of an electric circuit from high fault current, the system including: a sensing unit operatively coupled to the electric circuit to be protected, the sensing unit can be configured to monitor current flowing through the electric circuit, and correspondingly generate a first set of signals;a multiplier operatively coupled to the sensing unit, and can be configured to generate a second set of signals based on the first set of signals received from the sensing unit, wherein the second set of signals can correspond to square of the monitored current;an averaging unit operatively coupled to the multiplier, and can be configured to generate a third set of signals based on the second set of signals received from the multiplier, wherein the third set of signals can correspond to square of a root mean square (RMS) value of the monitored current; an integrator unit operatively coupled to the averaging unit, and can be configured to generate a fourth set of signals based on the third set of signals received from the averaging unit, wherein the fourth set of signals can correspond to thermal energy dissipated by the electric circuit due to the monitored current; anda first comparator operatively coupled to the integrator unit, and can be configured to generate a first set of trip signals when the thermal energy corresponding to the fourth set of signals exceed a first threshold value, wherein the first comparator can be configured to transmit the first set of trip signals to a switching unit of the electric circuit to restrict flow of current through the electric circuit after a predefined interval of time.
[0044] In an embodiment, the system can include a second comparator operatively coupled to the sensing unit, and can be configured generate a second set of trip signals when the monitored current corresponding to the first set of signals exceeds a second threshold value.
[0045] In an embodiment, the second comparator can be configured to transmit the second set of trip signals to the switching unit of the electric circuit to instantaneously restrict flow of current through the electric circuit.
[0046] In an embodiment, the first comparator and the second comparator can be operatively coupled to the trip unit through an OR circuit.
[0047] In an embodiment, the system can include a thermal memory unit configured between the OR circuit and the switching unit, wherein the thermal memory unit can be configured to determine a second time interval required to be elapsed before resetting the switching unit.
[0048] In an embodiment, the predefined interval of time can correspond to a trip time of the first comparator, and wherein the trip time can be inversely proportional to the square of the RMS value of the monitored current.
[0049] In an embodiment, the averaging unit can include a low-pass RC filter.
[0050] In an embodiment, the switching unit can include any or a combination of power electronics switch, circuit breaker, and solid-state power controller.
[0051] In an embodiment, the first threshold value of the first comparator can be 140% of a nominal value of current of the electric circuit, and wherein the second threshold value of the second comparator can be 1000% of the nominal value of current of the electric circuit.
[0052] In an embodiment, the system can be configured to operate for any or a combination of a static load current condition and a dynamic load current condition.
[0053] FIG. 1 illustrate exemplary block diagram of the proposed protection system being configured with an electric circuit to be protected, in accordance with an exemplary embodiment of the present disclosure.
[0054] As illustrated, in an aspect, the proposed protection system can be implemented in an electric circuit that includes a load 104 to which electrical power is delivered. A power source 101 can provide electric power to the load 104 through a conductor 103. A switching device 102 (also referred to as switch 102, herein) like MOSFET, but not limited to the likes can be used to switch power to the load. Referring to FIG. 1, the protection system 105 can monitor a current I passing from the power source 101 through the conductor 103 to the load 104, and can control the position of the switch 102 based on the monitored current. The protection system 105 can keep the switch 102 in the closed state when the current I is at the nominal rated current level or at a level that does not exceed the thermal limits of the conductor. The switch 102 can be deactivated or kept in an open state by the protection system 105 when the thermal limit of the conductor 103 is reached or exceeded.
[0055] In an exemplary implementation, the proposed protection system 105 can provide instantaneous tripping of the switch 102 in response to high fault currents such as the ones about 1000% of the nominal rating or more. In another exemplary implementation, for load currents above 140% up to 1000% of the rating, the protection system can provide delayed tripping, isolating the fault in a timely manner by preventing an overcurrent condition that exceeds the thermal capacity of the conductor 103.
[0056] FIG. 2 illustrate block diagram of the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0057] FIG. 3 illustrate equivalent circuit diagram of the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0058] As illustrated in FIG. 2 and 3, in an aspect, the proposed system can include a sensing unit operatively coupled to the electric circuit to be protected. The sensing unit can be configured to monitor current I flowing through the electric circuit 104, and can correspondingly generate a first set of signals. The system 105 can further include a multiplier 106 operatively coupled to the sensing unit, and which can be configured to generate a second set of signals based on the first set of signals received from the sensing unit, where the second set of signals can correspond to square of the monitored current I.In an illustrative embodiment, the multiplier 106 squares an input voltage Vcurr that is proportional to the monitored current I and produces a voltage signal (second set of signals) that is proportional to the square of the input current I (i.e., I2).
[0059] In an embodiment, the system 105 can include an averaging unit 107 (also referred to as averaging circuit 107, herein) operatively coupled to the multiplier 106, and which can be configured to generate a third set of signals based on the second set of signals received from the multiplier, where the third set of signals can correspond to square of a root mean square (RMS) value of the monitored current I.
[0060] In an exemplary embodiment, the Averaging circuit 107 can be configured as a low-pass RC filter, which can include a resistor R1 and a capacitor C1. The Averaging circuit 107 can receive the second set of signals from an output of the multiplier 106 at its input (i.e., at the first terminal of the resistor R1) and can average the second set of signals to generate its RMS value (i.e., voltage corresponding to I2RMS) at its output (i.e., at the second terminal of the resistor R1).
[0061] In an embodiment, the system 105 can include an integrator unit 108 operatively coupled to the averaging unit 107, and which can be configured to generate a fourth set of signals based on the third set of signals received from the averaging unit 107, where the fourth set of signals can correspond to (I2T ) thermal energy dissipated in the conductor 103 or the electric circuit 104, based on the monitored current I. In an exemplary embodiment, the integrator unit108 can be an operational amplifier (OpAmp).The output of the Averaging circuit 107 can be coupled to the input of the OpAmp integrator 108.
[0062] In an exemplary embodiment, the OpAmp integrator 108 can include an operational amplifier in inverting configuration. The resistor R2 and capacitor C2 can be connected across the OpAmp. The output of the Averaging circuit 107 can be coupled to the first terminal of the resistor R2. The second terminal of the resistor R2 can be connected to the inverting input of the OpAmp. The capacitor C2 and resistor R3 can be connected in the feedback position between the integrator 108 output and the inverting input. The OpAmp integrator 108 can integrate the input voltage (i.e., voltage corresponding to I2RMS) signal over time T to produce a voltage output corresponding to the energy accumulated due to the given load current I.
[0063] In an embodiment, the system 105 can include a first comparator 109 operatively coupled to the integrator unit 108, and which can be configured to generate a first set of trip signals when the thermal energy corresponding to the fourth set of signals exceed a first threshold value. The first comparator 109 can be configured to transmit the first set of trip signals to a switching unit 102 of the electric circuit to restrict flow of current through the conductor 103 after a predefined interval of time.
[0064] In an exemplary embodiment, the first comparator 109 can include an amplifier having the first input (i.e., the non-inverting input) coupled to the output of the OpAmp integrator 108. The second input (i.e., the inverting input) can receive the trip threshold voltage Vref1. The output of the OpAmp integrator 108 can be compared with the trip threshold voltage Vref1 and the comparator output can change its state when the output of the OpAmp integrator 108 exceeds the trip threshold voltage Vref1, causing the protection circuit to isolate the fault.
[0065] In an illustrative embodiment, the Averaging circuit 107 can average the signal received from the multiplier 106 to generate the voltage output (third set of signals) corresponding to the square of the RMS value of the current (i.e., I2RMS). The OpAmp Integrator 108 integrates the voltage output of the Averaging circuit 107 over time T to generate a voltage output (fourth set of signals) corresponding to the I2RMST energy dissipated by the conductor 103 due to the input current I. The first comparator 109 compares the output of the OpAmp integrator 108 with a fixed trip threshold voltage Vref1, and generates a trip signal when the comparative relationship between the output of the OpAmp integrator 108 and the trip threshold has changed.
[0066] During normal operation, the output of the OpAmp integrator 108 can be lesser than the trip threshold voltage Vref1, which is set according to the energy equation of the switch 102 or conductor 103 or load 104. As the input voltage Vcurr(i.e., the conductor current I) increases, the integrator output approaches the trip threshold voltage Vref1. The first comparator 109 output changes its state when the output of the OpAmp integrator 108 exceeds the trip threshold voltage Vref1. This time is referred to as the trip time. The trip time of the protection circuit is inversely proportional to square of the conductor current I.Thus, the protection system105 monitors the voltage corresponding to the energy accumulated due to the input current I and compares it to the trip threshold to determine when the accumulated energy reaches the maximum thermal capacity of the conductor, thereby achieving an I2T trip characteristic.
[0067] In an embodiment, the system 105 can include a second comparator 110 operatively coupled to the sensing unit, and which can be configured generate a second set of trip signals when the monitored current I of the conductor 103, corresponding to the first set of signals exceeds a second threshold value. The second comparator 110 can be configured to transmit the second set of trip signals to the switching unit 102 of the electric circuit to instantaneously restrict flow of current through the conductor 103.
[0068] In an embodiment, the first comparator 109 and the second comparator 110 can be operatively coupled to the switching unit 102 through an OR circuit 111, which outputs the trip signal when either of the comparator outputs have changed.
[0069] In an embodiment, the system can include a thermal memory unit 112 configured between the OR circuit 11 and the switching unit 102. The thermal memory unit 112 can be configured to determine a second time interval required to be elapsed before resetting the switching unit 102. The comparator output will charge the circuit 112, and the RC time constant can decide minimum time required to elapse before resetting the switch 102.
[0070] FIG. 4 illustrate an exemplary multiplier of the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0071] In an embodiment, as illustrated in FIG. 4, the multiplier 106 can be AD633AR. The voltage W at the output pin (pin no. 4) of the multiplier 106 is given by

[0072] The input voltage Vcurr (corresponding to the monitored current I) can be coupled to the input pin no. 7 (corresponding to voltage signal X1) and pin no. 2 (corresponding to voltage signal Y2) of the multiplier 106. The input pins 8 and 1 (corresponding to voltage signals X2 and Y1 respectively) are connected to the ground, which results in an output equation as follows:

[0073] The Pin no. 4 of the multiplier 106 can receive an external DC offset voltage Z. The value of the DC offset Z is chosen in such a way that the output W of the multiplier 106 can be a negative voltage value only for input currents higher than 140% of the nominal current rating.
[0074] The negative voltage output W at the output of the multiplier 106 can be further inverted by the OpAmp integrator 108. This produces a positive voltage value at the first input of the first comparator 109, whose other input is a fixed positive trip threshold voltage Z. This can enable the first comparator 109 to generate a trip signal whenever the output of the OpAmp integrator 108 becomes equal to or greater than the threshold voltage Z. For all load currents lesser than 140% of the nominal rated current, the output W of the multiplier 106 can be a positive voltage value, the diode parallel to the integrator capacitor prevents saturation of integrator to negative voltage, resulting in a negative voltage signal equal to diode potential input of the first comparator 109. This can causethe first comparator 109 to not generate the trip signal for any load current lesser than 140% of the nominal rated current. This feature can enable the protection circuit to avoid generation of unnecessary trip signals for lower load currents after a long period of time.
[0075] The multiplier 106 can produce at its output, a second set of signals corresponding to the square of the voltage signal at its input (i.e., voltage corresponding to I2). The output of the multiplier 106 can be coupled to an input of the Averaging circuit 107.
[0076] FIG. 5 illustrate an exemplary I2t characteristic provided by the proposed protection system, in accordance with an exemplary embodiment of the present disclosure.
[0077] As illustrated in FIG. 5, an exemplary I2t characteristic (graph) provided by the proposed protection system.The flat region of the graph can be referred to as the Instant trip region. In an implementation, for a load current as high as 1000% of the nominal current rating, the protection system 105 can generate a trip signal within about 500 us.
[0078] For load currents above 140% up to 1000% of the rating, the protection system 105 can provide delayed tripping, isolating the fault in a timely manner according to the energy equation of the MOSFET (switch 102) or according to the energy requirement of the load. This region can be referred to as the Always trip region.
[0079] For load currents that are equal to or less than 140% of the nominal current rating, the protection system 105 does not generate any trip signal. This region may be referred to as Never trip region.
[0080] In an embodiment, the protection system 105, according to the present invention can utilize an analog circuit to provide a close approximation of the I2T trip characteristic. The protection system 105 can also provide programmability with change in the load system through programmable trip thresholds Vref1 and Vref2, to suit the given current rating I. In addition to this, the feature of thermal memory is achieved through the integrator capacitor C2, R1, R2. The discharge pattern of the capacitor C2 enables the protection circuit to generate trip signal quickly in case of high current situations immediately after the reset of a previous trip.
[0081] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGS OF THE INVENTION
[0082] The proposed invention providesa protection systemfor electric circuits that provides an accurate I2T trip characteristic.
[0083] The proposed invention provides a protection system for electric circuits that provides an accurate I2T trip characteristicfor both constantand pulsed DC input signals.
[0084] The proposed invention provides a protection system for electric circuits having a low power, reliable, and low part count.
[0085] The proposed invention providesa protection system for electric circuits that provides an accurate I2T trip characteristic to provided delayed as well as instantaneous tripping of the electric circuits based on level of fault current.
[0086] The proposed invention provides a protection system for radar or other similar applications to quickly isolate the high fault current according to an I2T function.