Claims:1. A phase-lock control system for synchronization grid frequency, said phase lock control system comprising:
at least one field-programmable gate array (FPGA) unit comprises:
at least one sensing unit to measure grid voltage signals, wherein said grid voltage signals is single phase or three phase;
at least one transformation module to perform transformation of said grid voltage signals into two phase stationary reference frame components (Vα, Vβ);
wherein, said FPGA unit configured to perform transformation of said stationary reference frame components (Vα, Vβ) into synchronous reference frame components (Vd, Vq), wherein one of the said synchronous reference frame components maintained to its reference value (0) while other said synchronous reference frame components is subjected to at least one tunable proportional integral (PI) controller unit
said proportional integral (PI) controller unit configured to receive at least one input error signal corresponding to applied said synchronous reference frame component, and thereby generate at least one PI controller output corresponding to angular frequency (∆w), wherein said PI controller output adjusted to perform frequency correction and locking of grid frequency.
2. The phase-lock control system as claimed in claim 1, wherein said sensing unit is an analog to digital convertor (ADC) unit.

3. The phase-lock control system as claimed in claim 2, further comprises at least one voltage sensor unit to sense analog voltage signals from three phase or single phase grid, wherein said analog voltage signal fed to said ADC unit for subsequent processing.

4. The phase-lock control system as claimed in claim 1, wherein said FPGA performs transformation of said stationary reference frame components (α, β) into synchronous reference voltage frame components (d, q) using park transformation module.

5. The phase-lock control system as claimed in claim 1, wherein said angular frequency (∆w) fed to an integrator unit to obtain grid voltage phase angle.

6. The phase-lock control system as claimed in claim 5, wherein said grid voltage phase angle is applied to synchronous reference frame components (Vd, Vq) in FPGA, and thereby PI controller output tuned to adjust said grid voltage phase angle.

7. The phase-lock control system as claimed in claim 6, wherein tuning of said PI controller output maintains one of synchronous reference frame component (Vq) to zero and other synchronous reference voltage frame component (Vd) to unity, to enable frequency correction and locking of grid frequency.

8. A PLL method for synchronization grid frequency using FPGA, comprising:
receiving, by at least one analog to digital converter means in said FPGA, grid voltage analog signals, wherein said grid voltage analog signals is three phase or single phase;
transforming, by at least one transformation module in said FPGA, said grid voltage analog signals into two phase stationary reference frame components (Vα, Vβ), and thereby performing transformation of said of said stationary reference frame components (Vα, Vβ) into synchronous reference frame components (Vd, Vq), wherein one of the said synchronous reference frame components maintained to its reference value (0) while other said synchronous reference frame components is subjected to at least one tunable proportional integral (PI) controller unit;
receiving, by said PI controller unit, at least one input error signal corresponding to applied said synchronous reference frame component and thereby generating at least one PI controller output corresponding to angular frequency (∆w), wherein said PI controller output adjusted to perform frequency correction and locking of grid frequency.
, Description:TECHNICAL FIELD

[001] The present subject matter described herein, in general, relates to belongs to the system for measuring frequency and more particularly relates to a technique for accurately measuring the frequency of input signals that may vary over a wide dynamic range based on FPGA phase-lock control.

BACKGROUND

[002] A distributed power generation systems, which are small-scale generation units connected closer to the load on the grid. The distributed power generation units include a range of alternative energies, such as wind turbines, photovoltaic cells, fuel cells, and micro turbines and the like. The presence of an increasing number of distributed power generation systems units in the grid has caused the grid connection standards to become more stringent in order to prevent grid instability from occurring. Therefore, synchronization of the grip is required in the power generation systems.

[003] Typically, techniques of grid synchronization is implemented for detecting the phase angle of the grid voltage vector. The detected phase angle can then be used to synchronize the control variables of the system. However, in order to have a robust grid synchronization technique, a fast and accurate detection of the phase angle is necessary.

[004] Conventionally, techniques such as zero cross detection (ZCD) techniques are used for frequency tracking or locking of input grid frequency. In ZCD technique, through analog circuitry zero crossing edges of the input signal are detected and thus the frequency is measured. However, this technique is prone to grid distortion and noise as it only sense edges of the signal. Moreover, since the zero-crossing points can only be detected at each half cycle, the performance of the zero-crossing technique is considerably slow and vulnerable to distortions in the grid voltage.

[005] Another, technique used for frequency tracking or locking of input grid frequency is a filtering method, in which the phase angle of the grid voltage vector is obtained by filtering the grid voltages in the d,q or αβ reference frames. However, in filtering technique the filter delay adds to the measurement and hence correct frequency is not measured.

[006] Yet another technique is a phase-locked loop (PLL) system. A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The PLL system is are probably the most widely used synchronization technique in grid connected applications. A PLL is a nonlinear feedback control system that tracks the phase and frequency of the input signal fundamental component and is able to re track the phase, with no steady-state error, following a transient event such as phase and frequency jumps.

[007] Reference is made to US 3742353A, discloses a frequency measuring apparatus including phase locked loop. However, the apparatus disclosed in US ‘353 A comprises an analog frequency measurement technique wherein phase delay is possible and low dynamic response.

[008] Reference is made to US 7839178B2, provides an apparatus and method for detecting a phase difference between an input signal and a reference signal in an all-digital phase locked loop (PLL). However, it discloses a digital PLL wherein accurate measurement in case of distortion is not possible.

[009] Reference is made to CN 104022502 A, wherein power grid phase locking method for an energy converting system is disclosed. The power grid phase locking method is characterized in that a DSP control unit obtains the voltage-current information of the energy converting system by AD sampling, by Clark converting, input signals under an alpha-beta coordinate system are obtained, then by d-q converting, d-q shaft components are obtained, a d-shaft direction is the same as a three-phase voltage vector direction, q shaft output is subjected to PI adjusting, frequency correction is carried out through PI adjusting output, and after phase locking, a d-shaft angle, namely a phase angle in the three-phase voltage vector direction is obtained

[0010] However, the above prior art document uses floating point DSP for the computation of the algorithm which is comparatively slower when it comes to solving mathematical equations ,arithmetic calculations. Therefore, such mechanism when used in applications such as grid connected inverters or motor control wherein complex algorithm are to be executed along with PLL algorithm, the mentioned DSP will be slow and data loss will be there and hence accuracy will be less and so the frequency locking will not be accurate due to accumulated errors over various cycles.

[0011] Reference is made to non-patent literature, GUO Xiao-Qiang et.al. Phase locked loop and synchronization methods for grid-interfaced converters: a review, (http://www.red.pe.org.pl/articles/2011/4/48.pdf), wherein comprehensive review of the phase locked loop and synchronization methods is discussed.

[0012] Reference is made to a non-patent literature, Angelina Tomova, et al., International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622, Vol. 3, Issue 1, January-February 2013, pp.726-728, wherein PLL for synchronization with the public grid phase and frequency of grid-connected single phase inverter is disclosed. The approach uses trigonometric transformations of the inverter output voltage and the grid voltage. The proposed mathematical model is then studied by means of computer simulation for different voltage amplitudes of the grid voltage as well as the inverter output voltage.

[0013] Reference is made to a non-patent literature, S. Eren et.al. Enhanced Frequency-Adaptive Phase-Locked Loop for Distributed Power Generation System Applications(http://www.ontariosea.org/storage/26/1838_distributed_power_generation_systems.pdf), which discloses enhanced three-phase locked loop which can be used to synchronize the phase angle. It consists of a multi-block adaptive notch filter (ANF) integrated into a conventional three-phase synchronous reference frame phase-locked loop (SRF-PLL). The addition of the ANF to the phase-locked loop allows it to remove the double frequency ripple which occurs in the conventional three-phase SRF-PLL as a result of grid voltage unbalance.

[0014] Reference is made to a non-patent literature, R.Godha et.al., Improved Grid Synchronization Algorithm for DG System using and UH PLL under Grid disturbances, American Journal of Engineering Research (AJER) e-ISSN : 2320-0847 p-ISSN : 2320-0936 Volume-03, Issue-12, pp-69-75, wherein Unbalanced Harmonic (UH) based phase locked loop (PLL) is disclosed to provide an estimation of the angular frequency and both the positive and negative sequences of the fundamental component of an unbalanced three-phase signal.

[0015] Reference is made to non-patent literature, V. Jaya Prakash et.al., A Novel Approach To Sogi Grid Synchronization System For Three-Phase Grid-Connected Power Converters Under Unstable Conditions, International Journal of Advanced Trends in Computer Science and Engineering, Vol.2 , No.6, Pages: 108-113 (2013), wherein s a new grid synchronization method for three-phase three-wire networks, namely dual second-order generalized integrator (SOGI) frequency-locked loop. The method is based on two adaptive, implemented by using a SOGI on the stationary αβ reference frame, and it is able to perform an excellent estimation of the instantaneous symmetrical components of the grid voltage under unbalanced and distorted grid conditions.

[0016] Reference is made to a non-patent literature, Sreelekshmi K. R, et. al., Design of higher order phase locked loop, International Research Journal of Engineering and Technology (IRJET), Volume: 02 Issue: 02 | May-2015, pg 1001-1004, which discloses a technique to improve the performance of phase-locked loop (PLL) under adverse grid condition. It incorporates a first-order low-pass filter (LPF) into its control loop. The firstorder LPF, however, has a limited ability to suppress grid disturbances. Normally the loop filter is designed to match the characteristics required by the application of the PLL. If the PLL is to acquire and track a signal the bandwidth of the loop filter will be greater than if it expects a fixed input frequency. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart.

[0017] Reference is made to a non-patent literature, Mohammad Jafari Far, Simulation for Synchronization of a Micro-Grid with Three-Phase Systems, international journal of scientific & technology research volume 4, issue 09, September 2015 ISSN 2277-8616, pg 335-340, which discloses technique for synchronization of a microgrid with the network when its voltage is synchronized with the voltage in the main grid. Phase lock loops are responsible to identify the voltage phase of the micro-gird and the main grid, and when these two voltages are in the same phase, they connect the micro-grid to the main grid. In this research, the connection of a micro-grid to the main grid in the two phases of synchronous and asynchronous voltage is simulated and investigated.

[0018] Reference is made to a non-patent literature, Timothy Thacker et. al., Phase-Locked Loops using State Variable Feedback for Single-Phase Converter Systems, (http://www.ee.bgu.ac.il/~pedesign/Graduate_problem_papers/papers2009/PLL.pdf), wherein feedback mechanisms using the estimated frequency and phase in single-phase PLLs (in the stationary and rotating reference frames) is disclosed which enhances performance. The estimated frequency ripple is eliminated without using low-pass filters (LPFs), and feedback terms are shown to improve the synchronization speed, by as much as 80% in some cases. Mathematical analyses, simulation, and hardware results are presented to verify the methods.

[0019] Reference is made to a non-patent literature, Anani et al. Synchronization of a renewable energy inverter with the Grid, J. Renewable Sustainable Energy 4, 043103 (2012), wherein a new all-digital phase-locked loop system for synchronizing a voltage source DC-AC single-phase inverter with the low voltage utility grid are presented. The system which is based on the time-delay digital tanlock loop was simulated using MATLAB/ SIMULINK and was tested by subjecting the grid voltage to various perturbations similar to those which can occur in a real power system, such as voltage sags and nonlinear distortion of the grid voltage waveform. Results indicate that even in the presence of such perturbations the system achieved and/or re-gained synchronization within 100 ms. The proposed system is all-digital and can be readily implemented using a field programmable gate array and easily embedded into a power inverter.

[0020] However, the above mentioned prior art documents mentioned above has the following drawbacks:
• In the above mentioned prior art literatures, there are various delays like fixed delay τ, variable delay, digital filter which will add delay and also error to the frequency measurement. Also during input side fluctuation or sags will not be able to correct the frequency measurement and hence the system synchronization can be disturbed, which will harm to other devices connected to the power system, or there can be over speed in case of motor control.
• Besides, in the prior art, there are low pass filters (eg. Fixed 90 degree delay) having fixed time delay and further mathematical computation on this, are used to provide fixed delay and based on this frequency is extracted. They can be unit delay filters.

[0021] Thus, there exists a dire need to address the hitherto problems of the prior art by providing an improved grid synchronization technique using Field field-programmable gate array (FPGA). FPGA is a device in which parallel processing of mathematical and logical functions occurs and hence is faster and better latency time compared to digital signal processor.
SUMMARY OF THE INVENTION

[0022] The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the present invention. It is not intended to identify the key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concept of the invention in a simplified form as a prelude to a more detailed description of the invention presented later.

[0023] An object of the present invention is to provide PLL system for frequency measurement/locking, harmonic measurement and compensation such as to lock the input frequency and measures the input frequency accurately as compared to other techniques like ZCD and filtering.

[0024] Another object of the present invention is to provide an accurate, fast responding PLL system implemented using FPGA to measure phase angle and frequency of the grid voltage for control and protection purposes.

[0025] Yet object of the present invention is to provide an improved grid synchronization technique that is able to detect the phase angle and frequency despite the presence of distorted and noisy environment, and frequency variations in the phase-locked loop input signal

[0026] Accordingly to one aspect, the present invention provides a phase-lock loop (PLL) control system for grid synchronization, said phase lock control system comprising: at least one field-programmable gate array (FPGA) unit comprises: at least one sensing unit to measure grid voltage signals, wherein said grid voltage signals is three phase or single phase; at least one transformation module to perform transformation of said grid voltage signals into two phase stationary reference frame components (Vα, Vβ); wherein, said FPGA unit configured to perform transformation of said stationary reference frame components (Vα, Vβ) into synchronous reference frame components (Vd, Vq), wherein one of the said synchronous reference frame components maintained to its reference value (0) while other said synchronous reference frame components is subjected to at least one tunable proportional integral (PI) controller unit; said proportional integral (PI) controller unit configured to receive at least one input error signal corresponding to applied said synchronous reference frame component, and thereby generate at least one PI controller output corresponding to angular frequency (∆w), wherein said PI controller output adjusted to perform frequency correction and locking of grid frequency.

[0027] In another aspect of the present invention, there is provided a PLL method for synchronization grid frequency using FPGA, the method comprising:
• receiving, by using at least one analog to digital converter means in an FPGA, grid voltage analog signals, wherein said grid voltage analog signals is three phase or single phase;
• transforming, by using at least one transformation module in said FPGA, said grid voltage analog signals into two phase stationary reference frame components (Vα, Vβ), and thereby performing transformation of said of said stationary reference frame components (Vα, Vβ) into synchronous reference frame components (Vd, Vq), wherein one of the said synchronous reference frame components maintained to its reference value (0) while other said synchronous reference frame components is subjected to at least one tunable proportional integral (PI) controller unit;
• receiving, by said PI controller unit, at least one input error signal corresponding to applied said synchronous reference frame component and thereby generating at least one PI controller output corresponding to angular frequency (∆w), wherein said PI controller output adjusted to perform frequency correction and locking of grid frequency.

[0028] Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

[0029] The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

[0030] Figure 1 illustrates a block diagram representation phase control lock loop system for three phase grid synchronization implemented in FPGA, according to one implementation of the present invention.

[0031] Figure 2 illustrates transformation of abc to alpha beta component, according to one implementation of the present invention.

[0032] Figure 3 illustrates FPGA simulation result for the phase control lock loop system, according to one implementation of the present invention.

[0033] Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0034] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary.

[0035] Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0036] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
[0037] It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.

[0038] By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

[0039] Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.

[0040] It should be emphasized that the term “comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0041] It is also to be understood that the term “module” is used in the specification to indicate set of instructions stored and executed by the FPGA. The term “means” when used in the specification is taken to specify the mode by which desired result is achieved.

[0042] The present invention provides an improved PLL system implemented using FPGA for synchronization of grid frequency both in three phase and/or single phase application. Here apart from FPGA other hardware component includes accurate voltage sensor and accurate execution of modules in FPGA with proper tuning of PI controller in accordance to lock the output with the grid input frequency.

[0043] Reference is made to figure 1, wherein the block diagram for three phase grid synchronization technique is illustrated. In this invention, the three phase to two phase transformation is performed. The three/single phase input can be sensed through ADC and converted from three phase to two phase and one of the resultant component can be tracked and maintained to its reference value ( 0 or maximum) in order to lock the frequency to the input frequency.

[0044] In another implementation, the present invention can be extended to a single phase application also. The single phase input will serve as one of the component i.e. real component alpha, the beta component has to be derived as the imaginary component which will be 90 degrees phase apart from the available signal. In case of single phase system abc to alpha beta conversion is not required and the second block alpha, beta to d,q conversion has to be directly used and the 90 degree signal can be created within FPGA as an imaginary signal.

[0045] In one implementation, the main components of the PLL system are voltage sensor, which measures the accurate analog voltage and this analog voltage is thereby sensed by the ADC of the FPGA and the transformation and the module executed inside FPGA controller changes the PLL system behavior and the frequency measurement is more accurate and can function in distorted and noisy environment.

[0046] In one implementation, the phase-lock control system further comprises a voltage sensor unit to sense analog voltage signals from three phase or single phase grid, wherein said analog voltage signal fed to said ADC unit for subsequent processing.

[0047] In one implementation, the FPGA comprises one or more modules which when executed performs transformation of stationary reference frame components under (α, β) coordinate system into synchronous reference voltage frame components (d, q). One of the transformation module stored and executed by FPGA is park transformation module.

[0048] In one implementation, the filtering is done through a proportional integral (PI) controller unit and hence the dynamics of the system is determined by PI controller response which can be tuned. The PI controller output corresponds to angular frequency (∆w) which is thereby fed to an integrator module to obtain grid voltage phase angle. The grid voltage phase angle is applied to synchronous reference voltage frame components (Vd, Vq) in FPGA, and thereby PI controller output tuned to adjust said grid voltage phase angle.

[0049] In one implementation, tuning of said PI controller output maintains one of synchronous reference voltage frame component (Vq) as zero and other synchronous reference voltage frame component (Vd) as unity, to enable frequency correction and locking of grid frequency.

[0050] In one implementation, three phase grid voltages are measured by configuring FPGA according to the following equations:
Va = Vg (1)
Vb = Vg.cos(Ø - 2π/3) (2)
Vc = Vg. cos(Ø + 2π/3) (3)

Measured voltages are transformed to two phase stationary reference frame
Vα = 2/3[Va – (Vb-Vc)/2] (4)
Vβ = 1/ √3(Vb-Vc) (5)

Two phase stationary reference frame components are transformed to synchronous reference frame d, q components d, q using park transformation:
Vd = Vα.cos Ø’ + Vβ.sin Ø’ (6)
Vq = - Vα.sin Ø’ + Vβ.cos Ø’ (7)
Now, Vα is aligned to Va hence Vα = Vg.cosØ and Vβ= Vg. sinØ,
Considering above statement the Vd and Vq becomes as,
Vd = Vg.cos(Ø - Ø’) (8)
Vq = Vg.sin(Ø - Ø’) (9)

The Vq component derived if maintained to zero, and compared with actual Vq obtained, then the PI controller will be having the input error as,
e= 0 – Vq = 0 - Vg.sin (Ø - Ø’) (10)

This implies, Ø’ = Ø, and this would lead to steady state equalization of the estimated and actual phase angle of the input voltage phase angle.

Thus, the output of the PI controller, is
∆w = (Kp + ki/s).e(s) (11)

Wherein, Kp and Ki are coefficients for the proportional, integral components, and e(s) is the error signal

Integrating the angular frequency will give the estimate grid voltage phase angle as,
Ø’ = ʃ ∆w (12)
This the estimated phase angle is used to calculate the new Vd,Vq, until Vq becomes 0 and Vd becomes unity and thus locking the grid frequency.

[0051] In one implementation, as shown in figure 2, the three phase voltage Va,b,c are converted to (α, β) by rotating this frame with angle as 0 degree and hence by solving the vector diagram of three phase voltage, (α, β) components are obtained. The equation 4 and 5 are achieved which are implemented inside FPGA.

[0052] Reference is made to figure 3, which shows FPGA Simulation results for the proposed PLL( 1. Clock, 2. Reset, 3. Vbeta, 4. Va, 5. Vb, 6. Vc, 7. Vd, 8. Valpha, 9.Output (cos theta), 10. Vq). It shows that output of the PLL follows input i.e. if Va is compared with cos theta components, they are in phase and follows whenever input frequency changes. Also the Vq component is always maintained zero, which ensure phase locking and hence the PI controller is properly tuned.

[0053] Some of the advantages of the present invention, are as follows:

1. The present invention is implemented using FPGA which is a parallel processing device wherein execution of various process takes place in parallel and hence is immensely faster than DSP and hence latency and delay errors will not be there and accuracy will be far better than DSP.
2. The present invention can be implemented a single FPGA and there are no limitation on number of ports or PWM pins as compared to DSP, and hence the reliability of the system is better than one with DSP.
3. FPGA based frequency measurement in PLL system. Using FPGA for frequency tracking is an advantage when clubbing the PLL system to other complex systems.
4. The present invented PLL system can work even when input signal is distorted
5. Good dynamic response and no phase delay
6. Multiple harmonic measurement for applications such as active power filters. Multiple harmonic measurement is done through the PLL technique as illustrated in figure1, wherein if multiple PLL loops are executed for n no. of harmonics then, multiple harmonics can be detected.
7. FPGA use in the system for faster processing.
8. Fast response frequency measurement, or phase locked loop.
9. The PLL system of the present invention can detect various multiples of frequency i.e., harmonics individually due to high precision and accurate PLL loop.
10. No filtering delay exists.
11. The present invention is applicable in case of Grid synchronization and Grid Islanding cases wherein grid is required to isolate from inverter if inverter frequency drops below or goes above the specified limit that may include but not limited 49Hz to 51 Hz.
12. The dependency on Zero crossing technique is eliminated.

[0054] Although a system for synchronization of grid frequency and method thereof have been described in language specific to structural features and/or methods, it is to be understood that the embodiments disclosed in the above section are not necessarily limited to the specific features or methods or devices described. Rather, the specific features are disclosed as examples of implementations of the system for synchronization of grid frequency and method thereof.