DESC:FIELD
The present disclosure relates generally to the field of electronic security seals. More particularly, the present disclosure relates to a tamper indicating bolt-seal.
BACKGROUND
The background information herein below relates to the present disclosure but is not necessarily prior art.
Conventional (Near Field Communication) NFC, (Radio Frequency Identification) RFID, or dual frequency NFC+RFID security tags use the technology of inductive coupling, which is a process that transfers energy through a shared magnetic field between an RFID tag and an RFID reader. The RFID reader uses magnetic induction to create a radio-wave field that the RFID tag detects. Therefore, when a tag is placed in close proximity to the reader, the field from the reader's antenna coil couples with the tag's antenna coil and induces a voltage in the tag, which is then rectified and used to power the tag's internal circuitry.
Existing passive RFID security tags/seals are capable of checking and recording the status of the tamper loop only in presence of a radio frequency (RF) field of the RFID reader. Such chips derive their power from the RF field to send a pulse around the tamper loop. If the pulse is successfully sent and received, a tamper check flag is set as non-tampered and seal is declared non-tampered. In the absence of such an RF field, a skilled counterfeiter can open and close the tag/seal without changing the status of the tamper check flag. Hence, under such a condition, when the tamper check flag is read by an RFID reader, it will show non-tampered even though the seal/tag has been tampered with.
There is, therefore, felt a need for developing a tamper indicating seal that can count the number of tamper status changes of the tamper loop in real-time.
OBJECTS
Some of the objects of the present disclosure, which at least one embodiment herein satisfies, are as follows:
It is an object of the present disclosure to ameliorate one or more problems of the prior art or to at least provide a useful alternative;
An object of the present disclosure is to provide a tamper indicating seal.
Another object of the present disclosure is to provide a tamper indicating seal that can record number of times it is open and closed.
Yet another object of the present disclosure is to provide a tamper indicating seal that can identify tampering even if the seal is not damaged/broken.
Still another object of the present disclosure is to provide a tamper indicating seal that identifies tampering even if the seal is opened in the absence of a radio frequency (RF) field.
Other objects and advantages of the present disclosure will be more apparent from the following description, which is not intended to limit the scope of the present disclosure.
SUMMARY
The present disclosure envisages a tamper indicating seal. The tamper indicating seal comprises a tamper loop and a tamper detection chip. The tamper loop includes a first portion and a second portion. The tamper loop is configured to close when an electrical connection is established between the first portion and the second portion. The tamper detection chip is provided in the first portion. The tamper detection chip is configured to detect events corresponding to opening and closing of the tamper loop, and is further configured to facilitate detection of tampering of the seal based on the count of either the detected closing events or the detected opening and closing events.
In an embodiment, the tamper indicating seal is in the form of a bolt seal comprising a bolt member and a housing. The housing is configured to receive the bolt member, and is further configured to facilitate snap-locking of the bolt member therewithin. The first portion of the tamper loop is embedded within the bolt member and the second portion is embedded within the housing, wherein locking of the bolt member with the housing causes the tamper loop to close and unlocking of the bolt member from the housing causes the tamper loop to open.
In an embodiment, the tamper detection chip comprises a control unit, a memory, a tamper switch, a counter, and a comparator. The control unit is configured to detect events corresponding to opening and closing of the tamper loop, and is further configured to generate a closed event signal upon detecting closing of the tamper loop and an open event signal upon detecting opening of the tamper loop. The memory comprises an identification register, a tamper flag register, and a pre-determined threshold tamper value. The identification register stores a unique identification code associated with the tamper indicating seal. The tamper switch is configured to cooperate with the control unit to receive the closed event signal and the open event signal, and is further configured to toggle between an open state position and a closed state position based on the received closed event and open event signals. The counter is configured to store a tamper count value, and is further configured to cooperate with the tamper switch to increment the tamper count value by one based on detection of change in the position of the tamper switch. The default value of the tamper count value stored in the counter is zero. In an embodiment, the counter is a 3-bit memory and can count up to 7. In an embodiment, the counter is configured to increment tamper count value by one every time the tamper switch toggles between the open state and closed state positions. In another embodiment, the counter is configured to increment tamper count value by one every time the tamper switch toggles to the closed state position.
The comparator is configured to cooperate with the memory and the counter to receive the pre-determined threshold tamper value and the tamper count value respectively, and is further configured to change the status of the tamper flag register, when the tamper count value becomes equal to the pre-determined threshold tamper value, thereby indicating tampering of the seal.
In an alternate embodiment, the comparator is configured to change at least one status bit of the identification code stored in the memory, when the tamper count value becomes equal to the pre-determined threshold tamper value, thereby indicating tampering of the seal. In an embodiment, the control unit, the counter, and the comparator are implemented using one or more processor(s).
In an embodiment, the tamper loop includes at least one antenna, a battery, and a capacitor. The antenna is electrically connected to the tamper detection chip and is configured to cooperate with the memory to transmit the identification code, status of the tamper loop, the count value, and status of the tamper flag register upon receiving a radio frequency signal from a reader. The antenna is selected from a group consisting of a high frequency antenna, an ultrahigh frequency antenna, and a low frequency antenna. The identification code, status of the tamper loop, the count value, and status of the tamper flag register are transmitted to the reader using communication protocols selected from Radio Frequency Identification (RFID), Long Range Wide Area Network (LoRaWAN), Global Positioning System (GPS), and Wireless Fidelity (Wi-Fi). The battery is configured to supply power to the control unit to facilitate generation of the closed event and the open event signals. The capacitor is configured to supply power to the control unit to facilitate generation of the closed event and open event signals in absence of power supply from the battery.
In an embodiment, the tamper indicating seal is assumed to be tampered if the reader is unable to read the unique identification code correctly. In another embodiment, the identification code facilitates automatic identification of a container or a transport vehicle to which the seal is attached.
In an embodiment, the status of the tamper flag register facilitates determining whether the seal is tampered or not. Alternatively, the status bit of the identification code facilitates determining whether the seal is tampered or not.
Advantageously, the control unit is configured to generate the open event signal when the battery is removed without opening the tamper loop.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWING
A tamper indicating seal of the present disclosure will now be described with the help of the accompanying drawing, in which:
Figure 1 illustrates a sectional view of a tamper indicating seal of the present disclosure; and
Figure 2 illustrates a block diagram of a tamper detection chip of the tamper indicating seal of Figure 1.
LIST OF REFERENCE NUMERALS
100 – Tamper indicating seal
102 – Antenna
104 – Capacitor
106 – Tamper detection chip
108 – Battery
110 – Bolt member
112 – Terminals of tamper detection chip
114 – Terminals of tamper loop in housing
116 – Housing
118 – Control unit
120 – Tamper switch
122 – Memory
124 – Counter
126 – Comparator
302 – Shipping container/vehicle
304 – Reader
306 – Server
DETAILED DESCRIPTION
Embodiments, of the present disclosure, will now be described with reference to the accompanying drawing.
Embodiments are provided so as to thoroughly and fully convey the scope of the present disclosure to the person skilled in the art. Numerous details, are set forth, relating to specific components, and methods, to provide a complete understanding of embodiments of the present disclosure. It will be apparent to the person skilled in the art that the details provided in the embodiments should not be construed to limit the scope of the present disclosure. In some embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.
The terminology used, in the present disclosure, is only for the purpose of explaining a particular embodiment and such terminology shall not be considered to limit the scope of the present disclosure. As used in the present disclosure, the forms "a,” "an," and "the" may be intended to include the plural forms as well, unless the context clearly suggests otherwise. The terms "comprises," "comprising," “including,” and “having,” are open ended transitional phrases and therefore specify the presence of stated features, integers, steps, operations, elements, modules, units and/or components, but do not forbid the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The particular order of steps disclosed in the method and process of the present disclosure is not to be construed as necessarily requiring their performance as described or illustrated. It is also to be understood that additional or alternative steps may be employed.
When an element is referred to as being "mounted on," “engaged to,” "connected to," or "coupled to" another element, it may be directly on, engaged, connected or coupled to the other element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed elements.
Existing passive RFID security seals are capable of checking and recording the status of the tamper loop only in presence of a radio frequency (RF) field of the RFID reader. In the absence of RF field, a skilled counterfeiter can open and close the seal without changing the status of the tamper check flag. Under such a condition, when the tamper check flag is read by an RFID reader, it will show a non-tampered status even though the seal has been tampered with. To avoid this, a tamper indicating seal (hereinafter referred to as “seal 100”) of the present disclosure is now being described with reference to Figure 1 through Figure 3. The tamper indicating seal 100 records the number of tamper status changes to identify tampering.
Referring to Figure 1, the tamper indicating seal 100 comprises a tamper loop and a tamper detection chip 106. The tamper loop includes a first portion and a second portion. The tamper loop is configured to close when an electrical connection is established between the first portion and the second portion. The tamper detection chip 106 is provided in the first portion. The tamper detection chip 106 is configured to detect events corresponding to opening and closing of the tamper loop, and is further configured to facilitate detection of tampering of the seal 100 based on the count of either the detected closing events or the detected opening and closing events.
In an embodiment, the tamper indicating seal 100 is in the form of a bolt seal comprising a bolt member 110 and a housing 116. The housing 116 is configured to receive the bolt member 110, and is further configured to facilitate snap-locking of the bolt member 110 therewithin. The first portion of the tamper loop is embedded within the bolt member 110 and the second portion of the tamper loop is embedded within the housing 116 such that locking of the bolt member 110 with the housing 116 causes the tamper loop to close and unlocking of the bolt member 110 from the housing 116 causes the tamper loop to open. The tamper loop includes the tamper detection chip 106. The tamper detection chip 106 is configured to detect the number of times the tamper loop opens and closes to facilitate detection of tampering of the seal 100.
In an embodiment, the housing 116 includes a wire having two terminals 114. The terminals 114 of the wire are configured to connect with terminals 112 of the tamper detection chip 106 located in the bolt member 110 to form a continuous tamper loop when the seal 100 is in locked state.
Referring to Figure 2, the tamper detection chip 106 comprises a control unit 118, a memory 122, a tamper switch 120, a counter 124, and a comparator 126. The control unit 118 is configured to detect events corresponding to opening and closing of the tamper loop, and is further configured to generate a closed event signal upon detecting closing of the tamper loop and an open event signal upon detecting opening of the tamper loop. The memory 122 comprises an identification register, a tamper flag register, and a pre-determined threshold tamper value. The identification register stores a unique identification code associated with the tamper indicating seal 100. The tamper switch 120 is configured to cooperate with the control unit 118 to receive the closed event signal and the open event signal, and is further configured to toggle between an open state position and a closed state position based on the received closed event and open event signals. The counter 124 is configured to store a tamper count value, and is further configured to cooperate with the tamper switch 120 to increment the tamper count value by one based on detection of change in the position of the tamper switch 120. The default value of the tamper count value stored in the counter 124 is zero. In an embodiment, the counter 124 is a 3-bit memory and can only count up to 7. In an alternate embodiment, the counter 124 is a 4 or higher bit memory. The counter 124 does not reset to zero once the maximum count is reached. In an embodiment, the counter 124 is configured to increment tamper count value by one every time the tamper switch 120 toggles between the open state and closed state positions. In another embodiment, the counter 124 is configured to increment tamper count value by one every time the tamper switch 120 toggles to the closed state position. The comparator 126 is configured to cooperate with the memory 122 and the counter 124 to receive the pre-determined threshold tamper value and the tamper count value respectively, and is further configured to change the status of the tamper flag register, when the tamper count value becomes equal to the pre-determined threshold tamper value, thereby indicating a tampered seal. For example, the tamper flag register may be configured to store a single bit indicating whether or not the seal 100 is tampered. A bit value of ‘0’ may indicate a ‘non-tampered status and a bit value of ‘1’ may indicate a ‘tampered status’.
In an alternate embodiment, the comparator 126 is configured to change at least one status bit of the identification code stored in the memory 122, when the tamper count value becomes equal to the pre-determined threshold tamper value, thereby indicating a tampered seal.
In an embodiment, the control unit 118, the counter 124, and the comparator 126 are implemented using one or more processor(s). The processor may be a general-purpose processor, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), and/or the like. The processor may be configured to retrieve data from and/or write data to a memory. The memory can be for example, a random access memory (RAM), a memory buffer, a hard drive, a database, an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a read only memory (ROM), a flash memory, a hard disk, a floppy disk, cloud storage, and/or so forth.
The tamper loop further includes at least one antenna 102, a battery 108, and a capacitor 104. The antenna 102 is electrically connected to the tamper detection chip 106. The antenna 102 is configured to cooperate with the memory 122 to transmit the identification code, status of the tamper loop, the count value, and status of the tamper flag register upon receiving a radio frequency signal from a reader 304. The antenna 102 is selected from a group consisting of a high frequency antenna, an ultrahigh frequency antenna, and a low frequency antenna. In an embodiment, the antenna 102 is a dual frequency RFID/NFC antenna. The identification code, status of the tamper loop, the count value, and status of the tamper flag register can be transmitted to the reader 304 using communication protocols selected from Radio Frequency Identification (RFID), Long Range Wide Area Network (LoRaWAN), Global Positioning System (GPS), and Wireless Fidelity (Wi-Fi). The battery 108 is configured to supply power to the control unit 118 to facilitate generation of the closed event and the open event signals. The capacitor 104 is configured to supply power to the control unit 118 to facilitate generation of the closed event and open event signals in absence of power supply from the battery 108.
In an exemplary embodiment, when the tamper loop is closed, i.e. when the bolt member 110 is locked with the housing 116, the battery 108 drives a current through the tamper loop and supplies power to the control unit 118 of the tamper detection chip 106. Upon receiving the power, the control unit 118 detects the closed status of the tamper loop and generates a closed event signal. The control unit 118 transmits the generated closed event signal to a tamper switch 120. The tamper switch 120 changes state upon receiving the closed event signal. The change in state of the tamper switch 120 drives the counter 124 to increase the count value by one.
In another exemplary embodiment, when the tamper loop is opened, i.e. when the bolt member 110 is removed/unlocked from the housing 116, there will be no current in the tamper loop. However, the battery 108 is still connected to the control unit 118 and supplies power to the control unit 118. Upon receiving power from the battery 108, the control unit 118 detects opened status of the tamper loop (i.e. no current in the tamper loop) and generates an open event signal. The control unit 118 transmits the generated open event signal to the tamper switch 120. Upon receiving the open event signal, the tamper switch 120 goes back to its initial state. The change in state of the tamper switch 120 drives the counter 124 to increase the count value by one.
In an embodiment, the counter 124 increments tamper count value by one every time the tamper switch 120 toggles to the closed state position. In other words, the counter 124 increments tamper count value only during lock events i.e. when the tamper loop is closed and the bolt member 110 is locked with the housing 116, and ignores unlock events as it will be between two lock events and can be detected at the time of scan. This way the number of lock/unlock events that can be counted by the counter 124 is doubled using the same amount of counter memory. Referring to an embodiment of Figure 3, the reader 304 may be communicatively coupled to a server 306. Each reader 304 is associated with a unique account identifier (ID). The reader 304 is configured to transmit the identification code, the status of the tamper loop at the time of scan, the count value, and the unique account ID to the server 306 upon scanning of the tamper seal 100. In this configuration, the seal 100 can be used as a reusable seal with each event being stored on blockchain or the server 306. For example, a first user locks the seal 100. This increments the count value by 1. He then scans the seal 100 using a secure access account (account ID) to validate the transaction. At this stage, the identification code, the status of the tamper loop at the time of scan, the count value, and the unique account ID are transmitted to the server 306. At the reader end, the expected count value is 1. Upon receipt, the receiver scans the seal 100 and checks the count value. If the checked count value matches with the count value stored in the server 306, then the seal 100 is declared non-tampered. The scan records his account ID, the identification code, the status of the tamper loop, and the count value, on the server 306. For the next use, he simply locks the seal 100 again, thus increasing the count to 2. Upon receipt, if the next user sees an open tag status or if the count is 3, the seal 100 is declared tampered.
In an exemplary embodiment, referring to table 1 below, the default condition of the tamper loop is open and the count value of the counter 124 is set at 0. The manufacturer tests the seal 100 by closing the tamper loop. At this stage, the count value increases to 1. After successful testing, the loop is opened again and the count value increases to 2. The tamper seal 100 is supplied to an end user in this condition.
Only one locking attempt is allowed to the end user. Once locked, the tamper loop is again closed and the count value goes to 3. This is the only condition that should be returned to the reader 304 for the seal 100 to be declared as untampered.

Tamper loop status Location Event number Count value Interpretation
Open Factory 0 000 Factory default
Closed Factory 1 001 Factory QC test
Open Factory 2 010 Factory reset
Closed User 3 011 Locked by authorized end user (exporter)
Open Tamper 4 100 Tampered
Closed Tampered 5 101 Tampered
Open Tampered 6 110 Tampered
Closed Tampered 7 111 Tampered
Table 1
In case of any pre or post tampering attempt, it is not possible to bypass the counter 124. If the seal 100 is tampered by opening the tamper loop, the counter 124 immediately goes to 4. If the tamper loop is successfully reattached, the counter 124 increases to 5. When this condition is detected by the reader 304 at the customs, the seal 100 is declared as tampered.
In an embodiment, the identification code facilitates automatic identification of a container or a transport vehicle (302) to which the seal 100 is attached. The reader 304 is configured to read the unique identification code and cooperate with the server 306 to enable automatic identification of any container or transport vehicle (302), to which the seal 100 is attached. The seal 100 is assumed to be tampered if the reader 304 is unable to read the unique identification code correctly.
In an embodiment, the status of the tamper flag register facilitates determining whether the seal 100 is tampered or not. In another embodiment, the status bit of the identification code facilitates determining whether the seal 100 is tampered or not.
Advantageously, the control unit 118 is configured to generate the open event signal when the battery 108 is removed without opening the tamper loop, i.e. without unlocking the bolt member 110 from the housing 116. For example, if there is an attempt to remove the battery 108 without opening the tamper loop, i.e. without removing bolt member 110 from the housing 116, there will be a loss of power across the tamper loop, and subsequently a loss of power across the control unit 118. In this case, the capacitor 104 provides a sufficient power to the control unit 118 to facilitate generation of the open event signal. The tamper switch 120 changes its state upon receiving the open event signal, thereby incrementing the count value of the counter 124 and changing the status of the tamper flag register or the status bit of the identification code, the moment the battery 108 is disconnected.
The tamper indicating seal 100 facilitates identification of tampering even when the seal 100 is opened without damaging it or when the seal 100 is opened in the absence of a radio frequency (RF) field. Thus, tamper detection is ensured even if the seal 100 is tampered by a skilled counterfeiter.
The foregoing description of the embodiments has been provided for purposes of illustration and not intended to limit the scope of the present disclosure. Individual components of a particular embodiment are generally not limited to that particular embodiment, but, are interchangeable. Such variations are not to be regarded as a departure from the present disclosure, and all such modifications are considered to be within the scope of the present disclosure.
TECHNICAL ADVANCEMENTS
The present disclosure described herein above has several technical advantages including, but not limited to, the realization of a tamper indicating seal that:
• can count the number of times it is open and closed;
• identifies tampering even if the seal is not damaged/broken;
• identifies tampering even if the seal is opened in the absence of a radio frequency (RF) field;
• identifies if the seal has not been locked; and
• can be deployed as a reusable seal.

The embodiments herein and the various features and advantageous details thereof are explained with reference to the non-limiting embodiments in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
The foregoing description of the specific embodiments so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.
The use of the expression “at least” or “at least one” suggests the use of one or more elements or ingredients or quantities, as the use may be in the embodiment of the disclosure to achieve one or more of the desired objects or results.
The numerical values mentioned for the various physical parameters, dimensions or quantities are only approximations and it is envisaged that the values higher/lower than the numerical values assigned to the parameters, dimensions or quantities fall within the scope of the disclosure, unless there is a statement in the specification specific to the contrary.
While considerable emphasis has been placed herein on the components and component parts of the preferred embodiments, it will be appreciated that many embodiments can be made and that many changes can be made in the preferred embodiments without departing from the principles of the disclosure. These and other changes in the preferred embodiment as well as other embodiments of the disclosure will be apparent to those skilled in the art from the disclosure herein, whereby it is to be distinctly understood that the foregoing descriptive matter is to be interpreted merely as illustrative of the disclosure and not as a limitation.
,CLAIMS:WE CLAIM
1. A tamper indicating seal (100) comprising:
• a tamper loop having a first portion and a second portion, said tamper loop configured to close when an electrical connection is established between said first portion and said second portion; and
• a tamper detection chip (106) provided in said first portion, said tamper detection chip (106) configured to detect events corresponding to opening and closing of said tamper loop, and further configured to facilitate detection of tampering of said seal (100) based on the count of either said detected closing events or said detected opening and closing events.
2. The tamper indicating seal (100) as claimed in claim 1, which is in the form of a bolt seal comprising a bolt member (110) and a housing (116), wherein said housing (116) is configured to receive said bolt member (110), and further configured to facilitate snap-locking of said bolt member (110) therewithin.
3. The tamper indicating seal (100) as claimed in claim 2, wherein said first portion is embedded within said bolt member (110) and said second portion is embedded within said housing (116), wherein locking of said bolt member (110) with and said housing (116) causes said tamper loop to close and unlocking of said bolt member (110) from said housing (116) causes said tamper loop to open.
4. The tamper indicating seal (100) as claimed in claim 1, wherein said tamper detection chip (106) comprises:
• a control unit (118) configured to detect events corresponding to opening and closing of said tamper loop, and further configured to generate a closed event signal upon detecting closing of said tamper loop and an open event signal upon detecting opening of said tamper loop;
• a memory (122) comprising an identification register, a tamper flag register, and a pre-determined threshold tamper value, said identification register configured to store a unique identification code associated with said tamper indicating seal (100);
• a tamper switch (120) configured to cooperate with said control unit (118) to receive said closed event signal and said open event signal, and further configured to toggle between an open state position and a closed state position based on said received closed event and open event signals;
• a counter (124) configured to store a tamper count value, and further configured to cooperate with said tamper switch (120) to increment said tamper count value by one based on detection of change in the position of said tamper switch (120); and
• a comparator (126) configured to cooperate with said memory (122) and said counter (124) to receive said pre-determined threshold tamper value and said tamper count value respectively, and further configured to change the status of said tamper flag register, when said tamper count value becomes equal to said pre-determined threshold tamper value, thereby indicating tampering of said seal (100),
wherein said control unit (118), said counter (124), and said comparator (126) are implemented using one or more processor(s).
5. The tamper indicating seal (100) as claimed in claim 4, wherein said comparator (126) is configured to change at least one status bit of said identification code stored in said memory (122), when said tamper count value becomes equal to said pre-determined threshold tamper value, thereby indicating tampering of said seal (100).
6. The tamper indicating seal (100) as claimed in claim 4, wherein said counter (124) is a 3-bit memory and can count up to 7.
7. The tamper indicating seal (100) as claimed in claim 4, wherein said counter (124) is configured to increment tamper count value by one every time the tamper switch (120) toggles between the open state and closed state positions.
8. The tamper indicating seal (100) as claimed in claim 4, wherein said counter (124) is configured to increment tamper count value by one every time the tamper switch (120) toggles to the closed state position.
9. The tamper indicating seal (100) as claimed in claim 4, wherein the default value of said tamper count value stored in said counter (124) is zero.
10. The tamper indicating seal (100) as claimed in claim 4, wherein said tamper loop includes:
• at least one antenna (102) electrically connected to said tamper detection chip (106), said antenna (102) configured to cooperate with said memory (122) to transmit said identification code, status of said tamper loop, the count value, and status of said tamper flag register upon receiving a radio frequency signal from a reader (304);
• a battery (108) configured to supply power to said control unit (118) to facilitate generation of said closed event and said open event signals; and
• a capacitor (104) configured to supply power to said control unit (118) to facilitate generation of said closed event and open event signals in absence of power supply from said battery (108).
11. The tamper indicating seal (100) as claimed in claim 10, wherein said antenna (102) is selected from the group consisting of a high frequency antenna, an ultrahigh frequency antenna, and a low frequency antenna.
12. The tamper indicating seal (100) as claimed in claim 10, wherein the identification code, status of the tamper loop, the count value, and status of the tamper flag register are transmitted to said reader (304) using communication protocols selected from Radio Frequency Identification (RFID), Long Range Wide Area Network (LoRaWAN), Global Positioning System (GPS), and Wireless Fidelity (Wi-Fi).
13. The tamper indicating seal (100) as claimed in claim 10, wherein said identification code facilitates automatic identification of a container or a transport vehicle (302) to which said seal (100) is attached.
14. The tamper indicating seal (100) as claimed in claim 10, which is assumed to be tampered if said reader (304) is unable to read said unique identification code correctly.
15. The tamper indicating seal (100) as claimed in claim 4, wherein the status of said tamper flag register facilitates determining whether said seal (100) is tampered or not.
16. The tamper indicating seal (100) as claimed in claim 5, wherein the status bit of said identification code facilitates determining whether said seal (100) is tampered or not.
17. The tamper indicating seal (100) as claimed in claim 10, wherein said control unit (118) is configured to generate said open event signal when said battery (108) is removed without opening said tamper loop.
Dated this 7th Day of November, 2019

_______________________________
MOHAN DEWAN, IN/PA - 25
of R.K.DEWAN & CO.
Authorized Agent of Applicant

TO,
THE CONTROLLER OF PATENTS
THE PATENT OFFICE, AT MUMBAI