FIELD OF THE INVENTION
This invention relates to acquisition module which has the inherent capability to acquire
digital data on MIL STD 1553 bus by utilizing the capability of discrete components mounted in
synchronization with a MC68 K Processor.
BACKGROUND OF THE INVENTION
The embedded systems are based on highly-integrated 32-bit microcontrollers,
combining high-performance data manipulation capabilities with powerful peripheral
subsystems. CPU Module is the core module of acquisition system, whose job is to supervise or
control the functions of other modules, has extensive built-in-test facility for system health
monitoring, data acquisition, processing and storing. This module has been designed based on
the Motorola’s MC68K processor, a 32-bit Quad Integrated Communication Controller operating
at 25 MHz clock frequency. This is the module where main application program executes and
makes the entire hardware run accordingly. The communication among QUICC on CPU
Module, on-board peripherals MIL-1553B is interrupt based. But, for data transfer among
QUICC on CPU Module, on-board memories and other modules the necessary control signals
are generated by QUICC and two high performance CMOS CPLDs on Processor Module.
SUMMARY OF PRESENT INVENTION
At start-up (Power ‘ON’) time, software running on the CPU Module initializes –
registers, memories and MIL-STD-1553 interfaces. Processor Module senses the state of
function mode pins (FMODE1-FMODE0) for start of acquisition of Mil-STD-1553 data. Once the
power is ‘ON’ and mode is to start acquisition, it starts data acquisition from MIL-1553B data,
converts them into frames as per data frame format/layout and transmits them on RS 422 for
telemetry at 115.2 kbps baud rate & simultaneously store these frames in the external memory.
The activities of CPU Module have been scheduled / configured such that it finishes all
its activities in one second which is accomplished by using QUICC’s internal RISC timer and
keep on repeating the same for ever till the module is ‘ON’. The Processor Module performs
activities like – updating NVRAM contents, performing Self tests, fault indication – if any, data
acquisition from MIL-1553B bus. Then, it makes direct MIL-1553B data frame, FCS data frame,
stores these frames into PMM, transmitting the frame on RS422 for telemetry and transmitting
message words on MIL-1553B bus to OAC.
An another aspect of the present invention is to facilitate Fault Indication - whenever any
test fails during self testing of the module, & to drive the fault indication LED in the system’s
maintenance panel (external to module).
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention become more apparent and
descriptive in the description when considered together with figures/flow charts presented:
Figure 1: is a Block Diagram of ACE/Mini‐ACE Interface to 1553 Bus
Figure 2: is a Block Diagram of architecture of electronic module
DETAILED DESCRIPTION
The MIL-STD-1553B interfaced to the main processor card through the buffers and
CPLD in the 16-bit buffered mode. The signals between the buffers and the device are shown in
Figure: 2.
The 1553-B has 64K X 17 words of internal RAM. Hence to access this RAM, 16 bits of
address are connected to the 1553-B and the selection line from the CPLD is connected to the
memory control signal of the 1553-B. The Chip Select line of the CPLD is connected to the Chip
Enable pin of the MARK3 device. When the address line MEM/REG signal line is logic LOW, the
internal registers of MARK3 can be accessed and if the address line is logic HIGH, the internal
RAM of MARK3 can be accessed provided the respective chip select is asserted. The Read and
Write cycles associated with the MARK3 are to be externally terminated based on the READY
status signals from the MARK3.
The Direct coupled (DC) and Transformer coupled (TC) signals of channel A and
channel B from the transformer are brought out on the PCB edge connector to enable short stub
and long stub interconnects respectively. The interrupt lines of the MARK3 are connected to the
CPLD and then it goes to the Main processor module.
The CPU Module also has a MIL-STD-1553B bus interface, which has been provided by
Mil interface device. The Mil interface integrates dual 5V (low-power) transceivers,
encoder/decoders, BC/RT/MT multi-protocol logic, memory management and interrupt logic,
processor interface logic, 64K x 16-Bit of shared SRAM. It also contains internal address latches
and bidirectional buffers to provide a direct interface to QUICC bus. For FDR application, Mil
interface has been configured for RT mode. For each transmit, receive, or broadcast subaddress,
either a single-message data block, a double buffered data word blocks, or a variable
sized circular buffer may be allocated for data storage. The circular buffer feature can greatly
reduces the burden on QUICC for bulk data transfer. End-of-message interrupts may be
enabled either globally, following error message, on a transmit/receive/broadcast sub-address
or when any particular transmit/receive/broadcast sub-address circular buffer reaches its lower
boundary. An interrupt status register allows the host processor to determine the cause of all
interrupts by means of a single read operation. All address mapping of Mil interface is word
oriented, rather than byte oriented. Mil interface requires 16 MHz clock for its operation. The
interface between Mil interface and MIL-STD-1553 bus can be of two types depending on stub
length:
• Direct (Short Stub) Coupling – When stub length is up to 1 ft (max)
• Transformer (Long Stub) Coupling – When stub length is up to 20 ft (max)
Here, Transformer (Long Stub) Coupling has been used as stub length is exceeding 1
feet limit. For both types of coupling configuration, the transformer that interfaces directly to Mil
interface is the isolation transformer. Whereas the transformer that interfaces the stub to the
MIL-STD-1553 bus is the coupling transformer. The turn’s ratio of the isolation transformer
varies depending upon the specified peak-to-peak output voltage at the output terminals of Mil
interface. For transformer coupled applications with Mil interface, isolation transformer has been
used having 1:1.79 turn’s ratio.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Acquisition module for MIL-STD-1553B interfaced with Motorola MC68K microprocessor comprising; MIL 1553B Mini-Ace chip for interfacing with MIL-1553 Bus to Microprocessor, Buffers for transmitting and receiving of MIL1553B data with compatible format and CPLD is used to provide glue logic and control signal generation for the entire module for proper operation.

2. Acquisition module for MIL-STD-1553B of claim 1 wherein The MIL-STD-1553B interfaced to the main processor card through the buffers and CPLD in the 16-bit buffered mode.

3. Acquisition module for MIL-STD-1553B of claim 1 wherein The Direct coupled (DC) and Transformer coupled (TC) signals of channel A and channel B from the transformer are brought out on the PCB edge connector to enable short stub and long stub interconnects.

4. Acquisition module for MIL-STD-1553B of claim 3 wherein The Mil interface integrates dual 5V (low-power) transceivers, encoder/decoders, BC/RT/MT multi-protocol logic, memory management and interrupt logic, processor interface logic, 64K x 16-Bit of shared SRAM.

5. Acquisition module for MIL-STD-1553B as claimed in any of the preceding claims wherein Mil interface has been configured for RT mode for FDR application and for each transmit, receive, or broadcast sub-address, either a single-message data block, a double buffered data word blocks, or a variable sized circular buffer may be allocated for data storage.

6. Acquisition module for MIL-STD-1553B as claimed in any of the preceding claims wherein all address mapping of Mil interface is word oriented, rather than byte oriented. Mil interface requires 16 MHz clock for its operation. ,TagSPECI:As per Annexure-II