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Adaptive Clock Modulation

Abstract: Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
03 September 2022
Publication Number
14/2023
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
Parent Application

Applicants

INTEL CORPORATION
2200 Mission College Boulevard, Santa Clara, California 95054, USA

Inventors

1. TERRY REMPLE
13043, Via Caballo Rojo, San Diego, California - 92129, USA

Specification

Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/491,827 filed on 01 October 2021 and titled “ADAPTIVE CLOCK MODULATION” the entire disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD
[0002] Embodiments described herein pertain to supply voltages in integrated circuits. Some embodiments relate to operations associated with a voltage droop of a supply voltage.

Background
[0003] An integrated circuit device needs a supply volage to operate. During operations of the device, a sudden change in workload in the device can cause current consumption in the device to increase, which in turn can cause a sharp decrease in the supply voltage. Such a sharp decrease is commonly referred to as a voltage droop. A large voltage droop can change normal operating conditions of components (e.g., combinatorial logic circuitry) in the device that can lead to functional failure of the device. Numerous standard approaches have been designed to deal with voltage droops in the die voltage. However, such standard approaches have drawbacks including increasing power consumption and lowering the power and performance of the device, as discussed below.

Brief Description of the Drawings
[0004] FIG. 1 shows an apparatus in the form of a device including an adaptive clock modulation (ACM) block, according to some embodiments described herein.
[0005] FIG. 2A through FIG. 2F are diagrams showing the effect of changes in a die voltage of the device of FIG. 1 on a frequency of a clock signal during an operation of a delay circuit of the ACM of FIG. 1, according to some embodiments described herein.
[0006] FIG. 3A and FIG. 3B are graphs showing the relationship between a die voltage and frequency including a frequency overshoot at an output of the delay circuit of FIG. 1 during different time intervals of the operations of the delay circuit, according to some embodiments described herein.
[0007] FIG. 4 is a timing diagram showing a transient response of the ACM block of FIG. 1 in response to a voltage droop of a die voltage used in the device of FIG. 1, according to some embodiments described herein.
[0008] FIG. 5 is a graph showing changes in a minimum die voltage at different times based on the transient response of the ACM block of FIG. 1, according to some embodiments described herein.
[0009] FIG. 6 is a graph showing changes in clock frequency at different times based on the transient response of the ACM block of FIG. 1, according to some embodiments described herein.
[0010] FIG. 7 is a flowchart showing a method of responding to a voltage droop of a die voltage, according to some embodiments described herein.
[0011] FIG. 8 shows a block diagram of a machine (e.g., a computer system) including the device of FIG. 1, according to some embodiments described herein.

Detailed Description
[0012] Numerous conventional approaches have been used to mitigate first voltage droop, including proactive scheduling, charge injection, digital linear voltage regulation, clock squashing, and other approaches. However, these approaches have their drawbacks.
[0013] Proactive scheduling attempts to predict when a workload will cause a large increase in current consumption, and then proactively schedule future operations over a longer period such that the current peak is avoided. Although it may be possible to predict when certain operations are likely to cause current peaks, the size of the peak is a function of both the operations and the input data. Proactive scheduling is not able to predict whether the incoming data will cause a peak. As a result, proactive scheduling is subject to both false positives (slowing down the processor when it doesn’t need to be slowed down), and false negatives (not slowing down the processor when it does need to be slowed down). Proactive scheduling doesn’t generally result in any significant PnP improvement. The Power and Performance (PnP) metric is defined as the energy to execute a given workload multiplied by the execution time. Lower values of PnP indicate better overall performance.
[0014] Charge injection attempts to mitigate a first voltage droop by injecting charge into the voltage rail whenever it drops below some voltage. There are several issues with charge injection. For example, the charge needs to be stored at a higher voltage than the rail voltage, it has to be fast enough to respond to a first voltage droop, and such charge injection generally needs a certain amount of time to replenish its stored charge after an injection event. If a second droop event occurs before the charge has been replenished, the second droop event is not mitigated. Secondly, charge injection generally occurs whenever the rail drops below some threshold. Setting this threshold to high, results in triggering charge injection too often, which consumes extra power. Setting this threshold too low decreases then amount of time the circuit has to react, resulting in marginal mitigation. For the above reasons, when charge injection is used in real systems with random workloads, it generally fails to provide a PnP improvement.
, Claims:
1. An apparatus comprising:
a supply node to receive a die voltage;
a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal;
a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and
a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

Documents

Application Documents

# Name Date
1 202244050398-US 17491827-DASCODE-3758 [03-09-2022].pdf 2022-09-03
2 202244050398-FORM 1 [03-09-2022(online)].pdf 2022-09-03
3 202244050398-DRAWINGS [03-09-2022(online)].pdf 2022-09-03
4 202244050398-DECLARATION OF INVENTORSHIP (FORM 5) [03-09-2022(online)].pdf 2022-09-03
5 202244050398-COMPLETE SPECIFICATION [03-09-2022(online)].pdf 2022-09-03
6 202244050398-FORM-26 [28-12-2022(online)].pdf 2022-12-28
7 202244050398-FORM 3 [03-02-2023(online)].pdf 2023-02-03
8 202244050398-Proof of Right [10-10-2023(online)].pdf 2023-10-10
9 202244050398-FORM 18 [24-09-2025(online)].pdf 2025-09-24