The present disclosure relates to field effect transistors, and in particular relates to fabrication of vertical tunnel field-effect transistors (VTFET).
BACKGROUND
In recent years, continuous scaling down of MOSFET devices have been reached the nanoscale domain. CMOS devices have been observed to exhibit two fundamental limits: (a) larger OFF-state current due to subthreshold conduction and (b) subthreshold slope (SS) greater than 60 mV/decade at room-temperature. A lower SS gives a higher I_ONT_OFF ratio and a lower power dissipation in the OFF-state. In sub-threshold region of MOSFET, the SS is defined as:
ss=d(log10IDS) = 23M,+C^
dVG q \ Cox)
where C_d is the depletion region capacitance, C_ox is the gate oxide capacitance, q is the charge of electron, T is temperature and k is Boltzmann constant. Accordingly, devices having steep 'SS' have been researched with the aim of replacement of conventional MOSFETs in future semiconductor circuits.
As a part of solution, TFET comes with benefits such as lower OFF-state current and less than 60 mV/decade SS at room temperature, which makes it a promising device for low-power energy efficient circuits. Despite such advantages, TFET faces at-least a limitation of ambipolarity. Ambipolarity typically depicts that the device conducts current for both positive gate voltage supply and negative gate voltage supply. It represents that the same TFET with the electrons as majority carriers exhibits n-type behavior and with the holes as majority carriers exhibits p-type behavior, at the same drain voltage-supply. Such a limitation restricts the usability of TFET for digital circuit design in complementary circuit-applications.
In an ideal TFET, Ambipolar current is not desirable at least due to following reasons:
1. Ambipolar conduction would permit a higher OFF-state current.
2. It would lead to higher stand-by leakage or circuit failure for the CMOS-type circuits.

Conventionally, various approaches have been adopted to suppress the ambipolarity in TFETs such as gate-drain underlap/overlap, asymmetric source/drain doping, non-uniform drain doping, spacer engineering, work-function engineering, drain-pocket and gate material engineering etc. While such approaches attempt to suppress the ambipolarity, yet they remain substantially far from fully eliminating the ambipolar-current. Moreover, such approaches tend to act adversely by leading to reduction in ON-state current.
Therefore, there lies a need to eliminate ambipolarity and accordingly achieve efficiency.
There lies at least another need to achieve ambipolarity-free TFET for large range of negative voltage.
SUMMARY
This summary is provided to introduce a selection of concepts in a simplified-format that are further described in the detailed description of the invention. This summary is not intended to identify key or essential inventive concepts of the invention, nor is it intended for determining the scope of the invention.
The present subject matter describes a vertical tunnel field effect transistor (VTFET) . The VTFET comprises a source region comprising a lower band-gap semiconductor-material. A drain region comprises a higher band-gap semiconductor material, wherein the drain region defines a doping-type opposite the source-region's doping-type. A channel-region is located between the source-region and the drain-region and comprising a higher band-gap semiconductor material. The channel region defines a doping-type opposite the source-region's doping-type. A gate-terminal is located above the source-region and is at-least partly in contact with the source-region through a gate-dielectric. At-least one doped epitaxial layer is located between the source-region and the gate-dielectric, wherein said epitaxial layer is disposed parallel to the gate-dielectric and at least defined by a doping-type opposite the source-region's doping-type.
The present subject matter at-least enables a novel Vertical Tunnel Field Effect Transistor (VTFET) to completely eliminate ambipolar-conduction. While the presence of heteroj unction boosts the ON-state current, a low drain doping concentration at least leads to elimination of the ambipolar conduction. In an example, a 2-D sentauraus TCAD simulator is

used for simulation and a deep-meshing is used for simulation in respect of the present VTFET. Furthermore, as will be evident from the detailed description, the DC, Analog/RF and Linearity-characteristics of the proposed device exhibits tremendous performance, which makes it an effective candidate for nanoscale low-power devices and digital circuits.
At least an aim of this present subject matter is to improve the ON-state current and to completely eliminate the ambipolar conduction to make the TFETs a real contender for reliable low-power circuits. The present subject matter achieves elimination of the ambipolar conduction without sacrificing the ON-state current. The presence of hetero-junction boosts the ON-state current due to narrower tunneling barrier width between source and channel region and the presence of low doping concentration at drain region (ND = 2 x 1018 /cm3) widens the tunneling barrier width between the channel and drain region (as shown in Fig. 8), which indicates complete elimination of ambipolarity conduction is achieved.
At least the ambipolarity-free behavior of the present VTFET enables a usage for digital-circuits design, since the VTFET is in ON-state for positive gate voltage supply and in OFF-state for negative gate voltage supply, thereby meeting the ideal conditions. In addition to these benefits, other Analog/RF and linearity parameters also ensure present VTFET as a suitable candidate for CMOS circuits.
To further clarify advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

Fig. 1 depicts a schematic view of Single gate hetero material (SG-HM) VTFET, in accordance with an embodiment of the present invention;
Fig. 2 depicts a simulated energy band diagram of SG-HM VTFET of Fig. 1
Fig. 3 illustrates transfer-characteristics of the SG-HM VTFET of Fig. 1;
Fig. 4 illustrates ambipolar-characteristics of the SG-HM VTFET of Fig. 1 at Vgs = -0.5V;
Fig. 5 illustrates ambipolar-characteristics of the SG-HM VTFET of Fig. 1 at Vgs = -1.0V;
Fig. 6 illustrates ambipolar-characteristics of the SG-HM VTFET of Fig. 1 at Vgs = -1.5V;
Fig. 7 illustrates ambipolar-characteristics of the SG-HM VTFET of Fig. 1 at Vgs = -1.8V;
Fig. 8 illustrates an energy-band diagram of the SG-HM VTFET of Fig. 1 for representing ambipolar-characteristics;
Fig. 9 illustrates Transconductance with respect to gate voltage of the SG-HM VTFET of
Fig. 1;
Fig. 10 illustrates Capacitance with respect to gate voltage of the SG-HM VTFET of Fig.
i;
Fig. 11 illustrates variation of cut-off frequency (fr) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 12 illustrates variation of gain bandwidth product (GBP) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 13 illustrates variation of transit time (s) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 14 illustrates variation of transconductance frequency product (TFP) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 15 illustrates a variation of transconductance generation factor (TGF) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 16 illustrates a variation of second order voltage interceptor point (VIP2) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 17 illustrates a variation of third order voltage intercept point (VIP3) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 18 illustrates a variation of third order intermodulation intercept point (IIP3) with respect to gate voltage of the SG-HM VTFET of Fig. 1;
Fig. 19 illustrates a variation of third order intermodulation distortion (IMD3) with respect to gate voltage of the SG-HM VTFET of Fig. 1;

Fig. 20 illustrates a variation of 1-dB compression point with respect to the SG-HM VTFETofFig. 1;
Further, skilled artisans will appreciate that elements in the drawings are illustrated for simplicity and may not have been necessarily been drawn to scale. For example, the flow charts illustrate the method in terms of the most prominent steps involved to help to improve understanding of aspects of the present invention. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understand the embodiments of the present invention so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having benefit of the description herein.
DETAILED DESCRITION OF FIGURES
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are explanatory of the invention and are not intended to be restrictive thereof.
Reference throughout this specification to "an aspect", "another aspect" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does

not include only those steps but may include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or sub-systems or elements or structures or components proceeded by "comprises... a" does not, without more constraints, preclude the existence of other devices or other sub-systems or other elements or other structures or other components or additional devices or additional sub-systems or additional elements or additional structures or additional components.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The system, methods, and examples provided herein are illustrative only and not intended to be limiting.
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
Fig. 1 depicts a schematic-view of Single gate hetero material (SG-HM) VTFET 100, in accordance with an embodiment of the present invention.
The VTFET 100 comprises a source region 102 having a lower band-gap semiconductor-material. In an implementation, the source-region is defined by at least one of a low band-gap semiconductor material 'Germanium', a doping-concentration (NA) of 2 X 1020; a source-length (Ls) of 80 nano-meters; and a thickness (ts;) of about 10 nano-meters.
Further, the VTFET 100 comprises a drain region 104 comprising a higher band-gap semiconductor material, said drain region 104 defining a doping-type opposite the source-region's doping-type. The drain-region 104 is defined by at least one of: a high band-gap semiconductor material 'Si'; a doping-concentration (No) of 2*1018, a drain-length (Ld) of 50 nano-meters; and a thickness (ts;) of about 10 nano-meters.
Further, the VTFET 100 comprises a channel-region 106 located between the source-region and the drain-region and comprising a higher band-gap semiconductor material, said channel region defining a doping-type opposite the source-region's doping-type. The channel-region 106 is defined by at least one of a high band-gap semiconductor material 'Si', a doping-concentration (Nc) of 2x1016, a channel-length (Lc) of 20 nano-meters; and a thickness (ts;) of

about 10 nano-meters. Accordingly, a hetero-junction is formed between source-region 102 and channel region 106.
Further, a gate-terminal 108 is located above the source-region 102 and is at-least partly in contact with the source-region 102 through a gate-dielectric 110. The gate-dielectric 110 is a Hafnium-dioxide (HfCh) layer defined by an oxide-thickness (tox) of 2 nano-meter 110.
In an implementation, the gate-dielectric 110 or dielectric layer 110 is constituted by two spacers of HfC>2, having a dielectric constant of 25. The first spacer of length 20 nm is disposed at source-gate electrode and a second spacer of length 40 nm is located at gate-drain electrode to reduce the OFF current.
At-least one doped epitaxial layer 112 is located between the source-region 102 and the gate-dielectric and disposed parallel to the gate-dielectric 110. The epitaxial layer 112 is defined by at least a doping-type opposite the source-region's 102 doping-type, a high band-gap semiconductor material 'Si'; and a doping-concentration (NE) of 2 X 1016.
Overall, the gate-terminal 108, the gate-dielectric 110 and the epitaxial layer 112 are aligned at the side source-region 102. Further, the neighbouring regions of the epitaxial layer 112 comprises the source region 102 and at-least one of the channel region 106 or gate-dielectric 110.
The VTFET 100 further comprises a silicon-dioxide based 'dielectric buried oxide' 114 (box) below the source 102, channel 106 and drain region 104. The buried oxide is defined by at least one of a thickness (tt,ox) of about 8 nano-meter; and a length (LBS) of about 150 nano-meter.
In an implementation, the aforesaid VTFET 100 is a n-channel single gate hetero material VTFET (SG-HM VTFET) as shown in Fig. 1. In an example, the VTFET 100 may be electronically simulated through a 2D Sentaurus TCAD simulation tool, BTBT model, bandgap narrowing model, Shockley-Read-Hall (SRH) model, Drift-diffusion current transport model, Auger recombination, Lombardi mobility model and configured to attain optimized results. In an example, Table 1 shows the list of device simulation parameters.

Table 1

Parameters SG-HM VTFET
Channel thickness (tsi) 10 nm
Oxide thickness (tox) 2 nm
BOX thickness (tbox) 8nm
Drain length (LD) 50 nm
Channel length (Lc) 20 nm
Source length (Ls) 80 nm
Si02 BOX length (LBS) 150 nm
-3
Channel concentration (Nc) (cm ) 2 X 1016
-3
Drain concentration (ND) (cm ) 2 X 1018
-3
Source concentration (NA) (cm ) 2 X 1020
-3
Epitaxial layer concentration (NE) (cm ) 2 X 1016
This description of forthcoming figures 2-20 refers transfer & ambipolar characteristics of SG-HM VTFET 100 and performance parameters in terms of DC, analog/RF and Linearity metrics of proposed SG-HM VTFET 100.
Fig. 2 depicts a simulated energy band diagram of SG-HM VTFET of Fig. 1. Fig. 2 demonstrates the simulated energy band diagram of SG-HM VTFET, where it can be noticed that tunneling probability is higher in SG-HM VTFET which is responsible to drive more drain current in ON-state. Gate voltage controls the tunneling current. As gate voltage is increased, the junction at source-epitaxial layer becomes wider which leads to the increment in tunneling current. The existence of lower band-gap material (Ge) at the source side increases the carrier concentration and decreases tunneling barrier width which causes significant increase in tunneling current.
Fig. 3 depicts transfer-characteristics of SG-HM VTFET of Fig. 1. The transfer characteristic depict that SG-HM VTFET offers a very low leakage current and higher drive current. The leakage current of the SG-HM VTFET is 8.601 x 10"16 A/fim and the drive

current of the SG-HM VTFET is 2.133 x 10 4 A/fim. This proposed device has attained 1ON/1OFF = 0.247 x 1012, DIBL = 17 mV/V and steep subthreshold slope (SS) = 21.48 mV/decade. This shows that proposed structure provides superior performance.
Fig. 4, Fig. 5, Fig. 6 and Fig. 7 shows the ambipolar characteristics at different negative gate voltages, i.e. Vgs = -0.5V, Vgs = -1.0V, Vgs = -1.5V and Vgs = -1.8V, respectively, and accordingly show no ambipolar current.
Fig. 8 illustrates an energy-band diagram of the SG-HM VTFET of Fig. 1 for representing ambipolar-characteristics. The energy band diagram of Fig. 8 clearly indicates that no tunneling take place in between channel and drain region in ambipolar state. Therefore, zero ambipolar current exists in this device which is a tremendous advantage over LTFET which only suppress the ambipolar current upto some extent. However, the proposed SG-HM VTFET completely eliminates the ambipolar conduction.
The description of forthcoming figure 9 till 15 illustrate performance evaluation of analog/RF characteristics. More specifically, considering the requirements of high-speed communication, different analog/RF parameters have been analyzed so as to achieve superior performance for high-frequency applications. These parameters include such as transconductance (gm ), gate to source capacitance (Cgs), gate to drain capacitance (Cgd ), gain bandwidth product (GBP), cut-off frequency (fr ), transit time (x), transconductance frequency product (TFP) and transconductance generation factor (TGF).
Fig. 9 illustrates 'transconductance' with respect to gate voltage of the SG-HM VTFET of Fig. 1. More specifically, Fig. 9 represents the higher value of gm approximately 1.21 x 10~3A/V in SG-HM VTFET. Higher value of the transconductance (gm) gives the amplification capability of the device and is expressed as:
The effect of parasitic capacitance is required to be considered when a device works at higher frequency. This parasitic capacitance is responsible for circuit oscillation at high-frequency which results in signal distortion. Therefore, these capacitances must be suppressed to reduce the

signal distortion. As compared to other capacitances, Cgd plays a crucial role to degrade the device performance.
Fig. 10 illustrates Capacitance with respect to gate voltage of the SG-HM VTFET of Fig. 1. More specifically, Fig. 10 shows that as potential barrier at source-channel region decreases, it results in decrease of Cgs with increase in Vgs. In SG-HM VTFET, Cgs is higher owing to the presence of lower band-gap material at source region. On the other hand, Cgd increases with increase in Vgs as a result of enhance potential barrier at channel-drain region as depicted in Fig. 9. In SG-HM VTFET, Cgd is lower owing to the presence of higher band-gap material at drain region. It is noticed that SG-HM VTFET attained smaller value of total capacitance as clarified in Fig. 9, which is essential to reduce signal distortion.
To use the device for wireless applications, other RF parameters in terms of fT, GBP, z, TFP and TGF are also calculated as depicted in Fig. 11 till 14.
Fig. 11 illustrates variation of cut-off frequency (fr) with respect to gate voltage of the SG-HM VTFET of Fig. 1. demonstrates the changes in fT with respect to Vgs. fT is expressed as the frequency at which device operates and makes the short circuit current gain falls to unity and can be calculated as:
2n(Cgs + Cgd) SG-HM VTFET has higher value of fT as a result of higher value of gm because of the presence of lower band-gap material at source region as observed in Fig. 11.
Fig. 12 illustrates variation of gain bandwidth product (GBP) with respect to gate voltage of the SG-HM VTFET of Fig. 1. GBP is computed for certain DC gain of 10 and can be calculated as:
GBP = 9m (4)
20nCgd K )
GBP plays an important role to offer the trade-off between bandwidth and gain for a given
device. Fig. 12 depicts that higher value of GBP is obtained in SG-HM VTFET as a result of
increase in the value of Cgd even though the higher value of gm.
Fig. 13 illustrates variation of transit time (s) with respect to gate voltage of the SG-HM VTFET of Fig. 1. The transit time, z, plays an vital role in RF ciruits. It measures the time required by

the charge carriers to cover the distance between source and drain region and decides the switching speed, r variation with Vgs is depicted in Fig 13. It is the reciprocal of fT and formulated as:
T = ^T (5)
2nfT From the above equation, it can be observed that higher switching speed leads to better response of the device. Thus, it can be noticed from Fig. 13 that better switching speed is obtained in SG-HM VTFET.
Fig. 14 illustrates variation of trans conductance frequency product (TFP) with respect to gate voltage of the SG-HM VTFET of Fig. 1. TFP is another key parameter to analyse the device behavior for high-speed designs and is defined as:
TFP = (^jxfT (6)
Fig. 15 illustrates a variation of transconductance generation factor (TGF) with respect to the SG-HM VTFET of Fig. 1. SG-HM VTFET have higher TFP due to higher gm as illustrated in Fig. 9. TGF is also known as device efficiency. It refers to the device ability to transform DC parameter (drain current) into AC parameter (gm) and is calculated as:
TGF = j± (7)
Us
Fig. 16 till 20 illustrate consideration of linearity parameters for analysing device performance for RFIC designed system at high frequency regime. The distortion is required to be minimum in the output signal over the required input voltage range for a system to be sustainable at high frequencies. The important parameters for linearity analysis of device are second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order intermodulation intercept point (IIPs), third order intermodulation distortion (IMD3) and 1-dB compression point which can be defined as below:
VIP2 = 4 x — (8)
9m2
VIP3 = (24 x— (9)
9m3
UP3 = - x 9ml (10)
3 9m3 X °s

IMD3 = RS[4.S x (VIP33) X gj (11)
1-dB = 0.22 — (12)
A 9ml
where Rs = 5 OH is considered.
Fig. 16 illustrates a variation of second order voltage interceptor point ( VIP2), Fig. 17 illustrates a variation of third order voltage intercept point ( VIP3), Fig. 18 illustrates a variation of third order intermodulation intercept points (IIP3), Fig. 19 illustrates a variation of third order intermodulation distortion (IMD3), and Fig. 20 illustrates a variation of 1-dB compression point with respect to gate voltage of the SG-HM VTFET of Fig. 1;
In VIP2, first and second order harmonics are equal. Fig. 16 shows the amplitude of VIP2 of SG-HM VTFET is higher at low Vgs which is required to attain the high linearity. In VIP3, first and third harmonics are equal. Similarly, Fig. 17 depicts the higher peak value of VIP3 at low Vgs which results in higher degree of linearity. The graph of IIP3 is demonstrated in Fig. 18, where IIP3 is higher for SG-HM VTFET which is the effect of higher transconductance.
Another important linearity parameter is IMD3 in which first and third harmonics are equal. It gives degeneracy in communication system. Fig. 19 shows the required changes in IMD3 with VgS for SG-HM VTFET. A 1-dB compression point gives the minimal value of input power from its model value to drop the gain by 1-dB. Fig. 20 illustrates the higher peak value of 1-dB compression point of SG-HM VTFET at lower gate voltage which is responsible to attain low distortion and higher linearity. Table 2 illustrates the optimized results.
Table 2

Parameters SG-HM VTFET
I0N(A/nm) 2.133 X10"4
I0FF(A/nm) 8.601 X 10"16
ION/IOFF 0.247 X 1012
SS(mV/decade) 21.48

9m (.A/V) 1.21 X 10"3
CgsifF) 6.2
CgdifF) 13
CtotalifF) 15
MGHz) 14
GBP (GHz) 17
DIBL(mV/V) 17
The present subject matter at least provides a novel Vertical Tunnel Field Effect Transistor (VTFET) which completely eliminates ambipolar conduction. It has been investigated that the presence of heteroj unction boost the ON-state current and low drain doping concentration completely eliminates the ambipolar conduction. The present subject matter improves the ON-state current and completely eliminates the ambipolar conduction to make the TFETs a real contender for reliable low-power circuits. The present SG-HM VFET eliminates the ambipolar conduction without sacrificing the ON-state current. The presence of heteroj unction boosts the ON-state current due to narrower tunneling barrier width between source and channel region and the presence of low doping concentration at drain region (ND = 2 x 1018 /cm3) widens the tunneling barrier width between the channel and drain region as shown in Fig. 8, which indicates that the complete elimination of ambipolarity conduction is achieved.
Ambipolarity-free behavior of TFET makes it a good candidate for digital circuits design because such device is in ON-state for positive gate voltage supply and in OFF-state for negative gate voltage supply. In addition to these benefits, other Analog/RF and linearity parameters are also analyzed that offers satisfactory results to enable the SG-HM VTFET as a good candidate for CMOS circuits.
While specific language has been used to describe the disclosure, any limitations arising on account of the same are not intended. As would be apparent to a person in the art, various

working modifications may be made to the method in order to implement the inventive concept as taught herein.
The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment.
The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any component(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component.

WE CLAIM

1.A vertical tunnel field effect transistor (VTFET) comprising:
a source region (102) comprising a lower band-gap semiconductor-material;
a drain region (104) comprising a higher band-gap semiconductor material, said drain region defining a doping-type opposite the source-region's doping-type;
a channel-region (106) located between the source-region and the drain-region and comprising a higher band-gap semiconductor material, said channel region defining a doping-type opposite the source-region's doping-type;
a gate-terminal (108) located above the source-region (102) and at-least partly in contact with the source-region through a gate-dielectric (110);
and
at-least one doped epitaxial layer (112) located between the source-region (102) and the gate-dielectric (110), said epitaxial layer (112) disposed parallel to the gate-dielectric (110) and at least defined by a doping-type opposite the source-region's doping-type.
2.The VTFET (100) as claimed in claim 1, wherein the gate-terminal (108), the gate-dielectric (110) and the epitaxial layer (112) are aligned at the side of source-region (102).
3.The VTFET (100) as claimed in claim 1, wherein the epitaxial layer (112) has neighbouring regions comprising:
the source region (102) and
at-least one of the channel region (106) or gate-dielectric (110).
4.The VTFET (100) as claimed in claim 1, wherein a hetero-j unction is formed between source-region (102) and channel region (106).
5.The VTFET as claimed in claim 1, wherein the source-region (102) is defined by at least one of:
a low band-gap semiconductor material 'Germanium';
a doping-concentration of 2 x 1020;
a source-length of 80 nano-meters; and
a thickness of about 10 nano-meters.

6.The VTFET (100) as claimed in claim 1, wherein the channel-region (106) is defined by at
least one of:
a high band-gap semiconductor material 'Si';
a doping-concentration of 2 x 1016 ;
a channel-length of 20 nano-meters; and
a thickness of about 10 nano-meters.
7.The VTFET (100) as claimed in claim 1, wherein the drain-region (104) is defined by at least
one of:
a high band-gap semiconductor material 'Si';
a doping-concentration of 2 x 1018 ;
a drain-length of 50 nano-meters; and
a thickness of about 10 nano-meters.
8.The VTFET (100) as claimed in claim 1, wherein the epitaxial-layer (112) is defined by at-
least one of:
a high band-gap semiconductor material 'Si';
a doping-concentration of 2 x 1016;
9.The VTFET (100) as claimed in claim 1, wherein gate-dielectric is a Hafnium-dioxide (HfCh)
layer (110) defined by an oxide-thickness of 2 nano-meter.
10.The VTFET (100) as claimed in claim 1, further comprising:
a silicon-dioxide based dielectric buried oxide below the source (102), channel (106) and drain region (104) and defined by at least one of:
a thickness of about 8 nano-meter; and
a length of about 150 nano-meter.