DESC:TECHNICAL FIELD OF THE INVENTION

[0001] The present disclosure/invention relates generally to a motherboard and more particularly, to an efficient motherboard for Control Centre Processing Unit (CCPU).
BACKGROUND OF THE INVENTION

[0002] Generally, motherboard is known as a main printed circuit board (PCB) in general-purpose computing devices and other expandable systems. The motherboard functionality can be improvised by building intelligence on the board itself.
[0003] In air defense systems, the command and control centre plays a pivotal role in performing mission critical air defense operations. It is the management infrastructure for defense. A control centre intrinsically performs a diverse range of activities, incorporating a complex mixture of personnel and man-made systems to effectively manage the planning, execution and control all the air operations to protect vulnerable areas and points. Generally, a control centre commands and controls a large number of combat groups, each of which usually consists of tracking radar, launcher and support systems. Hence, any failure in the control centre will result in failure of entire air defence system. So, it becomes imperative to design highly reliable control centre hardware, more importantly the Control Centre Processing Unit (CCPU), which provides real time air situation picture to the Commander on the commander console to perform effective command and control operations. Designing for redundancy is an effective way to improve the reliability of the mission critical systems akin CCPU.
[0004] One of the prior art describes that multiplexer is used for connecting two or more sources to a single destination among computer units, and it is useful for constructing a common bus system. However, multiplexer becomes the single point failure even with redundancy.
[0005] Another prior art refers to a KVM (K: keyboard, V: video, M: mouse) switch that switches a plurality of computers when a console composed of keyboard, a mouse and a monitor is shared between a plurality of computers. However, modern commander console consists of additional I/O’s devices like optical encoder, touch screen interface of display, functional keyboard matrix switch, and optical encoder etc.,
[0006] The traditional KVMs are only used for switching keyboard, display video and mouse. Further, the conventional design involves the use of external KVMs, which is interfaced between processor unit and the console displays amidst various connector junctions and cable interfaces.
[0007] Usually, in air cooled chassis, the typical MIL-GRADE circular I/O connector are fixed to chassis and routed via cables from motherboard through Rear Transition Modules (RTM). Further, in usual design of military air-cooled chassis, the circular I/O connector are fixed to chassis and routed via cables from motherboard through Rear Transition Modules (RTM). This increases the size of the unit along junctions for the signals.
[0008] Therefore, there is a need with an efficient motherboard for Control Centre Processing Unit (CCPU) to solve the above-mentioned limitations.
SUMMARY OF THE INVENTION
[0009] An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.
[0010] Accordingly, in one aspect of the present invention relates to a fault tolerant system for a Control Centre Processing Unit (CCPU) of a defense system, the system comprising: a motherboard and a console, the motherboard comprising: at least two Single Board Computer (SBC) configured to perform a control operations of the Control Centre Processing Unit (CCPU) which provides a real time air situation picture to commander on the commander console to perform effective command and control operations, wherein during operation the motherboard connects first SBC to console I/O’s and second SBC works in hot stand by operation, at least one USB switching circuit configured and integrated to the motherboard for selecting and switching either of the two Single Board Computer (SBC) to the console I/O’s, at least one USB multiplexer configured to receive signals from the USB switching circuit for multiplexing, at least one high speed signal conditioner configured at output of each stage to compensate for Inter-symbol Interference (ISI) signal loss and at least two Power Supply (PS) configured to supply power to each Single Board Computer (SBC).
[0011] Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0012] The detailed description is described with reference to the accompanying figures.
[0013] Figure 1 shows a context diagram of CCPU according to an exemplary implementation of the present disclosure/ invention.
[0014] Figure 2 shows a block diagram of CCPU and console according to an exemplary implementation of the present disclosure/invention.
[0015] Figure 3 shows a schematic diagram of USB switching circuit according to an exemplary implementation of the present disclosure/invention.
[0016] Figure 4 shows a layout of motherboard according to an exemplary implementation of the present disclosure/invention.
[0017] Figure 5 shows an eye diagram of USB according to an exemplary implementation of the present disclosure/invention.
[0018] Figure 6 shows a GA views of CCPU according to an exemplary implementation of the present disclosure/invention.
[0019] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION OF THE INVENTION
[0020] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
[0021] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
[0022] It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces.
[0023] By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.
[0024] Figures discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way that would limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged communications system. The terms used to describe various embodiments are exemplary. It should be understood that these are provided to merely aid the understanding of the description, and that their use and definitions in no way limit the scope of the invention. Terms first, second, and the like are used to differentiate between objects having the same terminology and are in no way intended to represent a chronological order, unless where explicitly stated otherwise. A set is defined as a non-empty set including at least one element.
[0025] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these details. One skilled in the art will recognize that embodiments of the present disclosure, some of which are described below, may be incorporated into a number of systems.
[0026] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently disclosure and are meant to avoid obscuring of the presently disclosure.
[0027] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0028] The various embodiments of the present invention describe about a Motherboard for Control Centre Processing Unit (CCPU) for fault tolerant operation using dual modular redundancy. The present invention describes about the design of the motherboard for Control Centre Processing Unit (CCPU), which interfaces the Single Board Computer’s (SBC’s) along console Input/output devices and primly the redundancy circuit. Apparently, for implementing redundancy, requires a method of switching to the redundant SBC in case of failure of working SBC. The switching circuit plays a critical role in redundancy design and usual design approach is single stage multiplexer.
[0029] The present invention provides the design of the motherboard for Control Centre Processing Unit (CCPU), which interfaces the Single Board Computer’s (SBC’s) along console Input/output devices and primly the redundancy circuit. Apparently, for implementing redundancy, requires a method of switching to the redundant SBC in case of failure of working SBC. The switching circuit plays a critical role in redundancy design and usual design approach is single stage multiplexer.
[0030] In one embodiment, the present invention provides a motherboard for CCPU for fault tolerant operation using dual modular redundancy.
[0031] In one embodiment, the present invention is catered for various I/O devices of commander console.
[0032] In the present invention, the switching circuit itself is embedded on the motherboard and output is directly taken to console, thus avoiding intermediate junctions, which makes the design compact.
[0033] Generally, in air cooled chassis, the typical MIL-GRADE circular I/O connector are fixed to chassis and routed via cables from motherboard through Rear Transition Modules (RTM). In the present invention, the MIL-GRADE circular I/O connectors are fixed on the motherboard itself, which avoids cables and minimise junctions. This makes design very compact and more reliable. This design methodology is very useful in handling high frequency signals where multiple junctions can create interference and may result in signal loss also.
[0034] In one embodiment, the present invention avoids single point failure of switching circuit with dual stage switches compared to single stage multiplexer design in KVMs, which are un-reliable.
[0035] Figure 1 shows a context diagram of Control Centre Processing Unit (CCPU) according to an exemplary implementation of the present disclosure/ invention.
[0036] The figure shows a context diagram of Control Centre Processing Unit (CCPU). The Control Centre Processing Unit (CCPU) is the main control and data processing system of Command, Control, Communications, Computers and Intelligence (C4I) control centre which is interfaced with the console to provide the air situation picture and combat control operations to the commander.
[0037] The console consists of various Input/output devices viz., display, keyboard, trackball, functional keyboard, Optical LED and Rotary encoder with soft buttons. The target data received from radar is presented to the commander along command and control operation are carried out with these I/O devices.
[0038] In one embodiment, the present invention relates to a fault tolerant system for a Control Centre Processing Unit (CCPU) of a defense system, the system comprising: a motherboard and a console, the motherboard comprising: at least two Single Board Computer (SBC) configured to perform a control operations of the Control Centre Processing Unit (CCPU) which provides a real time air situation picture to commander on the commander console to perform effective command and control operations, wherein during operation the motherboard connects first SBC to console I/O’s and second SBC works in hot stand by operation, at least one USB switching circuit configured and integrated to the motherboard for selecting and switching either of the two Single Board Computer (SBC) to the console I/O’s, at least one USB multiplexer configured to receive signals from the USB switching circuit for multiplexing, at least one high speed signal conditioner configured at output of each stage to compensate for Inter-symbol Interference (ISI) signal loss, and at least two Power Supply (PS) configured to supply power to each Single Board Computer (SBC).
[0039] The motherboard interfaces the Single Board Computer’s (SBC’s) with console Input/output devices. The console comprises plurality of Input/output devices configured to provide an air situation picture and combat control operations to the commander.
[0040] The system wherein in case of failure of one of the Single Board Computer (SBC), the motherboard connects another Single Board Computer (SBC) to perform un-interrupt command and control operations for an user on the commander console, thus the system is highly fault tolerant and meets the critical mission requirement. Further, the system is configured with two stages of multiplexing scheme, where first stage comprises demultiplexing with demultiplexer circuit and second stage comprises multiplexing with multiplexer circuit.
[0041] In the present invention, the switching circuit further comprises at least two demultiplexer, wherein during an operation, an SBC 1 output is available at the output of switching circuit (J17 connector) and SBC 2 output is available at the first stage (J9 connector), wherein during another operation, an SBC 2 output is available at the output of switching circuit (J17 connector) and SBC 1 output is available at the first stage (J1 connector).
[0042] The system wherein in case of failure of second stage multiplexer circuit, the output is obtained at the first stage of demultiplexer output. The system wherein in case of failure of one of the demultiplexer of the first stage demultiplexer circuit, the output is available at another demultiplexer of the first stage demultiplexer circuit.
[0043] Figure 2 shows a block diagram of Control Centre Processing Unit (CCPU) and console according to an exemplary implementation of the present disclosure/invention.
[0044] The figure shows the block diagram of Control Centre Processing Unit (CCPU) interfaced with console. It is designed to accommodate two VPX (Versa-Module Euro Peripheral Component Interconnect Extent) Single Board Computer (SBC) boards and two Power Supply (PS) boards to cater for Dual Modular Redundancy (DMR). The VPX standard is selected for handling extensive data-intensive application programs, particularly for dealing with high frequency signals i.e., Digital Visual Interface (DVI), Universal Serial Bus (USB) and Ethernet in Control Centre Processing Unit (CCPU).
[0045] The mission critical application programs execute in VPX SBC for performing command and control operations. The VPX SBC is interfaced to console via motherboard, which is the backbone of CCPU. The various Input/output (I/O) interfaces of console viz., Recommended Standard 232 (RS232), USB, DVI and Ethernet are routed in motherboard to VPX SBC, which are basically high speed differential pair connections. During normal operation, motherboard connects SBC 1 to console I/O’s and SBC 2 works in hot stand by operation. On failure of SBC 1, the console I/O’s are switched to SBC 2, to provide un-interrupt command and control operations for the user on the commander console.
[0046] The main challenge is designing the motherboard for dual modular redundancy of USB 2.0 Interface. Since most of the sub-systems of console viz., Keyboard, track ball, OLED, rotary encoder etc. work with USB interface and at data rate of 480 Mbps, design consideration becomes more complex to minimize the signal integrity impairments. Hence, the design of USB switching circuit in is critical part of the invention. Here, the USB switching circuit is designed and integrated on the motherboard for selecting either of the two Intel i7 VPX SBC to the console.
[0047] The usual design for switching USB is carried out with single multiplexer, which selects USB data from either SBC1 or SBC2 based on select line input. However, failure of multiplexer results in failure of entire processing unit even though both the SBC’s are in working condition. To overcome this single point failure of switching circuit, the multiplexing scheme is designed with two stages viz., Demultiplexer in the first stage and Multiplexer in the second stage.
[0048] Figure 3 shows a schematic diagram of USB switching circuit according to an exemplary implementation of the present disclosure/invention.
[0049] The figure shows the schematic diagram of designed USB switching circuit and USB multiplexer scheme is shown in Table 1.
Table 1 is the USB MUX Selection Scheme
SEL Description

0 SBC 1 output is available at J17 and SBC 2 output is available at J9. In case of 1:2 DEMUX D2 failure, the output of SBC 1 is available at J17. In case of 2:1 MUX M1 or 1:2 DEMUX D1 failure, the SBC 2 output is available at J9.
1 SBC 2 output is available at J17 and SBC 1 output is available at J1. In case of 1:2 DEMUX D1 failure, the output of SBC 2 is available at J17. In case of 2:1 MUX M1 or 1:2 DEMUX D2 failure, the SBC 1 output is available at J1.

[0050] This scheme avoids the single point failure of switching circuit and thus fault tolerant with high reliability. For the case, when select (SEL) is '0', the SBC 1 output is available at the output of switching circuit (J17 connector) and SBC 2 output is available at the first stage (J9 connector). In case of failure of second stage multiplexer circuit, the output can still be obtained at the first stage of demultiplexer output. And also, if one of the demultiplexer fails, the output can still be obtained from other demultiplexer. A High speed signal conditioners are added at the output of each stage to compensate for Inter-symbol Interference (ISI) signal loss.
[0051] Another aspect of the invention is the compact design of air cooled chassis. In usual design of military air-cooled chassis, the circular I/O connector are fixed to chassis and routed via cables from motherboard through Rear Transition Modules (RTM). This increases the size of the unit along with junctions for the signals. In the present invention, the circular I/O connectors are embedded on the motherboard itself, which avoids cables and minimise junctions. This makes design very compact and more reliable.
[0052] Figure 4 shows a layout of motherboard according to an exemplary implementation of the present disclosure/invention.
[0053] The figure shows a layout of motherboard. The VPX backplane is shown in Fig. 4. This design methodology is very useful in handling high frequency signals where multiple junctions can create interference and may result in signal loss also.
[0054] The figure 5 shows an eye diagram of USB and the figure 6 shows a GA views of Control Centre Processing Unit (CCPU).
[0055] In case of high speed signals, the signal integrity is a major concern. At most basic level, the signal integrity ensures that a signal is moved from “Point A” to “Point B” with sufficient quality or integrity to allow effective communication. The common method for signal integrity evaluation is using eye pattern. The eye patterns are a time domain characterization of system level performance which indicates the combined effects of channel noise and inter-symbol interference. With Eye patterns, the signal rise time, fall time, undershoot, overshoot, jitter, line capacitance and bandwidth effects of data transmission are evaluated. The eye diagrams of USB is shown in Fig 5. The larger the eye the better the data signal integrity. The acceptable signal quality are defined with eye mask and also overlapped in Fig 5.
[0056] The design of motherboard provides redundancy with two processors and the redundancy circuit viz., switching circuit itself is designed with redundancy feature. This ensures the design is highly fault tolerant and meets the critical mission requirement of military applications. Also, the system is made compact by embedding MIL circular connectors on-board which avoids additional wiring as well as space.
[0057] Figures are merely representational and are not drawn to scale. Certain portions thereof may be exaggerated, while others may be minimized. Figures illustrate various embodiments of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.
[0058] In the foregoing detailed description of embodiments of the invention, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description of embodiments of the invention, with each claim standing on its own as a separate embodiment.
[0059] It is understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively.

,CLAIMS:

1. A fault tolerant system for a Control Centre Processing Unit (CCPU) of a defense system, the system comprising:
a motherboard and a console, the motherboard comprising:
at least two Single Board Computer (SBC) configured to perform a control operations of the Control Centre Processing Unit (CCPU) which provides a real time air situation picture to commander on the commander console to perform effective command and control operations, wherein during operation the motherboard connects first SBC to console I/O’s and second SBC works in hot stand by operation;
at least one USB switching circuit configured and integrated to the motherboard for selecting and switching either of the two Single Board Computer (SBC) to the console I/O’s;
at least one USB multiplexer configured to receive signals from the USB switching circuit for multiplexing;
at least one high speed signal conditioner configured at output of each stage to compensate for Inter-symbol Interference (ISI) signal loss; and
at least two Power Supply (PS) configured to supply power to each Single Board Computer (SBC).

2. The system as claimed in claim 1, wherein the motherboard interfaces the Single Board Computer’s (SBC’s) with console Input/output devices.

3. The system as claimed in claim 1, wherein the console comprises plurality of Input/output devices configured to provide an air situation picture and combat control operations to the commander.

4. The system as claimed in claim 1, wherein in case of failure of one of the Single Board Computer (SBC), the motherboard connects another Single Board Computer (SBC) to perform un-interrupt command and control operations for an user on the commander console, thus the system is highly fault tolerant and meets the critical mission requirement.

5. The system as claimed in claim 1, wherein the system is configured with two stages of multiplexing scheme, where first stage comprises demultiplexing with demultiplexer circuit and second stage comprises multiplexing with multiplexer circuit.

6. The system as claimed in claim 1, wherein the switching circuit further comprises at least two demultiplexer, wherein during an operation, an SBC 1 output is available at the output of switching circuit (J17 connector) and SBC 2 output is available at the first stage (J9 connector), wherein during another operation, an SBC 2 output is available at the output of switching circuit (J17 connector) and SBC 1 output is available at the first stage (J1 connector).

7. The system as claimed in claim 1, wherein in case of failure of second stage multiplexer circuit, the output is obtained at the first stage of demultiplexer output.

8. The system as claimed in claim 1, wherein in case of failure of one of the demultiplexer of the first stage demultiplexer circuit, the output is available at another demultiplexer of the first stage demultiplexer circuit.

9. The system as claimed in claim 1, further comprising a MIL-GRADE circular I/O connector are fixed directly on the motherboard, which avoids cables and minimize junctions.

10. The system as claimed in claim 1, wherein the system avoids the single point failure of switching circuit and thus fault tolerant with high reliability.