An Field Programmable Gate Array (Fpga) Based Data Decipher Device For Extracting Data From Pulse Duration Modulated Signals From Field Networks With Parallel Data Conversion, And Switching Data By Selecting The Optimum Bus Line With Acknowledgements For Every Data Element

Abstract: The invention relates to an Field Programmable Gate Array (FPGA) based data decipher device for extracting data from pulse duration modulated signals from field networks with parallel data conversion, and switching data by selecting the optimum bus line with acknowledgements for every data element, comprising; a FPGA module (1) transmitting and receiving pulse duration modulated signals for extracting data corresponding to the origin and content of the data, the FPGA module (1) producing multiple signals indicative of availability including error status or received data, and provided with redundant paths for data transfers to ensure maximum connectivity with field elements; a signal processing module (2) consisting of logic gates, discrete timers, and storage elements for producing static memory signals for transfer of data to a dual port memory block (3), the signal processing module (2) having selection jumpers and switches to allow detection of connectivity between the external modules and the FPGA module (1) including identification of the said external modules; the dual port memory block (3) acting as a data server and connected to a processing and communication module (4) to perform the bulk data transfer via Ethernet protocol to a presentation module (HMI); and the processing and communication module (4) includes a microcontroller with its address data bus interfaced to the dual port memory and incorporates at least two serial communication channels, the module (4) having a supervision and configuration circuit (5) to continuously monitor processor activities.

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