AN IMPROVED ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICE
Field of Invention:
This invention relates to an improved programmable logic device architecture, and more particularly to an improved Field Programmable Gate Array (FPGA) architecture that provides more efficient utilization of resources by enabling access to circuit elements in the domain of one Programmable Logic Block (PLB) from other PLBs.
Background:
Field Programmable Gate Arrays (FPGAs) are general-purpose logic devices that can be configured to provide any desired logic function within the range of capabilities of the FPGA. Each FPGA comprises internally of one or more Programmable Logic Blocks (PLBs) that can be interconnected at their outputs and inputs through a programmable interconnection matrix. Each PLB is composed of logic circuit elements that can be programmed to interconnect in one of several possible ways. The range of capabilities provided by each PLB is defined by the set of logic circuit elements available. A PLB is incapable of providing functionality that requires any additional logic circuit elements.
In several applications, logic circuit elements in some PLBs remain unutilized or underutilized while other PLBs are limited by the availability of insufficient quantities
of logic circuit elements. This situation results in inefficient utilization of the FPGAs

resources. In these conditions it would prove beneficial if the unutilized logic circuit elements in one PLB could be utilized by other PLBs. Current FPGA architectures do not provide any means to permit the sharing of logic circuit elements between PLBs. This limitation is particularly applicable to sequential logic elements.
US Patent 5,883,525 describes an FPGA architecture that provides an arrangement for reducing the chip area of an FPGA by minimizing the programmable interconnection points in the programmable routing matrix. However, this invention does not provide any mechanism for enabling access to internal logic elements of a PLB.
The object of this invention is to overcome the above-mentioned drawbacks and provide an FPGA architecture that enables more efficient utilization of logic circuit elements.
To achieve the said objective, the invention provides:
An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a routing means that selectively connects the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.
Said routing means is a controlled gate structure that selectively enables the input or output of the circuit element to the interconnect matrix, based on the value of a selection input.

Said routing means provides bi-directional access to the input or output of atleast some defined circuit elements.
The defined circuit elements are combinatorial or sequential logic elements or combinations thereof.
Atleast one of the defined logic circuit elements is a sequential logic circuit element.
A method for improving the utilization of FPGA resources by enabling access to defined logic circuit elements in the domain of any PLB by selectively connecting the input or output of any such logic circuit element to the common interconnect matrix connecting all the PLBs together.
Selective connection is accomplished by connecting a particular input or output of the logic circuit element to the interconnect matrix, based on the value of a selection input.
The selective connection provides bi-directional access.

The invention will now be explained with the help of the accompanying drawings:
Fig.-l is the top level diagram of an FPGA according to the conventional
architecture, showing the "tiled" structure.
Fig-2 shows the internal structure of a "tile" in the conventional FPGA. Fig-3 shows the arrangement for interconnecting the "tiles" in a conventional
FPGA. Fig-4 shows the block diagram of a Programmable Logic Block (PLB) in a
conventional FPGA. Fig-5 shows a modification of the PLB to provide access to the sequential logic
elements from outside the PLB.
Fig-6 shows the diagram of an interconnecting circuit block.
Fig-7 shows the internal circuit diagram of a conventional interconnecting Circuit
Block, Fig-8 shows the circuit diagram of an interconnecting Circuit Block modified
according to this invention. Fig-9 shows the circuit diagram of a modified interconnecting Circuit Block that
provides bi-directional access to the sequential logic circuit elements in the
PLB.
As shown in Fig-1, an FPGA 20 generally consists of an array of Tiles 25 that collectively provide configurable logic circuit element resources. The Tiles are
programmatically interconnected to provide the desired set of functions using the resources available in one or more Tiles.

Fig-2 shows the internal structure of a Tile 25. Each Tile is made up of a programmable logic block (PLB) 30 and routing resources 35 that connect its input and output signals with other PLBs. A PLB 30 is also termed a configurable logic Block (CLB), a configurable Logic Element (CLE) or a Programmable Function Unit (PFU) i.e. any circuitry in which logic can be implemented, in programmable logic devices.
The interconnection between Tiles in existing FPGA architectures is shown in Fig-3. A PLB 30 in one Tile is connected with PLBs in other Tiles using routing resources in the form of a Connection Block 40 and a Switching Block 41. The Connection Block 40 provides the facility to select one or more PLB outputs and/or inputs for connecting to one or more PLBs. Each output from a Connection Block 40 is connected to a programmable Switching Block 41 that enables a circuit connection to the Output/input of one or more selected PLBs.
Fig-4 shows the internal structure of a conventional PLB. Each PLB 30 often includes one or more input lines, one or more output lines, one or more latches and one or more Look Up Tables (LUT) 50 with sequential logic 51 such as a D flip flop. The LUT 50 can be programmed to perform various functions including general combinatorial or control logic functions, read only memory (ROM) or RAM operations or to function as a data path between the input and output lines. In this manner, the LUT 50 determines whether
the PLB 30 performs general logic, or operates in a special mode such as an adder, a subtracter, a counter, a register or a memory cell and thereby whether or not it utilizes a sequential logic element 51. The sequential logic elements 51 may be used as registering elements within the same programmable logic block (PLB) 30. However, these sequential logic elements 51 cannot be used to register functions from other PLBs.

Fig-5 shows a modified PLB that incorporates the facility to utilize the sequential logic elements of one PLB to register functions from other PLBs. Additional input pins C 45 connect to desired outputs of other PLBs and provide access to the input of the sequential logic elements 51. Unregistered output O 48 is simultaneously available with the registered output Q 47. However, this approach requires additional dedicated pins, 45 and 47 which reduces the pins to functionality ratio of programmable logic block 30. These additional inputs and outputs also increase the routing resources, which results in increased silicon area and additional delays.
Fig 6 shows a programmable routing matrix 41 with the capability to connect a signal Al 62 with m points A2-Am 65. Each connection is individually programmable and it is therefore possible to select as many connections as desired.
Fig 7 shows a schematic of the routing matrix 41. Signal Al 62 can be connected to any (or all) other points A2-Am 65 by programming the control lines P2-Pm 66 to control the gates 67. If, for example, a connection is desired from Al 62 to A3 65-3 and Am 65-m, then programmable control lines P2 66-3 & Pm 66-m are gated high to turn-on gates 67-3
and 67-ra respectively while the remaining control lines remain low and turn-off the
remaining gates. Similarly, reversible connections are also possible because of the bidirectional capability of structure 41. To connect A2 65-2 with Al 62, programmable elements turn P2 66-2 high so as to turn-on gate 67-2 while the remaining control lines P3 to Pm remain low to keep gates 67-3 to 67-m turned-off.

Fig 8 shows the schematic of programmable routing matrix 71 according to the present invention. In this arrangement the connections to the sequential logic elements are provided with the help of the routing resources instead of the selection circuitry in the programmable logic block 30. Signal Al 72 can make a connection with any (or all) other points A2-Am 75 in two different modes - direct mode or registered-mode. In direct mode, the programming element turns Tl 78 low to turn-on gate 79-p and to turn-off gate 79-n to pass the signal from Al 72 to node M 80 directly without registering it in flip flop 74. In registered-mode, the programming element turns Tl 78 high to turn-off gate 79-p and to turn-on gate 79-n to pass the signal from Al 72 to node M 80 through flip flop 74. Since gates 79-p and 79-n are complementary in nature and are controlled by a single control line Tl 78 only one gate, either 79-p or 79-n is switched-on at any time to provide either direct or registered mode operation. Node M 80 can connect to any point A2 -Am 75 by programming control of lines P2-Pm 76 to control the status of gates 77. To connect signal Al 72 to point A2 75-2, programming elements turn control line P2 76-2 high to turn-on gate 77-2 while the remaining control lines A3-Am are kept low to turn-off the remaining gates 77-3 to 77-m. Gate 77-2 connects node M 80 to A2 75-2 and hence Al 72 to A2 75-2 either in direct mode or registered mode depending on the status of control line T1 78. In this case, bi-directional connectivity is not possible in registered
mode. In direct mode, which is activated by setting T1 78 low, signal A2 75-2 connects with Al 72 using gate 77-2 and gate 79-p which are bi-directional elements and hence provide bi-directional connecting. For registered mode, the uni-directional routing structure 71 can be converted bi-directional by providing a flip flop 74 at every node (Al to An) — in other words by registering the data at A2 node and then connecting to Al. However this requirement is relatively expensive in terms of chip area.

Fig 9 shows an embodiment of present invention that provides bi-directional connectivity in both registered and direct modes. In this structure 81, there is an addition of gate pair 92 to select the direction of the signal. This type of structure has four different modes for connecting the signals — Al 82 to A2 85-2 direct mode, Al 82 to A2 85-2 registered mode, A2 85-2 to A1 82 direct mode and A2 85-2 to Al 82 registered mode. In A1 82 to A2 85-2 direct mode, programming elements turn T2 91 and T1 88 low and hence gates 92-p and 89-p are on to connect Al 82 directly to node M 90. Gates 92-n and 89-n are switched off. To connect node M 90 to point A2 85-2, programming elements turn control line P2 86-2 high to turn on gate 87-2 while the remaining control lines remain low to switch off gates 87-3 to 87-m. In the same configuration, signal A2 85-2 is able to drive point Al 82, and hence connect A2 85-2 to Al 82 in direct mode. In Al 82 to A2 85-2 registered mode, programming elements turn control line T2 91 low to switch on gate 92-p and T1 88 high to switch on gate 89-n. In this configuration, gates 92-n and 89-p remain off. Gates 92-p and 89-n provide the signal Al 82 at node M 90 through flip-flop 74. To connect this registered signal at node M 90 with point A2 85-2, programming elements turn control line P2 86-2 high to turn on gate 87-2 while the remaining control
lines remain low to switch off gates 87-3 to 87-m. For reversed connection from A2 85-2 to Al 82 in registered mode, programming elements turn T2 91 high to switch on gate 92-n & T1 88 low to switch on gate 89-p. In this configuration, because of T2 91 being high and T1 88 low, gates 92-p and 89-n remain off. To connect A2 85-2 to node M 90, programming elements turn control line P2 86-2 high to turn on gate 87-2 while the remaining control lines remain low to switch off gates 87-3 to 87-m. Gate 89-p connects node M 90 to the input of the flip flop 84 and gate 92-n connects flip flop 84 output to AI 82, and hence provide connectivity from A2 85-2 to Al 82 through flip flop 84. In this manner, this structure provides a programmable bi-directional routing connectivity in both registered and direct modes. Since each PLB is surrounded by this type of routing structure the sequential elements can be provided in the routing structure instead of in the PLB. This routing resources 81 provides a group or bank of flip-flops 84 which are accessible to all PLBs. Therefore, this architecture increases the utilization of unused resources (flip flops) by providing accessibility to all parts of the FPGA.

We Claim:
1. An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.
2. An improved Programmable Logic Device architecture as claimed in claim 1 wherein said connecting means is a controlled gate structure that selectively enables the input or output of the circuit element to the interconnect matrix, based on the value of a selection input.
3. An improved Programmable Logic Device architecture as claimed in claim 1 wherein said selecting means provides bi-directional access to the input or output of atleast some defined circuit elements.
4. An improved Programmable Logic Device architecture as claimed in claim 1 wherein the defined circuit elements are combinatorial or sequential logic elements or combinations thereof.

5. An improved Programmable Logic Device architecture as claimed in claim 1
wherein atleast one of the defined logic circuit elements is a sequential logic circuit
element.
6. A method for improving the utilization of Programmable Logic Device resources
by enabling access to defined logic circuit elements in the domain of any PLB by
selectively connecting the input or output of any such logic circuit element to the
common interconnect matrix connecting all the PLBs together.
7. A method as claimed in claim 6 wherein selective connection is accomplished by
connecting a particular input or output of the logic circuit element to the
interconnect matrix, based on the value of a selection input.
8. A method as claimed in claim 6 wherein the selective connection provides bi
directional access.
9. An improved Programmable Logic Device architecture substantially as herein
described with reference to the accompanying drawings.
10. A method for improving the utilization of Programmable Logic Device resources
substantially as herein described with reference to the accompanying drawings.