AN IMPROVED FRAME RATE CONVERTER AND A METHOD FOR
OBTAINING THE SAME
Field of the invention
[0001] The invention generally relates to signal processing. More particularly, embodiments of the invention relates to an improved frame rate converter and a method for displaying Super Video Graphics Array (SVGA) signals on high resolution monitors without motion discontinuities.
Prior Art [0002] Screen displays on monitors such as patient monitors are normally of SVGA format. The signals are progressively scanned and have frame rates typically in the range of 25 to 30Hz. Ultrasound systems, movie cameras are other examples of devices operating at low frame rate. When the output signals of such monitors are to be connected to higher display monitors such as a television and/or LCD monitors, a mismatch occurs due to incompatibility of the frame rates. This results in motion discontinuities leading to misrepresentation of the patient data. The frame rate incompatibility is also a problem if the data stored in one patient monitoring system has to be displayed on another patient monitoring system with an advanced display monitor.
[0003] There are methods known in the prior art to convert progressively-scanned computer graphics for example VGA and SVGA signals to interlaced National Television System Committee's (NTSC) and Phase Alternation Line (PAL) television signal form for display on a conventional television set. There is a need for a frame rate converter that is capable of displaying lower frame rates without motion discontinuities on a high resolution display monitor. There is also a need for a frame rate converter that performs real time conversion of lower frame rate to higher frame rate. Further, there is also a need for a frame rate converter that is capable of converting frame rates in various output formats. Also there is a need for a method for converting lower frame rates to higher frame rates for efficient display on high resolution monitors.

OBJECT OF THE INVENTION
[0004] It is an object of the invention to provide an improved frame rate converter
capable of displaying lower frame rate output without motion discontinuities on a
high resolution display monitor.
[0005] It is another object of the invention to provide a real time frame rate
converter capable of converting lower frame rates to higher frame rates.
[0006] It is a further object of the invention to provide a frame rate converter
capable of handling various input formats with lower frame rates and converting
them into various output formats with higher frame rates.
[0007] It is also an object of the invention to provide a method for converting
lower frame rates to higher frame rates for efficient display on high resolution
monitors.
BRIEF DESCRIPTION OF THE DRAWINGS [0008] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to various embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. [0009] FIG. 1 represents a block diagram of the apparatus used for achieving the frame rate conversion.
[0010] Figure 2 represents the HSYNC figure-2A and VSYNC figure"2B data for SVGA format at 62.5 out put frame rate recorded during frame rate conversion. [0011 ] Figure 3 reprsents the SYNC signal timings for SVGA output
DETAILED DESCRIPTION OF INVENTION [0012] Various embodiments of the invention provide an improved frame rate converter capable of converting low frame rate inputs into outputs with higher frame rate. The invention also provides a frame rate converter that enables real time display without motion discontinuities. The method of conversion of frame rate shall be described in detail herein as examples of the invention.

[0013] The block diagram of figure 1 shows the operation of the invention. The Digital RGB (8, 8, 8) data given is read and stored in the memory by the Field Programmable Gate Array (FPGA). If digital RGB is not directly available then the analog RGB can convert to Digital with the help of a suitable Analog to Digital Converter (ADC). The FPGA is programmed to read the memory at a rate at least twice the rate at which it writes to the memory to double the frame rate. The converted digital RGB data is converted again to analog by a suitable Digital to Analog converter (DAC), so that the data is compatible for external LCD, CRT displays.
[0014] I2C controller is used to configure video ADC. The ADC registers are suitably configured through I2C lines with FPGA acting as master and ADC as slave. ADC has inbuilt Phase Locked Loop (PLL) and generates the video composite signals, which are then acquired by FPGA. Input sync generator module takes care of generating blank and other sync signals depending upon the incoming VSYNC and HSYNC signals. Pixel clock obtained from ADC is taken as the reference clock to generate all the sync signals corresponding to input frame rate. [0015] Input Dual Port RAM (DPRAM) within the FPGA is utilized for proper flow of data into DDR2. Each time, single line information is filled into DPRAM in accordance with input blank. DDR2 Controller makes an interface between frame buffer logic and DDR2 memory access. All major timing requirements for this high speed memory is taken care by the controller. The logic of writing into memory and reading at double speed is interfaced to controller and controller manages all the memory read-write operations generating suitable memory timings.
[0016] Output DPRAM module within FPGA is employed for proper streaming of data between DDR2 memory and display. Line by line information is filled into DPRAM. Then the data is fed to DAC and corresponding HSYNC and VSYNC signals are given to display. The HSYNC data are represented in table 2A of Figure 2 and the corresponding VSYNC data are represented in table 2B of Figure 2, according to an example of the invention.

[0017] Figure 3 represents timing diagram of the above mentioned SYNC signal data. Given an example R-Data line, the line data represented as Analog data, Sync, Back porch. Front porch timings are shown corresponding to HS YNC signal. Also VSYNC timings are shown with respect to HSYNC signal, [0018] The prior method for any video display was to use a video controller along with the processor. The processor writes the data into frame memory and the video controller is used to generate appropriate video signal timings. Video controller is used to read the video data from frame memory generating the required frame rate. In the current design FPGA replaces the functionality of both processor and the video controller. The data acquisition is done by the FPGA and put into the frame memory. The data acquisition is taken care by producing the input sync signal timings corresponding to the input frame rate. The data in the frame memory is read through FPGA and required output frame rate is produced by generating corresponding sync signal timings. Since acquisition part of the design is done by FPGA itself, the burden on the processor has been reduced. [0019] In an example of the invention, the SVGA RGB input data 30 frames per second is read by the FPGA and stored in the frame buffer memory. The Digital data is decoded properly from the RGB signal lines neglecting the Back porch and Front porch period. The memory size for converting the frame rate is a single-frame memory. The Digital data is read with a double rate so that 60 frames per second is achieved and properly encoded with Front porch and Back porch. The HSYNC and VSYNC corresponding to the read data is generated without mismatches. The Digital SVGA RGB is converted to Analog using a Digital to Analog Converter to enable output data with the converted frame rate, to be displayed without motion discontinuities on high resolution monitors such as commercially available LCD and CRT displays.
[0020] The video A/D converter is configured by FPGA using I2C lines for generating 24-bit RGB signals. The ADC further provides input HSYNC, VSYNC and pixel clock data to FPGA. Depending on the blank signal, the actual data is written into internal DPRAM. The blank signal also enables sending of the complete line information to external RAM. Hence, FPGA loads frame memory

line by line of the video. Further, line wise information read from the frame memory and written into one more internal DPRAM. The timings corresponding to output frame rate is generated by the FPGA. Sync signals along with pixel clock and 24-bit RGB data is fed to video D/A converter. Thus, the FPGA advantageously utilizes the configuration described in detail earlier herein to efficiently convert a slow frame rate into a faster frame rate and enables real time display of data on high resolution monitors.
[0021] In an alternate embodiment of the invention the method described in detail herein earlier and the apparatus employed can be advantageously utilized to convert lower input frame rates into output frame rates of 90Hz. The SVGA RGB input data at a rate of 30 frames per second is read by the FPGA and stored in the frame buffer memory. The Digital data is then decoded from the RGB signal lines neglecting the Back porch and Front porch period. The memory utilized for storing the input data is a single-frame memory. The Digital data is read with a rate three times the rate at which it is written to the memory so that a desired output of 90 frames per second is achieved and properly encoded with Front porch and Back porch. The HSYNC and VSYNC corresponding to the read data is generated without mismatches. The Digital SVGA RGB is converted to Analog using a Digital to Analog Converter to enable output data with the converted frame rate, to be displayed without motion discontinuities on high resolution monitors such as commercially available LCD and CRT displays.
[0022] The video A/D converter is configured by FPGA using I2C lines for generating 24-bit RGB signals. The ADC further provides input HSYNC, VSYNC and pixel clock data to FPGA. Depending on the blank signal, the actual data is written into internal DPRAM. The blank signal also enables sending of the complete line information to external RAM. Hence, FPGA loads frame memory line by line of the video. Further, line wise information read from the frame memory and written into one more internal DPRAM. The timings corresponding to output frame rate is generated by the FPGA. Sync signals along with pixel clock and 24-bit RGB data is fed to video D/A converter.

[0023] The invention as described in detail herein and as illustrated by drawings provides an improved frame rate converter. The invention provides a method for converting an input data with a slow frame rate to an ouput data with a higher frame rate to enable correct display of data on high resolution monitors. [0024] The foregoing description of the invention has been set for merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof

We claim:
1. An improved frame rate converter comprising
means for reading input signals at the monitor's frame rate, means for generating a succession of progressively scanned frames wherein each frame is repeated at least twice in succession, means for storing at least two progressively scanned frames, and means for writing said progressively scanned frames into said means for storing at the frame rate of said progressively scanned frames.
2. An improved frame rate converter of claim 1, wherein said means for
reading input signals at monitor's frame rate comprises
means for receiving said input signal at a frame rate of at least
30Hz,
means for converting said input signal to a digital signal, and
means for storing said digital signal into a frame buffer memory.
3. An improved frame rate converter of claim 1, wherein means for generating
a succession of progressively scanned video frames comprises
means for writing the data into frame memory,
means for generating appropriate video signal timings, and
means for utilizing said signal timings to obtain a frame rate of least
twice the rate at which the frame rate is read.
4. An improved frame rate converter of claim 1, wherein said means for storing said frames is a video frame buffer memory.
5. A method for frame rate conversion comprising
reading input signals at the monitor's frame rate,
generating a succession of progressively scanned frames wherein
each frame is repeated at least twice in succession,
storing at least two progressively scanned frames, and
writing said progressively scanned frames into said means for
storing at the frame rate of said progressively scanned frames.

6. A method of claim 5, wherein said reading input signals at the monitor's
frame rate comprises converting the analog signal to a digital signal, and
reading each frame successively.
7. A method of claim 5, wherein said generating a succession of progressively
scanned frames comprises of
writing the input frame data into frame memory,
generating video signal timings hsync and/or vsync from the input
frame data to facilitate rapid reading and writing of input frame
data, and
utilizing said signal timings to obtain a frame rate of least twice the
rate at which the frame rate is read.
8. An improved frame converter of claim 5, further wherein said storing
9. An improved frame converter obtained by the method as claimed in claims
5 -7. means for storing input frame on a single high speed frame memory.