1. Title of the invention

An Improved Method of Scheduling Aperiodic Mill 553 messages

2. Field of the Invention

The present invention relates to databus communication between various onboard Avionics systems. In particular, it relates to a method of scheduling MN1553B aperiodic messages for the exchange of data and information by the Bus Controller with the other Remote terminals.

3. Prior art and Draw backs of prior art

MIL-STD-1553 is a military standard interface used to provide a protocol for the exchange of data between various Line Replaceable Units (LRUs) or systems in an aircraft. The Mill553 protocol allows scheduling of periodic and aperiodic messages. Aperiodic 1553 messages are inserted by bus controller into a regular message frame sequence for one-time execution. These aperioidic messages transact as soon as the Bus Controller transmits them. In conventional designs, the Bus Controller (BC) inserts these aperiodic messages before or after the periodic messages thus utilizes the unused time space of minor cycle. If no time is available in a regular minor cycle, then aperiodic messages are lost or bus controller waits till free time space is available. The process of waiting for free time is not suitable when the aperiodic messages need to be scheduled frequently. Sometimes the aperiodic messages need to be executed every 20 ms or 40 ms etc for a short period of time. In such cases, aperiodic messages are lost as these messages are overwritten new set of aperiodic messages if Mill 553 bus is busy with execution of periodic messages.

4. Aim of the Invention

The main objective of this invention is to provide an improved method of scheduling frequent aperiodic messages by inventing method which stores the messages in specific memory buffers and executes these messages when bus controller is free hence avoids any loss of data during aperiodic message scheduling.

5. Summary of the invention:

This method involves handling of aperiodic messages sent by the remote terminal and scheduling of aperioidic messages by bus controller. The Avionics system architecture consisting of remote terminals and bus controller on Mill553 bus is shown in figure 1. The figure 2 shows the architecture of processor module and the Mill553 bus controller module which communicates with each other through PCI bus for aperiodic messages storage and retrieval. In this method, the module [1] as shown in figure 2 receives the request for scheduling different aperiodic messages within a minor cycle and prepares a list of these messages according to the sequence in which it is received. To stores these messages, the local memory area [2] are divided into four or more partitions based on the bus load handled by the bus controller. The module [1] stores the list of aperiodic messages received every cycle into one of the local memory partitions [2} cyclically. The module [1] then writes the messages into the bus controller memory by reading the memory partitions one by one keeping track of the previous list copied and executed. The module[1] periodically tests the status of completion of execution of any previous list of aperiodic messages list. The module [1] maintains the track of the previously accessed memory partition and the next memory partition to be accessed. Hence by this method of aperiodic message scheduling, no loss of message takes place.

6. Detailed description of the invention:

In this method, the processor module 1 shown in figure 2 receives the list of different aperiodic messages from the external system based on pilot operations. The local memory [2] shown in figure 2 is divided into four parts. The number of buffers or memory partitions depends on the average message load per minor cycle. In this case four memory buffers are chosen assuming that minor cycle is 20 milliseconds and worst case delay in handling the aperiodic messages is 60 milliseconds. The number of memory buffer stages can increase if the aperiodic messages handling period are more than 60 milliseconds. So, four memory buffers are chosen so that by the time memory buffer is overwritten by new message list, previously stored messages are transacted on the bus. It is assumed that aperioidic messages arrive at the rate of 20 milli seconds for some period of time. In steps 100 & 101, the processor module 1 (figure 2) checks for any aperiodic messages from external system. If a message exists, then module 1 copies the messages in any of the free partition cyclically as shown in steps 102 to 109 . If partition 4 is not free, the partition 1 messages are overwritten. Here, the assumption is that partition 1 previous messages are scheduled by the time module 1 overwrites it.

As shown in figure 4, in step 110 the processor module gets the bus controller status and in step 111 checks for readiness of the bus controller for scheduling the aperioidic messages. In steps 112, the module 1, checks whether partition 1 messages are copied and if partition 1 messages are not copied, then it copies the partition 1 messages into bus controller memory. In steps 113 to 119, module 1 carries out the copying of messages into bus controller memory as shown in figure 4. In every minor cycle, the processor module keeps track of the partition state from which messages are copied. 7.

Brief description of the drawings:

Fig-1: Bus Controller and Remote Terminal Architecture on Mill 553 (Dual Bus) shows the arrangement of different remote terminal and bus controller.

Fig-2: Architecture For Aperioidic Message Scheduling, shows aperiodic message storage into local memory and interaction of bus controller module with processor module.

Fig-3: Method of Storage of Aperiodic Messages into Local Memory.

Fig-4: Method of Storage of Aperiodic Messages into Bus Controller Memory.

CLAIMS

We Claim

1. Method of scheduling aperiodic messages which consists of storage of aperioidic messages into cyclic memory buffer of local memory and scheduling of messages from the bus controller memory.

2. Method of accessing aperiodic messages from local memory of claim 1 which consists of storage of the messages in cyclic buffer and retrieval of the messages cyclically from the memory buffers.

3. Method of scheduling aperiodic messages of claim 1 which consists of copying messages from local memory buffers into bus controller memory cyclically and scheduling them when bus controller is ready.