Field of the Invention
This invention relates to an improved pass gate multiplexer, particularly to detection of stuck-at faults in high performance structures like pass gate multiplexers.
Background of the invention:
Automatic Test Pattern Generation (ATPG) is an effective way to automatically test electronic circuits including integrated circuits. For testing of digital circuits, the process commonly employs a "stuck-at fault" model to emulate physical defects that may occur during fabrication of integrated circuit. Such models represent stuck-at defects as nodes or pins within the circuit that are continually held (i.e. "stuck") at a single logic value, either a 0 or a 1. Each pin in the circuit is individually subjected to a single stuck-at fault condition. A complete set of test vectors is applied to the integrated circuit under test and the simulation results so obtained are compared with the simulation results of an identical "good" circuit (i.e. with no injected faults). If, for any one of the test vectors, the output of the faulted circuit exhibits a "hard" difference (i.e. "1" expected buf'0" detected, or vice versa) from the output of the good circuit, then the stuck-at fault condition is detected.
Pass-gate multiplexers are a common circuit element in several integrated circuits. The usage of these multiplexers severely impacts the ATPG fault-coverage of the design. Consider a typical two input pass gate multiplexer (Figure I of the accompanying drawings). Dl, D2 are data inputs of the multiplexer. SI. & S2 are decoded selects for the pass gates. The data inputs are adequate for ATPG purposes, i.e. they are both observable and controllable. The selects however, are not controllable or observable. This will cause a drastic fall in the fault coverage for the logic in the fanin/fanout of these select lines.
To test a stuck-at 1 fault on SI, a "0" is driven on SI. Since the selects have to be fully decoded S2 will be logic 1. If there is a stuck-at I fault on SI, both transistors Tl & T2 will be on. hence there will be contention on Output O, and output will be in an "X" (unknown) state. None of the ATPG tools can observe a X or a Z (High impedance) state. The ATPG tools expects outputs to be either 0 or 1. Therefore, a stuck-at 1 fault is not testable on SI select. The same holds true for select S2. Similarly to test a stuck-at 0 on SI, a T is driven on Si. S2 will have to be logic 0. If there is a stuck-at-0 fault on SI, both transistors Tl & T2

will be switched off, hence the output will be high-Z state. Again the ATPG tools cannot identify a High-Z state. Therefore, a stuck-at "0" fault is also not testable on SI. The same holds true for select S2. Thus the selects for the pass gate multiplexers are unobservable for ATPG. This results in a severe reduction of Fault coverage.
The same explanation is true for pass gate multiplexers with any number of inputs.
To have a good fault coverage, the pass gate multiplexer is sometimes modeled, as a simple nand-nor multiplexer. Using this, the ATPG tools will give a high fault coverage figure but the vectors generated will not be able test the stuck-at faults on the selects of multiplexer and the preceding logic.
Therefore, a methodology to test these structures is very critical for silicon testing.
US patent 6,185.713 describes a method and approach for improving fault coverage of a tri-state bus holder. However, this patent does not address the specific issues pertaining to testing of pass gate multiplexers.
The object and summary of the invention
The object of this invention is to provide an improved pass gate multiplexer that is fully testable using externally generated test pattern vectors.
To achieve the said objective this invention provides an improved pass gate multiplexer comprising a decoder for selecting one out of a plurality of pass gates characterized in that it includes:
a weak pull up at the output of said multiplexer for providing a defined logic level when all the pass gates are deselected and means for enabling or disabling said decoder.
to facilitate the testing of the internal select signals using externally generated test pattern vectors.
The said means is an electronic circuit connected to said decoder for enabling or disabling its output by an external enable / disable signal.

The said weak pull-up is controllable by logic signals so that it is disabled during normal operation and enabled only during testing.
The present invention further provides a method for improving a pass gate multiplexer comprising the steps of:
providing a weak pull-up at the output of said multiplexer for obtaining a defined logic level when all the pass gates are deselected and making the internal decoder controllable by an enable/disable signal, to facilitate the testing of the internal select signals using externally generated test pattern vectors.
The controlling of said weak pull-up is such that it is disabled during normal operation and enabled only during testing.
Brief description of the drawings:
The invention will now be described with reference to the accompanying drawings.
Fig. 1 shows a two-input pass gate multiplexer, according to the prior art.
Fig. 2 shows an improved pass gate multiplexer, according to the present invention.
Fig. 3 shows Stuck-at 0 fault at SI
Fig. 4 shows Stuck-at 1 fault at SI
Detailed Description of the Invention
In the proposed invention a weak controllable pull-up is attached at the output of the multiplexer and the select decoder is replaced with a decoder with an enable. That is, if the enable is logic 0. the outputs of decoder (selects of multiplexer) will all be logic 0.
Figure 2 shows the proposed scheme: From the prior art the data input pins Dl. D2 are observable & controllable, hence are testable. This scheme makes the selects of the multiplexer also observable & controllable. To test for stuck-at 0 fault at SI. SI is driven as logic one through the decoder. Hence S2 is driven to logic 0. The Data pin Dl is also driven to 0. If there is a stuck-at 0 fault on SI, both transistors Tl & T2 will be switched off, output will be pulled up by the weak pullup to logic 1. if there is no stuck-at 0 fault on SI (i.e SI is

logic 1), transistor Tl will be switched on, and transistor T2 will be switched off. Hence Dl will be transferred to output. Thus O will be logic 0. This is understood by the existing ATPG tools.
Figure 3 illustrates the above. The same holds true for observing a logic 1 on S1. The same explanation is true for testing stuck-at 0 fault at S2.
To test for stuck-at fault 1 at S1, we drive S1 as logic 0, through the enable of the decoder. So both SI & S2 are logic 0. The Data pin Dl is again driven to 0. If there is a stuck-at fault 1 on SI, transistor Tl is ON & T2 is OFF, hence output is equal to Dl. i.e. logic 0. If there is no stuck-at fault 1 on SI, both transistors Tl & T2 are off, output will be logic 1 (due to the pull-up). Figure 4 illustrates the above. The same holds true for observing a logic 0 on SI. The above explanation is true for testing stuck-at fault 1 at S2
Thus both SI & S2 are made fully observable and controllable, hence completely testable. This results in the drastic improvement in fault-coverage of the designs using pass gate multiplexers. The same explanation is true for pass-gate multiplexers with any number of inputs. The proposed scheme is tested using Tetramax ATPG tool. There was a drastic improvement in fault coverage. In principle the proposed scheme can be used with any ATPG tool.
Since the pullup's are controllable, this solution will NOT effect Iddq measurements or power consumption. For Iddq measurements the pullups can be switched off. Hence no testability feature of the design is compromised.

WE CLAIM:
1. An improved pass gate multiplexer comprising a decoder for selecting one out of a
plurality of pass gates characterized in that it includes:
a weak pull up at the output of said multiplexer for providing a defined logic
level when all the pass gates are deselected and
means for enabling or disabling said decoder,
to facilitate the testing of the internal select signals using externally generated test pattern vectors.
2. An improved pass gate multiplexer as claimed in claim 1 wherein said means is an
electronic circuit connected to said decoder for enabling or disabling its output by an
external enable / disable signal.
3. An improved pass gate multiplexer as claimed in claim 1 wherein said weak pull-up is
controllable by logic signals so that it is disabled during normal operation and enabled
only during testing.
4. A method for improving a pass gate multiplexer comprising the steps of:
providing a weak pull-up at the output of said multiplexer for obtaining a defined logic level when all the pass gates are deselected and making the internal decoder controllable by an enable/disable signal.
to facilitate the testing of the internal select signals using externally generated test
pattern vectors.
5. A method as claimed in claim 4 wherein controlling of said weak pull-up is such that
it is disabled during normal operation and enabled only during testing.
6. An improved pass gate multiplexer substantially as herein described with reference to the accompanying drawings.

7. A method for improving a pass gate multiplexer substantially as herein described with reference to the accompanying drawings.