Field of the Invention
The instant invention relates to an improved phase locked loop circuit. More particularly the instant invention relates to correcting error condition in switched capacitor resistance based phase locked loops.
Background of the Invention
Phase locked loop (PLL) circuits are used in circuits that require high frequency clock signals. In these circuits, usually the frequency of the clock signal is a multiple of the frequency of a stable low-noise reference signal. PLL circuits are also used in application where constant tracking of the reference signal is required for the output signal.
PLLs are commonly used in transmitters and receivers for locally generating signals for these devices. These signals are commonly used for extracting the channel information at the receiver end. PLLs are also used for clock recovery in communication systems, disk drives, etc. Another common application for PLLs is found in modulation and demodulation of frequency modulated signals.
Conventional PLL circuit is illustrated in Figure-1. A conventional PLL comprises a phase frequency detector (PFD) 11 and a loop filter 12, a voltage controlled oscillator (VCO) 13 and a N Divider 14. PFD 11 device receives two inputs and generates an output which represents the phase difference between the two input signals. The input to the PLL are the external reference input RFCLK on one terminal and while other port receives the feedback from the final output of the PLL FBCLK. The output of the PFD 11 is used as the input for a loop filter 12. At this point the filtered output is fed to a dc signal which is fed to the YCO 13. The contiol input to the VCO 13 is a measure of input frequency and the output of the VCO is a locally generated periodic signal with frequency which is usually a
multiple of the input signal. A divider circuit N 14 is provided for the feedback path to produce the multiplicity of input frequency in the output.
Figure-2 describes a widely used switched capacitor resistor PLL of US6420917. PLL comprises a phase frequency detector 211 and a charge pump 212. a loop filter 22 and a voltage controlled oscillator (VCO) 24. The loop filter 22 is used for connecting the output of the phase frequency detector 211 to a VCO 24. The output of the VCO 24 is the output of the PLL circuit. This is fed back to the phase frequency detector 211 through a divider circuit. The loop filter 22 is designed to meet the stability criteria so the loop does not enter oscillatory condition. Different resistive devices are inserted into the loop filter to result stabilization of the loop. A simple resistor results in excessive background thermal noise.
United States Patent US6420917 introduces an idea for implementing the passive resistor in the PLL loop filter 22 by a switched capacitor circuit. As noted in the patent, the sampling clock of this switched capacitor resistor has to be of a frequency which is higher than the PLL loop bandwidth for the switched capacitor resistor to accurately match an equivalent passive resistor. The Patent does not talk about the wax in which this sampling clock can be generated. Further there needs to be a definite phase relationship between this sampling clock and the input clock to the PLL. This relationship is important from the point of view of locking behavior of the PLL when the PLL starts from zero initial voltages at its various internal nodes.
Further, if FBCLK leads REFCLK at a particular instant, the state of the switched capacitor circuit would not change till the rising edge of REFCLK, but the charge pump would, depending on the phase difference between FBCLK and REFCLK, remove charge from the loop filter 22. This is an erroneous condition, because after the charge has been removed from the loop filter and before the voltages in
the loop filter 22 can settle to their final values, the state of the switched capacitor circuit would change to the other configuration. Ideally, the state of the switched capacitor circuit should change first and then only should the charge be removed from the loop filter 22. If REFCLK leads FBCLK at a particular instant, there would be a finite time delay for the non - overlapping clock generator 213 to generate the required clocks for the switched capacitor resistor. But if within this delay, the charge pump 212 delivers charge pump to the loop filter 22, it would again be an erroneous condition. This is because the configuration of the switched capacitor circuit when the charge pump 212 delivers charge is the previous configuration. Ideally, the charge should be delivered to the loop filter 22 only after the new configuration of the switched capacitor circuit has been set.
Hence, there is need for a loop filter that will lead to the avoidance of the erroneous condition in the charge pump. There is also need for a circuit for generating the sampling clock in the PLL circuit.
Object and Summary of the Invention
To obviate the aforesaid drawbacks of the prior art the object of instant invention is to provide an improved phase locked loop circuit.
Another object of the invention is to provide loop filter for PLL that will lead to the avoidance of the erroneous condition in the charge pump.
Anotlier object of the invention is to provide for a circuit for generating the sampling clock in the PLL.
To achieve the aforesaid objects the instant invention provides an improved phase-locked loop circuit comprising:
a phase-frequency detector for comparing the input signal with a feedback signal;
a charge pump controlled by control outputs from said phase-frequency detector, - a switched-capacitor resistance based loop filter connected to the output of said charge pump;
a voltage controlled oscillator connected to the output of said switched-capacitor resistance based loop filter with its output providing said feedback signal; and
a sampling clock for driving said switched-capacitor resistance; wherein
delay elements are introduced between said control outputs from said phase-frequency detector and the control inputs of said charge pump;
said sampling clock includes a set of non-overlapping clocks generated by a non-overlapping clock generator; and said non-overlapping clock generator is connected to a digital logic circuit that generates an output signal whose rising edges correspond to the earlier occurring rising edge of either of said control outputs from said phase-frequency detector.
The control outputs are UP and DN signals.
The delay elements are 2-input OR gate; each said OR gate have both their inputs coupled to each said control outputs from said phase-frequency detector.
The digital logic circuit is a 2-input OR gate having its inputs connected to said control outputs from said phase-frequency detector.

Further the invention provides a method for phase locking comprising the steps of: comparing the input signal with a feedback signal; generating control outputs from a phase-frequency detector, providing control outputs to a charge pump; filtering the output of said charge pump; and
providing said feedback signal with respect to output of said filtering; wherein
delaying said control outputs from said phase-frequency detector to
said charge pump;
generating a set of non-overlapping clocks by a non-overlapping
clock generator; and
generating an output signal whose rising edges corresponds to the
earlier occurring rising edge of either of said control outputs from
said phase-frequency detector.
Brief Description of the Drawings
The present invention will now be described with the help of accompanying
drawings:
Figure 1 illustrates a block diagram of a conventional phase locked loop circuit.
Figure 2 illustrates a block diagram for a switched resistor phase locked loop circuit in accordance with US6420917
Figure 3 illustrates a block diagram for the improved phase locked loop in accordance with instant invention.
Figure 4 illustiates a block diagram for an embodiment for the improved phase locked loop in accordance with instant invention.
Detailed Description of the Invention
The current invention is an improved phase locked loop with a modified loop filter to prevent the erroneous condition in the charge pump. The instant invention also provides a sampling clock for the switched capacitor resistor circuitry of the loop filter. Figure-3 illustrates the improved PLL circuit of the instant invention. The PLL circuit comprises a phase frequency detector 31, a charge pump 33, a voltage controlled oscillator 34, switched capacitor resistor circuit for loop filter 35, non-overlapping clock generator 36, an digital logic circuit 37 and delay elements 32.
The phase frequency detector 31 receives REFCLK and FBCLK and generates control signals UP and DN pulses. To ensure that the charge pump 33 charges/discharges the loop filter 35 only after the new set of non-overlapping clocks have been generated, delay cells 32 are introduced after the UP and DN pulses. The delay cells 32 are OR gates with both their inputs coupled to the UP and DN pulses. The output of the charge pump 33 is coupled to a loop filter 35 with capacitors and the switched capacitor resistor circuitry 35. An OR gate is used with its input as UP and DN pulses and generating an output signal whose rising edges correspond to whichever of the two signals, UP or DN go high first. The clock signal from the digital logic circuit 37 is now used to generate the non -overlapping clocks for the switched capacitor resistor 35. The output of the modified loop filter 35 is coupled to the voltage controlled oscillator 34. The frequency divider in the PLL to obtain FBCLK for the phase frequency detector 31 divides the output of the voltage controlled oscillator 34. Figure-4 shows another embodiment wherein said digital logic circuit is implemented using an OR gate.
All documents cited in the description are incorporated herein by reference. The present invention is not to be limited in scope by the specific embodiments and examples, which are intended as illustrations of a number of aspects of the
invention and any embodiments which are functionally equivalent are within the scope of this invention. Those skilled in the art will know, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. These and all other equivalents are intended to be encompassed by the following claims.

We claim:
1. An improved phase-locked loop circuit comprising:
a phase-frequency detector for comparing the input signal with a feedback signal;
a charge pump controlled by control outputs from said phase-frequency detector,
a switched-capacitor resistance based loop filter connected to the output of said charge pump;
a voltage controlled oscillator connected to the output of said switched-capacitor resistance based loop filter with its output providing said feedback signal; and
a sampling clock for driving said switched-capacitor resistance; wherein
delay elements are introduced between said control outputs from
said phase-frequency detector and the control inputs of said charge
pump;
said sampling clock includes a set of non-overlapping clocks
generated by a non-overlapping clock generator; and
said non-overlapping clock generator is connected to a digital logic
circuit that generates an output signal whose rising edges correspond
to the earlier occurring rising edge of either of said control outputs
from said phase-frequency detector
An improved phase-locked loop circuitry as claimed in claim 1 wherein said control outputs are UP and DN signals.
An improved phase-locked loop circuitry as claimed in claim 1 wherein said delay elements are 2-input OR gate; each said OR gate have both their
inputs coupled to each said control outputs from said phase-frequency detector.
An improved phase-locked loop circuitry as claimed in claim 1 wherein said digital logic circuit is a 2-input OR gate having its inputs connected to said control outputs from said phase-frequency detector.
A method for phase locking comprising the steps of:
comparing the input signal with a feedback signal; generating control outputs from a phase-frequency detector, providing control outputs to a charge pump; filtering the output of said charge pump; and
providing said feedback signal with respect to output of said filtering; wherein
delaying said control outputs from said phase-frequency detector to
said charge pump;
generating a set of non-overlapping clocks by a non-overlapping
clock generator; and
generating an output signal whose rising edges corresponds to the
earlier occurring rising edge of either of said control outputs from
said phase-frequency detector.
6. An improved phase-locked loop circuit substantially as herein described with reference to and as illustrated in the accompanying drawings.
7: A method for phase locking substantially as herein described with reference to and as illustrated in the accompanying drawings.