AN IMPROVED PHASE LOCKED LOOP (PLL) ARCHITECTURE
Field of the invention
The instant invention relates to a phase locked loop and particularly to a method and device for providing voltage controlled oscillator (VCO) gain compensation across process and/or temperature variations.
Background of the invention
A voltage-controlled oscillator (VCO) is an electronic oscillator in which the oscillation frequency is controlled by a voltage input. Voltage controlled oscillators are commonly used in modem communication devices. The variation of the oscillation frequency of the VCO is linear with respect to the input voltage. The change in the output frequency relative to the change in the input control voltage signal (i.e. delta frequency /delta volt) determines the frequency gain of the VCO.
One of the common applications for a VCO is phase locked loop (PLL) circuit. A phase-locked loop is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal. PLLs are commonly used in demodulation of amplitude modulated signals and angle modulated signals. A PLL circuit generally consists of a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and an adjustable divider.
The working of a PLL is similar to a feedback system. Here, the phase of the output signal is fed back and the VCO frequency gets adjusted until it is equal to that of the input signal. The phase-frequency detector generates a voltage signal which represents the difference in phase and frequency between two signal inputs. The charge pump uses energy storage elements to convert direct current (DC) voltages into other DC voltages. The loop filter is a low-pass narrow-band filter which is used to remove jitters from the charge pump output. If the VCO needs to operate at a higher frequency, the charge pump drives current into the loop filter. But if the VCO needs to operate at a lower frequency,
the charge pump draws current from the loop filter. The loop filter output voltage is given as input to the VCO, according to which the VCO oscillates at a higher or lower frequency. The oscillator output is given as a feedback signal to the adjustable divider which is used to make the PLL's output clock a fractional multiple of the reference frequency at the input of the PLL.
These devices extensively use transistors whose properties vary according to the variations in temperature. The transistor operating characteristics get degraded at high temperatures and the frequency gain is relatively low at hot temperatures. However at cold temperatures, the VCO frequency gain is relatively high- The large frequency gain variation adversely affects the PLL performance. The transistor properties also vary due to the manufacturing variations in a process. These variations in transistor properties lead to performance degradation and unreliable behavior in the PLL.
U.S. Patent No. 5896068 describes a scheme for gain compensation in the VCO. This scheme involves making changes in the circuit of the VCO for gain compensation. However, this scheme achieves gain compensation only across temperature variations, whereas no compensation is achieved across process variations. Making changes in the circuit of VCO adversely affects the design flexibility and also degrades VCO performance as this VCO design results in more phase noise.
Object and summary of the invention
In order to obviate the above drawbacks the instant invention provides a phase locked loop (PLL) comprising:
a phase frequency detector having a first input connected to the input of the
PLL,
a controlled charge pump with an associated loop filter, having its input
connected to the output of the phase frequency detector,
a controlled oscillator,
- a frequency divider having its input connected to the output of the controlled oscillator and its output connected to the second input of said phase frequency detector, and
a compensation block having a first input connected to the output of said controlled charge pump, a second input connected to the output of said controlled oscillator, a first output connected to the control input of said controlled charge pump and a second output connected to the control input of said controlled oscillator.
Further, the present invention provides a method for compensating the effects of temperatures and process variation factors on the Gain Sensitivity of the controlled oscillator in a Phase Locked Loop (PLL) comprising the steps of:
determining the expected minimum and maximum control signal values and
corresponding controlled oscillator expected output frequencies across process
comers and operating temperature limits using accurate simulations of
controlled oscillator performance,
applying the expected minimum value of control signal to the control input of
the controlled oscillator and measuring the minimum controlled oscillator
output frequency obtained,
applying the expected maximum value of the control signal to the control input
of the controlled oscillator and measuring the maximum controlled oscillator
output frequency obtained,
setting the gain of the charge pump to provide the required control signal levels
to adjust said measured minimum and maximum controlled oscillator output
frequencies to the expected minimum and maximum output frequencies.
An object of the present invention is to provide a method and a device for gain compensation in a signal generator for temperature and/or process variations without modifying the signal generator circuit or resulting in performance degradation.
Another object of the present invention is to provide a PLL in which gain compensation for a voltage controlled oscillator for temperature and/or process variations is achieved by modifying the charge pump current.
The present invention provides gain compensation in VCO for both temperature and process variations by modifying the charge pump current. The scheme does not involve any changes in the VCO circuit for gain compensation but rather modifies the charge pump current. This is possible because the loop bandwidth and the damping factor of the PLL.are proportional to the product of VCO gain and the charge pump current and the intention behind VCO gain compensation is to obtain constant damping factor and loop bandwidth across process and temperature corners.
Brief description of the accompanying drawings
An embodiment of the present invention is described with the help of following drawings.
Figure 1 illustrates the block diagram of a known PLL architecture.
Figure 2 illustrates the block diagram of PLL with a compensation block in accordance with the present invention.
Figure 3 is a block diagram showing in detail one of the implementations of the compensation block according to the present invention for use in a phase locked loop (PLL).
Figure 4 is an embodiment of programmable reference voltage generator in accordance with the instant invention.
Detailed description of the invention
Figure 1 shows the block diagram of the phase locked loop (PLL) architecture generally used. This comprises a phase-frequency detector (111), a charge pump (112), a loop filter (113), a controlled oscillator (114) and an adjustable divider (115). The phase-frequency detector (111) is a circuit that generates a voltage signal which represents the difference in phase and frequency between two signal inputs (116,119). The charge pump (112) is an electronic circuit that uses energy sotrage elements to convert direct current (DC) voltages into other DC voltages. The loop filter (113) removes jitters from the charge pump to smoothen the control voltage. The controlled oscillator (114) is an electronic oscillator which is controlled in oscillation frequency by a voltage or cuurent input. The oscillator output is given as a feedback signal (118) to the adjustable divider (115).The adjustable divider (115) is used to make the PLL's output clock (117) a fractional multiple of the reference frequency (116) at the input of the PLL.
Figure 2 illustrates the block diagram of PLL with a compensation block in accordance with the present invention. The compensation "block (215) is connected between the controlled oscillator (214/114) and the controlled charge pump (212). The compensation block (215) is used to calculate the charge pump current according to value/s representing actual performance of the controlled oscillator (214/114) and the typical performance of the controlled oscillator (214/114). The calculation is done in a way so that the charge pump current is modified according to the actual gain of the controlled oscillator (214/114). This is because the loop bandwidth and the damping factor of the PLL are proportional to the product of controlled oscillator gain and the charge pump current. So the arrangement provides controlled oscillator gain compensation by obtaining constant damping factor and loop bandwidth across process and temperature corners by changing the charge pump current according to controlled oscillator gain. Once the charge pump current is decided, it is used during the normal operation of the PLL.
Figure 3 is a block diagram showing in detail one of the implementations of the compensation block (215) according to the present invention for use in a phase locked
loop (PLL). The compensation block comprises a switch (311) , a digital control block (312), a counter (313), a first set of latches (314), a second set of latches (315), a subtractor (316) and a programmable reference voltage generator (317) . The programmable reference voltage generator (317) consists of a reference current source (411) and two impedances (412,413) connected in series. Here in this implementation we have taken the controlled oscillator as a voltage controlled oscillator (VCO) although any type of controlled oscillator can be used. Switch (311) receives inputs (318/217, 319, 321) from the programmable reference voltage generator (317) and a charge pump (213). The switch is used for switching between VCQNTI (319), VCONT: (321) and the charge pump output (318/217). The output (320/218) of the switch (311) is connected to the VCO (214).
Control signals required are generated by a digital control block (312). The digital control .block (312) receives inputs (328 , 329) from the latches (314,315). The switch (311) receives control signals (322) from the digital control block (312). The digital control block (312) also controls the operation of the counter (313) and the latches (314,315) . The counter (313) receives inputs from the PLL input clock (324) and the VCO (214) . Outputs of the counter (313) are coupled to first and second set of latches (314,315). The outputs (328, 329) of the latches (314, 315) are fed to the subtractor (316) and the digital control block (312). The output (330/220) of the subtractor (316) is fed back to the charge pump (212).
Figure 4 illustrates an embodiment of the programmable reference voltage generator (317) as used in the present invention. The input signal producer comprises a reference current source (411) and two impedances (412,413) connected in series. The requirement for the current reference (411) is that it should at least give a first order temperature compensated current.
In the present invention a simulator is used to find the maximum and minimum control voltages for the voltage controlled oscillator (VCO) frequency range for each combination of the process and temperature corners. Then the maximum and minimum
values of the control voltage are selected from these voltages and are termed as VCONTI and VCONT2 respectively. After the values of VCONTi and VCoNT2 are calculated, current from the current reference (411) is passed through two impedances (412,413) in series to generate the voltages VCONTI (414/319) and VCONT2 (415/321). The intermediate node between the two impedances (412,413) is tapped for control voltage VCONT2 (415/321) and output node of the reference current source is tapped for generating control voltage VCONTI (414/319) .The impedance (413) is connected to ground (416). Current in reference current source (411) may be varied to change VCONTI (414/319) and VCONT: (415/321).
When the PLL is powered up, the charge pump output (318/217) is disconnected from.the control voltage input (218/320) of the VCO (214) and Vcont-,-, (414/319) from the current reference (411) is connected to the control voltage input (218/320) of the VCO (214). The number of cycles of VCO (214) in some cycles of PLL input clock (324) are counted in binary form and stored in a first set of latches (314). After the bits have been latched, VCONTI (414/319) is disconnected from the control voltage input (218/320) of the VCO (214) and then Vcont2 (415/321) is connected to the control voltage input (218/320) of the VCO (214). The number of cycles of VCO output (325/219) in the same number of cycles of PLL input clock (324) used in case of Vcoxt (414/319) are again counted in binary form and stored in a second set of latches (315). Using a subtracter circuit (316), the two binary values are subtracted from each other to give another binary value termed Dcycle- Using simulator, the corresponding binary value is also obtained for the typical process and temperature comer of the voltage controlled oscillator for VCONTI(414/319) and VCONT2 (415/321) and is termed DICYCLE:-
The charge pump current is modified to change the current delivered to the loop filter (213) according to these bits (DCYCLI-:)- If the value of Dcycle is less than DHYCII:. this would imply that the VCO gain is lesser than the typical gain and hence more current should be delivered to the loop filter (213) to keep the bandwidth same as the bandwidth for typical process and temperature corner. If the value of Drvcle is larger than DICYCLE., the current delivered by the charge pump to the loop filter is decreased to keep the
bandwidth same as the bandwidth for typical process and temperature corner. If the value of DCYCLE is equal to DTCYCLE, then the output from the charge pump (212) should be such that the PLL has a bandwidth corresponding to the typical process and temperature corner.
After the charge pump bits (220/330) have been decided, the input control voltage (218/320) of the VCO (214) connects to the charge pump output (217/318) to start the normal operation of the PLL with modified charge pump current.
In this PLL architecture, gain compensation is achieved by modifying the charge pump current. The loop bandwidth and the damping factor of a PLL are proportional to the product of VCO gain and the charge pump current and the intention behind VCO gain compensation is to obtain constant damping factor and loop bandwidth across process and temperature comers.
One advantage of using this PLL architecture is that the VCO gain compensation is achieved for both process and temperature variations. The second advantage is that the goal is achieved without modifying the VCO circuit.
The present invention is not intended to be restricted to any particular form or arrangement, or any specific embodiment, or any specific use, disclosed herein, since the same may be modified in various particulars or relations without departing from the spirit or scope of the claimed invention hereinabove shown and described of which the apparatus or method shown is intended only for illustration and disclosure of an operative embodiment and not to show all of the various forms or modifications in which this invention might be embodied or operated.

We claim:
1. A phase locked loop (PLL) comprising:
- a phase frequency detector (211) having a first input (223) connected to the input of the PLL,
- a controlled charge pump (212) with an associated loop filter (213) . having its input connected to the output of the phase frequency detector (211),
a controlled oscillator (214),
a frequency divider (216) having its input connected to the output of the
controlled oscillator (214) and its output connected to the second input of said
phase frequency detector (211), and
a compensation block (215) having a first input connected to the output (217)
of said controlled charge pump (212) , a second input connected to the output
(219) of said controlled oscillator (214) , a first output (220) connected to-the
control input of said controlled charge pump (212) and a second output (218)
connected to the control input of said controlled oscillator (214).
2. A phased locked loop" (PLL) as claimed in claim 1, wherein said compensation block (215) comprising:
a three-way selection switch (311) having its output (320) connected to the second output (218) of said compensation block (215),
a programmable reference voltage generator (317) having a first reference voltage (319) connected to a first input of said three-way selection switch (311) and a second reference voltage (321) connected to a second input of said three-way selection switch (311),
a third input (318) of said three-way selection switch (311) connected to the first input (217) of said compensation block (215),
the selection input of said three-way selection switch (311) being connected to a first output (322) of a digital control block (312),
a gated counter (313) having a first gating input connected to the input clock (324) of the PLL, and a second gating input connected to a second output (323)
of said digital control block (312) and its count input (325) connected to said second input (219) of the compensation block (215),
a first set of latches (314) connected to the output (326) of said gated counter (313) for storing the count output when said first reference voltage (319) is enabled by said three-way selection switch (311), said first set of latches (314) being latch enabled by a third output (331) of said digital control block (312). a second set of latches (315) connected to the output (327) of said gated counter (313) for storing the count output when said second reference voltage (321) is enabled by said three-way selection switch (311), said second set of latches (315) being latch enabled by a fourth output (332) of said digital control block (312), and
a subtractor (316) receiving the output (328) of the first set of latches (314) at its first input, the output (329) of said second set of latches (315) at its second input, and having its output (330) connected to the second output (220) of said compensation block (215).
3. A phased locked loop (PLL) as claimed in claim 2 wherein said programmable
reference voltage generator (317) comprising:
a digitally controlled reference voltage generator (411) providing said first reference voltage (319) having its value defined by the output of computer simulation models covering the simulated combined effects of process variation limit conditions and operating temperature variation limit conditions, and a voltage divider (417) deriving said second reference voltage (321) from the first reference voltage (319) level.
4. A method for compensating the effects of temperatures and process variation
factors on the Gain Sensitivity of the controlled oscillator in a Phase Locked Loop
(PLL) comprising the steps of:
determining the expected minimum and maximum control signal values and corresponding controlled oscillator expected output frequencies across process
corners and operating temperature limits using accurate simulations of
controlled oscillator performance,
applying the expected minimum value of control signal to the control input of
the controlled oscillator and measuring the minimum controlled oscillator
output frequency obtained,
applying the expected maximum value of the control signal to the control input
of the controlled oscillator and measuring the maximum controlled oscillator
output frequency obtained,
setting the gain of the charge pump to provide the required control signal levels
to adjust said measured minimum and maximum controlled oscillator output
frequencies to the expected minimum and maximum output frequencies.
5. A method for compensating the effects of temperatures and process variation factors on the Gain Sensitivity of the controlled oscillator in a Phase Locked Loop (PLL) as claimed in claim 4, wherein the controlled oscillator output frequency is measured by the steps of:
enabling a counter connected to the output of the controlled oscillator during
one state of the PLL input clock, and
storing the count value in a set of latches at the transition of the PLL clock.
6. A phase locked loop (PLL) substantially as herein described with reference to and as illustrated in the accompanying drawings.
7. A method for compensating the effects of temperatures and process variation factors on the Gain Sensitivity of the controlled oscillator in a Phase Locked Loop (PLL) substantially as herein described with reference to and as illustrated in the accompanying drawings.