TECHNICAL FIELD
[001] The present disclosure relates to field of Electronics and VLSI (Very Large-
Scale Integration). More particularly, the present disclosure relates to an improved quantum-dot cellular automata (QCA) cell-based gate design for an efficient RAM cell.
BACKGROUND
[002] QCA is one of the latest candidate technologies for the nano scale computer
designing and promising technology for the replacement of the CMOS circuit in coming days. The principle logic element in QCA is majority gate; hence, efficiently constructing QCA circuits using majority gates has attracted a lot of attention. Since a majority not function forms a universal gate, majority logic can be used for implementing any logical function instead of employing
[003] Boolean logic operators. Up to now, most QCA circuits have been investigated
and designed only by means of 3-input majority gates. However, if these circuits are constructed using Five- input majority gates, they would be optimized in cell counts, area and complexity.
Faults of QCA circuits:
[004] Three major categories of faults can occur during the assembly of a QCA
circuit. First, fault may occur when quantum cells are shifted from their intended
locations which are called "misalignment" cells. Sometimes misalignment cells have no effect on functionality of a QCA circuit, and also sometimes they can cause a circuit to have an unexpected output. A second type of faults occurs when the quantum cell itself is "missing" resulting in the cell becoming defective and it would have no influence on its neighbors and it can cause a circuit to cease functioning well. A third type of faults occurs when quantum cells are rotated relative to the other cells in the array which is called "dislocation" cells. Also, in this case, the circuit may cease to function.
We limit our discussion and invention only on QCA based Five-input Majority
gate design and Basic RAM cell design.
Some basic terminology used in QCA Technology:
1. QCA technology and its working:

[005] QCA provide a novel electronics paradigm for information processing and
communication. It has been recognized as one of the revolutionary nano scale computing devices. A major advantage of QCA over other nano-electronic architectural styles is that the same cells that are used for making logic gates can be used to build wires carrying logic signals. The QCA allows operating frequencies in range of THz and device integration densities about 900 times more than the
[006] current end of CMOS scaling limits, which is not possible in current CMOS
technologies. It has been predicted as one of the future nanotechnologies in Semiconductor Industries Association^ International Roadmap for Semiconductors (ITRS). Logical operations and data movement are accomplished via Columbic interaction between neighboring QCA cells rather than current flow. The QCA design involves diverse new paradigms such as memory in-motion and processing-by-
[007] wire. Memory-in-motion is an instance of the more general paradigm of
processing-by-wire. Processing-by-wire (PBW) is the QCA capability by which information manipulation can be accomplished, while transmission and communication of signals take place. Quantum dots are nanostructures created from standard semi-conductive materials such as InAs/GaAs. These structures can be modeled as3-dimensional quantum wells. As a result, they exhibit energy
[008] quantization effects even at distances several hundred times larger than the
material system lattice constant. A quantum dot can indeed be visualized as a well. Electrons, once trapped inside the dot, do not alone possess the energy required to escape. We can use quantum physics to our advantage because the smaller a quantum dot is physically, the higher the potential energy necessary for an electron to escape.
QCA CELL:
[009] The fundamental unit in QCA circuits is a QCA cell which consists of four
quantum dots which are arranged in a square pattern. The cell is charged with two excess electrons which can be allowed to tunnel between the different quantum dots by a clocking mechanism. These electrons tend to occupy the antipodal sites as a result of their mutual electrostatic repulsion. The Coulombic repulsion is responsible for the transfer of information from one cell to an adjacent cell. This type of information flow does not involve actual electron flow and thus results in a reduction in the overall power consumption of the circuit. This feature of QCA circuits enables their usage at very high frequencies such as in RF circuitry. QCA cells conduct data from one to another and thus are simply used as wires.

In digital QCA design, the side-effects of using metal contacts such as junction capacitances, parasitic capacitances and high latency delays are all eliminated.
QCA CLOCKING:
[0010] QCA circuits have a four phase clock unlike CMOS circuits where there are
only two states "High" and "Low". All the four phases in QCA clocking have a phase shift of 90°. Power to the QCA circuit comes in the form of clock itself unlike external power supply as is the case in CMOS style. The four phases of clock correspond to "switch", "hold", "release" and "relax". In switch phase, the barriers are slowly raised and the QCA cell becomes polarized according to the state of their input driver. In the next "hold" phase, the barriers are kept high so that the cells in that sub array retain their values. During the "release" phase, the barriers are lowered and the cells are allowed to relax to an un-polarized state. In the final "relax" phase the barriers kept on low and the cells remain un-polarized.
Five-input majority gate:
[0011] A five-input majority gate must have five inputs and one output. It is a
versatile logic block in the QCA technology, which can be used effectively for designing QCA logic and arithmetic circuits and RAM cells. The functionality of the five-input majority function can be expressed according to Eq.
M (A, B, C, D, E) = ABC+ABD+ABE+ACD+ACE+ADE+BCD+BCE+BDE+CDE (1)
[0012] The five-input majority gate consists of five input cells, a voter part and an
output cell. The input cells are located adjacent to each other, they cannot be extended well.
The output cell can be placed in accordance with the designer's requirement. In the design of
Five- input gate, single layer approach or multilayer approach can be implemented.
[0013] The basic element of QCA circuit is a majority voter gate; digital operation
can be employed by using Majority voter gate. Majority voter gate characterizes and determines the function value based on majority verdict. Up to now, most QCA circuits have been investigated and designed only by means of 3-input majority gates. However, if these circuits are constructed using Five- input majority gates, they would be optimized in cell counts, area and complexity.

RAM cell:
[0014] RAM cell design is one of the most important topics for the QCA technology.
In general, for the QCA technology there are two kinds of RAM designs which are loop-based category and line- based category. The loop-based RAM structure is based on storing mechanism by means of a feed-back consisting of all four clocking zones. The line-based RAM structure saves the previous value using a QCA line.
Problems in existing Five- input majority gate designs:
[0015] 5- Input Majority gate designed has the problem of unreachability of output
cell and Input cells in a single layer described in the previous research. So these designs can be used only for multilayer structure. In existing designs, this problem is overcome but it has increased the number of QCA cells and so is the occupational area. It further causes more power dissipation due to earlier mentioned limitations.
PRIOR ART
[0016] Milad Bagherian Khosroshahy, Mohammad Hossein Moaiyeri, Keivan
Navi, Nader Bagherzadeh, "An energy and cost efficient majority-based RAM cell in
quantum-dot cellular automata", https://doi.Org/10.1016/j.rinp.2017.08.067: The present
research discloses a Five-input majority gates consisting of five input cells which are injected
with a rotated style into a voter part and subsequently the output value is calculated.
[0017] Navi K, Sayedsalehi S, Farazkish R, Azghadi MR, "Five-input majority gate,
a new device for quantum-dot cellular automata", Journal of Computational and Theoretical Nanoscience, American Scientific Publisher. 2010 Aug 1;7(8): 1546-53. The new present device reduces cell counts and area and uses conventional form of QCA cells. Furthermore, a QCA Full-Adder is constructed using the new present design. The present Full-adder circuit is designed with 2 majority gates and 2 invertors with area occupied 0.03um2
[0018] Navi K, Farazkish R, Sayedsalehi S, Azghadi MR,"A new quantum-dot
cellular automata full-adder". Microelectronics Journal. Elsevier, quantum-dot cellular automata. In NSTI Nanotech 2011 (Vol. 2, pp. 978-981): The present research article discloses a design of Five- input majority gates. Total number of cell used for designing are 10, total area occupied by cells is 0.01 um . The interference between the input cells is present and design is having multilayer majority gates.

[0019] S. Mohammadyan, S. Angizi, K. Navi, "New fully single layer QCA full-
adder cell based on feedback model", International Journal of High Performance Systems Architecture, 5 (2015) 202-208: "In the present article, by considering a new logic function, a fully single layer QCA one-bit full-adder cell presented for the first time with no need to conventional wire crossing methods".
[0020] R. Farazkish, "A new quantum-dot cellular automata fault-tolerant five-input
majority gate, Journal of nano- particle research", 16 (2014) 2259: In this paper, researcher presenting a new approach to the design of fault-tolerant Five- input majority gate by considering two-dimensional arrays of QCA cells. The fault-tolerance properties of such block five-input majority gate with respect to misalignment, missing, and dislocation cells are analyzed.
[0021] Angizi S, Sarmadi S, Sayedsalehi S, Navi K, "Design and evaluation of new
majority gate-based RAM cell in quantum-dot cellular automata". Microelectronics Journal. 2015 Jan 31;46(1):43-51.
[0022] No relevant patent/research paper was found in Indian patent database to the
best of the knowledge of the inventors. Therefore, it can be concluded from the above that in
spite of all the efforts made, the solutions have to be taken into consideration.
[0023] There is therefore a need in the art to provide an improved quantum-dot
cellular automata (QCA) cell-based gate design that overcome the above-mentioned and other limitations of the existing design and improved performance along with reducing the power consumption.
OBJECTS OF THE PRESENT DISCLOSURE
[0024] Some of the objects of the present disclosure, which at least one embodiment
herein satisfies are as listed herein below.
[0025] It is an object of the present disclosure to provide an improved quantum-dot
cellular automata (QCA) cell-based gate design.
[0026] It is another object of the present disclosure to provide an improved quantum-
dot cellular automata (QCA) cell-based gate design that utilizes less number of QCA cells for 5 input and one output.
[0027] It is another object of the present disclosure to provide an improved quantum-
dot cellular automata (QCA) cell-based gate design that uses lesser occupational area thus, lesser power dissipation.

[0028] It is another object of the present disclosure to provide an improved quantum-
dot cellular automata (QCA) cell-based gate design that provides with reachability of output cell and input cell in a single layer.
[0029] It is another object of the present disclosure to provide an improved quantum-
dot cellular automata (QCA) cell-based gate design that provides SET/RESET capabilities.
SUMMARY
[0030] The present disclosure relates to field of Electronics and VLSI (Very Large-
Scale Integration). More particularly, the present disclosure relates to an improved quantum-
dot cellular automata (QCA) cell-based gate design for an efficient RAM cell.
[0031] In an aspect, the present disclosure provides an improved quantum-dot cellular
automata (QCA) cell-based gate design for an efficient RAM cell. The QCA cell-based gate design can include: a plurality of QCA cells to provide a route to communicate data; at least one output QCA cell configured with the plurality of QCA cells; and at least five input QCA cells configured with the plurality of QCA cells, wherein arrangement of the at least one output QCA cell and the at least five input QCA cells with the plurality of QCA cell allow single as well as multilayer design of the RAM cell, and wherein the arrangement of the at least one output QCA cell, the at least five input QCA cells with the plurality of QCA cells is adapted to reduce input to output delay of the RAM cell.
[0032] In an embodiment, the QCA cell-based gate comprises: one of the at least five
input QCA cells is positioned at left extreme of RAM cell arrangement; the output QCA cell is positioned at right extreme of the RAM cell arrangement; two of the at least five input QCA cells are positioned on upper and lower extreme such that three of the plurality of QCA cells are sandwiched between them, wherein the arrangement of the two input QCA cells and three QCA cells are placed adjacent to the input QCA cell; and two of the at least five input QCA cells are positioned on upper and lower extreme such that five of the plurality of QCA cells are sandwiched between them, wherein the arrangement of the two input QCA cells and the five QCA cells are placed adjacent to the output QCA cell.
[0033] In an embodiment, the plurality of QCA are 11, the input QCA are 5 and
output QCA is 1 such that area expanded by the QCA cell-based gate design is at least .07 micrometre square.
[0034] In an embodiment, the input to output delay is reduced to at least 1.25 clocking
cycles.

[0035] In an embodiment, the RAM cell implementation of the QCA cell-based gate
design comprises at least 85 QCA cells, wherein the RAM cell comprises set and reset capability.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In the figures, similar components and/or features may have the same
reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0037] FIG. 1 illustrates an improved quantum-dot cellular automata (QCA) cell-
based gate design in accordance with an embodiment of the present disclosure.
[0038] FIG. 2 illustrates a simulation result for an improved quantum-dot cellular
automata (QCA) cell-based gate design in accordance with an embodiment of the present disclosure.
[0039] FIG. 3A illustrates a schematic representation of coplanar RAM cell with
set/reset ability in accordance with an embodiment of the present disclosure.
[0040] FIG. 3B illustrates a QCA cell implementation of coplanar RAM cell with
set/reset ability in accordance with an embodiment of the present disclosure.
[0041] FIG. 4 illustrates a simulation result for a QCA cell implementation of
coplanar RAM cell with set/reset ability in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0042] In the following description, numerous specific details are set forth in order to
provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0043] Embodiments of the present invention include various steps, which will be
described below. The steps may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, steps

may be performed by a combination of hardware, software, firmware and/or by human operators.
[0044] Various methods described herein may be practiced by combining one or more
machine-readable storage media containing the code according to the present invention with
appropriate standard computer hardware to execute the code contained therein. An apparatus
for practicing various embodiments of the present invention may involve one or more
computers (or one or more processors within a single computer) and storage systems
containing or having network access to computer program(s) coded in accordance with
various methods described herein, and the method steps of the invention could be
accomplished by modules, routines, subroutines, or subparts of a computer program product.
[0045] If the specification states a component or feature "may", "can", "could", or
"might" be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0046] As used in the description herein and throughout the claims that follow, the
meaning of "a," "an," and "the" includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.
[0047] Exemplary embodiments will now be described more fully hereinafter with
reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this invention will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).
[0048] While embodiments of the present invention have been illustrated and
described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.

[0049] The present disclosure relates to field of Electronics and VLSI (Very Large-
Scale Integration). More particularly, the present disclosure relates to an improved quantum-
dot cellular automata (QCA) cell-based gate design for an efficient RAM cell.
[0050] In an aspect, the present disclosure provides an improved quantum-dot cellular
automata (QCA) cell-based gate design for an efficient RAM cell. The QCA cell-based gate design can include: a plurality of QCA cells to provide a route to communicate data; at least one output QCA cell configured with the plurality of QCA cells; and at least five input QCA cells configured with the plurality of QCA cells, wherein arrangement of the at least one output QCA cell and the at least five input QCA cells with the plurality of QCA cell allow single as well as multilayer design of the RAM cell, and wherein the arrangement of the at least one output QCA cell, the at least five input QCA cells with the plurality of QCA cells is adapted to reduce input to output delay of the RAM cell.
[0051] In an embodiment, the QCA cell-based gate comprises: one of the at least five
input QCA cells is positioned at left extreme of RAM cell arrangement; the output QCA cell is positioned at right extreme of the RAM cell arrangement; two of the at least five input QCA cells are positioned on upper and lower extreme such that three of the plurality of QCA cells are sandwiched between them, wherein the arrangement of the two input QCA cells and three QCA cells are placed adjacent to the input QCA cell; and two of the at least five input QCA cells are positioned on upper and lower extreme such that five of the plurality of QCA cells are sandwiched between them, wherein the arrangement of the two input QCA cells and the five QCA cells are placed adjacent to the output QCA cell.
[0052] In an embodiment, the plurality of QCA are 11, the input QCA are 5 and
output QCA is 1 such that area expanded by the QCA cell-based gate design is at least .07 micrometre square.
[0053] In an embodiment, the input to output delay is reduced to at least 1.25 clocking
cycles.
[0054] In an embodiment, the RAM cell implementation of the QCA cell-based gate
design comprises at least 85 QCA cells, wherein the RAM cell comprises set and reset capability.
[0055] FIG. 1 illustrates an improved quantum-dot cellular automata (QCA) cell-
based gate design in accordance with an embodiment of the present disclosure.
[0056] In an embodiment, as shown in FIG. 1 an improved quantum-dot cellular
automata (QCA) cell-based gate design can include majority input. The majority is a logic

gate that implements the majority function, when a device is giving output as HIGH when the
majority of its inputs are HIGH, otherwise its output is LOW.
[0057] The present Five-input majority gate is shown in FIG.l. The QCA cell-based
gate design can include 5 input QCA cells A, B, C, D, and E. The QCA cell-based gate
design can include one output (OUT). Further, the QCA cell-based gate design can include
plurality of QCA cells. The Plurality of QCA cells present can be used for transmission of
data from the input QCA cells A, B, C, D and E to the output cell (OUT).
[0058] In an embodiment, if three or more than three inputs (majority of the inputs)
are high (logic 1) then the output (OUT) is also high. This can be easily explained and
depicted in simulation results of present Five- input majority gate as shown in FIG .2.
[0059] Simulation Results of present Five- input majority gate: Simulation results
of present Five- input majority gate is shown in FIG.2. Here A, B, C, D and E are the inputs
and "OUT" is the output. When three or more than three inputs are high, output is high.
Majority gate is provided with a single clock.
[0060] In an embodiment, the Comparison of present Five- input majority gate A, B,
C, D and E with the existing designs is shown in Table 1. The present majority gate design

has reduced area, accessible with single as well as multi- layer design. Table 1.
[0061] From Table 1, it is clear that, Five- input Majority gate designed in the cited
research articles has the problem of unreachability of output cell and input cells in a single layer. So, these designs can be used only for multilayer structure. In designs of cited research, this problem is solved but it has increased the number of QCA cells and hence increase in the occupation area. It further causes more power dissipation due to increased number of QCA cells and occupation area.
[0062] FIG. 3A illustrates a schematic representation of coplanar RAM cell with
set/reset ability in accordance with an embodiment of the present disclosure.
Five-input majority gate-based RAM cell structure of the present invention:
[0063] A novel Coplanar RAM cell structure based upon present Five-input majority
gate 300 is designed with reduced occupation area, cell count and input to output delay.
[0064] In an embodiment, as displayed in FIG. 3A, components used for designing
RAM cell are three 3-input majority gates (302, 304, 306), one NOT gate and one Five-input majority gate 308 having an additional feature of SET/RESET ability. The proposed RAM cell design is utilizing 85 number of QCA cells, 5 gate count having an occupational area of 0.07um with input to output delay of 1.25 clock cycles. Its QCA implementation is as displayed in FIG. 3B and its simulation results are shown in FIG. 4.
Key Features:
• Gate Count = 5
• Coplanar wire crossing = Yes
• Occupation Area = 0.07um2.
• SET/RESET capability = Yes
• Input to Output Delay = 1.25 clock cycles
Working of present RAM cell is explained as follows:
[0065] This design is composed of three-input majority gates which are three in
number connected in a manner with one five-input majority gate as shown in FIG 3A. The present RAM structure is controlled by two separated signals (Set and Reset). In the normal mode (Set = "0" and Reset = "1") when the select signal is activated(" 1") and write/read signal has been set to "1", input data will be transmitted to the output and consequently write

operation will be done. Moreover, read operation has been accomplished by setting these select and write/read signals to "1" and "0", respectively. In the set mode, content of RAM cell will be set to "1" using the determination of set signal value by "1". Also there set mode will be performed by fixing the reset signal to "0" independent of the state of select and write/read signals.
[0066] The Comparison between the present RAM cell structures with the existing
design is shown in Table 2
Table 2
[0067] In an embodiment, the present invention discloses Five- input majority gate
which is utilizing only 17 QCA cells with an occupational area of 0.01 um2.The Five- input majority gates are designed with optimized number of QCA cells which is helpful in reducing the overall size of the RAM cell design and thereby reducing the power dissipation. The structure of the present invention can be used for both single and multilayer design because its input and output cells are reachable from single layer as well as multilayer. It is clearly visible from FIG. 1 that the output of a proposed Five-input majority gate structure can further be connected with any QCA logic design on the same layer, which means that one can connect as many QCA cells as desired with the output QCA cell (OUT in FIG. 1) without using another layer. No such design using five-input majority gate is available to the best of the knowledge of the inventors. Hence the invention duly qualifies the novelty test. Other

such similar designs are either using more number of QCA cells or could not solve the problem of reachability of output cell and input cells in a single layer.
[0068] In an embodiment, the technical advancement of the knowledge lies in
disclosing a high performance QCA based Five-input majority gate design which is utilizing only 17 QCA cells with an occupational area of 0.01 um2 and optimization in the total area and power dissipation characteristics. Simulation results achieved (Tablel, Table2) proves that the QCA based Five- input majority gate has a simple and robust structure and surpasses previous design in terms of input to output latency and area occupation. It is clearly visible from FIG. 1 that the output of the proposed Five-input majority gate structure can further be connected with any QCA logic design on the same layer, which means that one can connect as many QCA cells as desired with the output QCA cell (OUT in FIG. 1) without using another layer. The present RAM cell structure shown in FIG. 3A can be used for both single layer and multi-layer design. The components used for designing RAM cell are three 3-input majority gates, one NOT gate and one Five-input majority gate having an additional feature of SET/RESET ability. The proposed RAM cell design is utilizing 85 number of QCA cells, 5 gate count having an occupational area of 0.07um2 with input to output delay of 1.25 clock cycles.
[0069] INDUSTRIAL APPLICATION-QCA based Five- input majority gate is used
in most of the Electronic equipment for making different circuits. The designing of RAM cell
using reduced number of QCA cells in the Five- input majority gate has enhanced its area
optimization capabilities. So it finds wide applications in Electronics industry for designing
of reduced size RAM cells for data storage and other electronic circuits. It can be easily
manufactured in industry, hence duly qualifies the Industrial application criteria.
[0070] Although the proposed system has been elaborated as above to include all the
main parts, it is completely possible that actual implementations may include only a part of the proposed modules/engines or a combination of those or a division of those in various combinations across multiple devices that can be operatively coupled with each other, including in the cloud. Further the modules/engines can be configured in any sequence to achieve objectives elaborated. Also, it can be appreciated that proposed system can be configured in a computing device or across a plurality of computing devices operatively connected with each other, wherein the computing devices can be any of a computer, a laptop, a smart phone, an Internet enabled mobile device and the like. All such modifications and embodiments are completely within the scope of the present disclosure.

[0071] Embodiments of the present disclosure may be implemented entirely
hardware, entirely software (including firmware, resident software, micro-code, etc.) or
combining software and hardware implementation that may all generally be referred to herein
as a "circuit," "module," "component," or "system." Furthermore, aspects of the present
disclosure may take the form of a computer program product comprising one or more
computer readable media having computer readable program code embodied thereon.
[0072] Thus, it will be appreciated by those of ordinary skill in the art that the
diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[0073] As used herein, and unless the context dictates otherwise, the term "coupled
to" is intended to include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms "coupled to" and "coupled with" are used synonymously. Within the context of this document terms "coupled to" and "coupled with" are also used euphemistically to mean "communicatively coupled with" over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device.
[0074] It should be apparent to those skilled in the art that many more modifications
besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms "comprises" and "comprising" should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements,

components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C .... and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0075] While the foregoing describes various embodiments of the invention, other and
further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.
ADVANTAGES OF THE PRESENT DISCLOSURE
[0076] The present disclosure provides an improved quantum-dot cellular automata
(QCA) cell-based gate design.
[0077] The present disclosure provides an improved quantum-dot cellular automata
(QCA) cell-based gate design that utilizes less number of QCA cells for 5 input and one
output.
[0078] The present disclosure provides an improved quantum-dot cellular automata
(QCA) cell-based gate design that uses lesser occupational area thus, lesser power
dissipation.
[0079] The present disclosure provides an improved quantum-dot cellular automata
(QCA) cell-based gate design that provides with reachability of output cell and input cell in a
single layer.
[0080] The present disclosure provides an improved quantum-dot cellular automata
(QCA) cell-based gate design that provides SET/RESET capabilities.

We Claim:
1. An improved quantum-dot cellular automata (QCA) cell-based gate design for an
efficient RAM cell, said QCA cell-based gate design comprising:
a plurality of QCA cells to provide a route to communicate data; at least one output QCA cell configured with the plurality of QCA cells; and at least five input QCA cells configured with the plurality of QCA cells, wherein arrangement of the at least one output QCA cell and the at least five input QCA cells with the plurality of QCA cell allow single as well as multilayer design of the RAM cell, and
wherein the arrangement of the at least one output QCA cell, the at least five input QCA cells with the plurality of QCA cells is adapted to reduce input to output delay of the RAM cell.
2. The QCA cell-based gate design as claimed in claim 1, wherein design of the QCA cell-
based gate comprises:
one of the at least five input QCA cells is positioned at left extreme of RAM cell arrangement;
the output QCA cell is positioned at right extreme of the RAM cell arrangement;
two of the at least five input QCA cells are positioned on upper and lower extreme such that three of the plurality of QCA cells are sandwiched between them, wherein the arrangement of the two input QCA cells and three QCA cells are placed adjacent to the input QCA cell; and
two of the at least five input QCA cells are positioned on upper and lower extreme such that five of the plurality of QCA cells are sandwiched between them, wherein the arrangement of the two input QCA cells and the five QCA cells are placed adjacent to the output QCA cell.
3. The QCA cell-based gate design as claimed in claim 1, wherein the plurality of QCA are 11, the input QCA are 5 and output QCA is 1 such that area expanded by the QCA cell-based gate design is at least .07 micrometre square.
4. The QCA cell-based gate design as claimed in claim 1, wherein the input to output delay is reduced to at least 1.25 clocking cycles.
5. The QCA cell-based gate design as claimed in claim 1, wherein the RAM cell implementation of the QCA cell-based gate design comprises at least 85 QCA cells.

6. The QCA cell-based gate design as claimed in claim 5, wherein the RAM cell comprises set and reset capability.