1. An Improved System and Method for access arbitration between two or more processor boards based on digital state machine.
2. Field of invention:

This invention relates to arbitration amongst two or more processor cards competing to read/write common devices in an embedded computer. This helps in optimizing the tasks sharing amongst the processor cards and exchanging the information across the tasks being exchanged in the individual processor cards.

3. Prior art and drawback

In the conventional method, the arbitration / access control to one processor card at a time was achieved through a standard arbitration control device . This method provided arbitration between two processor only. The improved method based on FPGA based digital logic has enhanced the arbitration control to more than two processors and adding the features like locking the access for one processor card meeting its higher requirement for the specific period and starving other processors during that period and vice versa .

4. Aim of the invention:

The aim of the invention is to improve the method of arbitration for inter processor exchange of information by accessing common resources with the additional feature of locking mechanism for providing uninterrupted access to one processor board for block operation.

5. Summary of the invention:

An improved system and method is invented for access control of common devices using a high speed FPGA to arbitrate two or more processor based intelligent boards. The arbitration method for efficient access control of common resources is shown in fig.1. The complete system is realized in two stages. In the first stage, the optimized access method is shown for two processor boards. . In the second stage, the optimized access method is shown for four processor boards.

6. Detailed Explanation of Drawing:

Access arbitration between two processor boards are shown in Fig.1. Any one processor issues a request signal to priority logic and receives its priority input signal. After receiving priority the processor board enables its ADDR/DATA buffers and accesses the common resources. In the same manner when the other processor board gets the priority it enables its ADDR/DATA buffers and accesses the common resources. Fig.2 explains the access arbitration amongst four processors. Fig.3 shows the state machine dia gram.

7. Detailed description of working methodology:

In this method, FPGA digital state logic in the both the processor board 1 and processor board 2 control the address/data buffer of individual boards with a common synchronizing clock . Each processor board asynchronously tries to access the common resources. But FPGA of each processor board resolves the conflict of simultaneous access and enables or disables their respective ADDR/DATA buffers. Thus one processor board only can access the common resources at one time. The other processor board waits till the first processor board completes its access. In the intervening period between two cycles the other processor board gains access of the common resources and arbitration goes on. In this process both the processors get equal opportunity to access the common resources. However any processor board wants to access common resources for a block of data transfer without interruption from the other processor board a lock mechanism is implemented for the particular processor board for this purpose. Any processor requiring to access the common resources for a block of data transfer without interruption issues a lock signal separately along with request signal. The particular processor board enables its ADDR/DATA buffers as long as lock is active and accesses the common resources for a block of data transfer without releasing the access right to other processor boards.

For more than two processors, in this case for four processors arbitration in particular, each processor board controls the ADDR/DATA buffer of individual boards with a common synchronizing clock. With a priority resolving logic implemented globally to assign priority to any one processor board by rotation. The processor board after receiving the priority enables its ADDR/DATA buffers to interface with the common devices for data transaction. In the intervening period between two data cycles priority resolver assigns the priority to the remaining requesting processor boards in a predetermined order. The first processor board after loosing its priority to another processor board disables its ADDR/DATA buffers and waits for its next priority assignment to regain the common resources whereas the new processor board assigned with priority enables its ADDR/DATA buffers for access of common resources. In this manner all the processor boards gets their priority in order and accesses the common resources in equal measure. However any processor board wants to access common resources for a block of data transfer without interruption from the other processor board a lock mechanism is implemented for the particular processor board for this purpose. Any processor requiring to access the common resources for a block of data transfer without interruption issues a lock signal separately along with request signal. The particular processor board enables its ADDR/DATA buffers as long as lock is active and accesses the common resources for a block of data transfer without releasing the access right to other processor boards.

CLAIMS

We claim

a) In the conventional method, the arbitration / access control to one processor card at a time was achieved through a standard arbitration control device. This method provided arbitration between two processor only. The improved method based on FPGA based digital logic has enhanced the arbitration control to more than two processors

b) It can also lock the access for any one processor card meeting its block data transfer requirement without interruption from other processor boards for the specific period .In this time the other processor boards cannot get access to common resources and remain starved for that specific period .Once this lock phase is completed by the particular processor the arbitration between the processors continues to function in equal opportunity basis by rotating the accesses.