1. Title of the Invention:

An Improved System and Method for communicating data packets in TTL level serial format between two systems. The rate of data transfer is 1 Mega bit per second.

2. Field of invention:

This invention relates to serial data transfer between two systems at 1 Mega bit per second. This is a synchronous protocol operating with 1 MHz clock source supplied by master system. The master initiates data transfer with ready signal and receives acknowledge from the slave system. The first bit of byte-wise data packet is transmitted in the first clock itself along with the ready signal so that there is no loss of clock cycles and no need of additional protocol bits.

3. Prior art and drawback

In the conventional method, Universal asynchronous / synchronous Receiver Transmitter (UART) protocol is used for serial data transfer wherein additional bits like stop bit and start bit is transmitted for receiver to identify the byte data. In UART asynchronous mode a valid bit state is recognized after 16 times sampling and consistency of central 3 bits as either high or low. This makes the data transfer rate slower. The method of serial communication has no overhead and faster.

4. Aim of the invention:

The aim of the invention is to improve the speed of serial data transfer and reliability between point to point communication. This type of communication will have added advantage in short distance communication between two systems in airborne platform.

5. Summary of the invention:

An improved system and method is invented for serial communication between master and slave devices using high speed FPGA. Master and slave devices can both be intelligent microprocessor based systems or one is intelligent and other is non-intelligent or both non-intelligent. Using a high speed FPGA faster and reliable serial communication between two systems in airborne platform provides a configurable and convenient mode of communication without the use of standard devices based on UART protocol eliminating the risk of obsolescence.

6. Detailed Explanation of Drawing:

High speed Serial communication scheme based on digital state logic implemented in FPGA without any overhead is shown in Fig.Land Fig.2 for transmission and receiver block respectively. Master system issues a ready signal to slave system and receives its acknowledge input signal. Before receiving acknowledge the master system sends the first bit along with ready signal and after receiving the acknowledge continues to send the remaining bits of the byte. It counts the number of bits from 7 down to 0 and again starts with the first bit for sending to slave system. In the same manner when the master system wants the slave system to send data packets it issues a request signal in the first clock period rising edge while slave system transmits the first bit in same clock along with the falling edge. The master system keeps counting the remaining bits from 7 down to 0, packs in a byte and then start receiving the subsequent bytes similarly.

7. Detailed description of working methodology:

In this improved method of high speed serial communication, FPGA digital state logic in the master system is implemented using VHDL language for transmission and receiving data packets. Similarly the slave system implements the FPGA digital state logic for receiving and transmitting the data packets with the master. Serial communication protocol is explained in two parts. Parti : The master transmits data packet to the slave system and the slave system receives the same. Part2: The master receives data from the slave system and slave system transmits the data packet to the master on his request.

Parti: The master interfaces with the slave system with 5 signals. They are data transmit request, transmit enable, transmit ready/start, acknowledge and clock . Both master and slave are synchronized for data transmit and receive with same clock sourced by master. Master digital state logic initiates data transfer by activating transmit enable signal and ready/start signal synchronized with rising edge of first clock for identification of the first bit of first byte for transmission. The first bit of first byte is transmitted by master on the rising edge of the first clock. The slave system start receiving data bits from the first clock falling edge onward and returns an acknowledge signal on the falling edge of the first clock. After receiving 8 bits and saving as a byte it keeps receiving 2nd, 3rd bytes till transmit enable signal remains activated. Detailed timing diagram is given in Fig.3.

Part2: The master interfaces with the slave system with 5 signals. They are data, receive request enable, receive ready/start, acknowledge and clock . Both master and slave are synchronized for data receive and transmit with same clock sourced by master. Master digital state logic initiates data transfer by activating receive enable signal and receive ready/start signal synchronized with rising edge of first clock for identification of the first bit of first byte for reception. The slave system start transmitting data bits from the first clock falling edge onward and returns an acknowledge signal on the falling edge of the first clock. Master starts receiving with the first bit on the rising edge of the 2nd clock and after receiving 8 bits of data it keeps receiving 2nd , 3rd byte till receive enable signal remains activated. Detailed timing diagram is given in Fig.4.

CLAIMS

We claim

1) The system and method for high speed custom serial communication for Airborne platform, based on FPGA based digital logic to communicate from one node to another node initiated by master to transmit and receive serial data to/from slave devices.

2) The system and method claimed in Claiml : In the improved method a protocol is used which enables the transmission of each bit at every clock requiring no overhead and extra sampling with the help of three control signals like transmit enable, transmit start/ready and acknowledge. It achieves the high speed synchronous transmission between two nodes with 1 MHz common clock supplied by master.

3) The system and method claimed in Claiml : In the improved method a protocol is used which enables the receiving of each bit at every clock requiring no overhead and extra sampling with the help of three control signals like receive enable, receive start/ready and acknowledge. It achieves the high speed synchronous reception between two nodes with 1 MHz common clock supplied by master.