AN IMPROVED VOLTAGE TRANSLATOR HAVING MINIMIZED POWER
DISSIPATION
Field of the Invention
The present invention generally relates to the field of voltage level translator circuits. In particular it relates to an improved low to high-level voltage translator where the difference between core and I/O supply voltage is very large.
Background of the Invention
Advancements in semiconductor fabrication and manufacturing techniques have led to reduction in operating voltage levels. One of the reasons to use lower operating voltage levels is to reduce the power consumption of a semiconductor chip.
Considering the case when the chip is interfaced with bus standards based on higher voltage levels, only main bulk (core) of the chip is operated at lower voltage level and its I/O interface is operated at higher voltage levels. In order to implement such a scheme it is required to translate high voltage I/O signals to low voltage core signals and low voltage core signals to high voltage I/O signals.
One main problem while translating low voltage core signals to high voltage I/O signals is of direct current paths causing power dissipation. If a low voltage signal is used to drive device operating at higher voltage, it would cause the device to draw d.c. power, since it is neither fully off nor fully on. Thus a circuitry is required for translating voltage signals, which can minimize dc current problems and thus minimize power dissipation.
Figurel shows a prior art translating circuitry that is an embodiment of the US Patent
5,422,523.
This translator circuitry gives good results when voltage difference is small, but starts malfunctioning and even fails completely when difference between higher and lower supply voltages is large.
Figure 2 shows the simulation results of the prior art circuitry, for higher supply voltage VCC equal to 3.3 V and lower supply voltage equal to 1.2 V. In the figure output OUT of translating circuitry is shown for five different operating conditions (mentioned in figure itself). It can be seen that for Cond.l, Cond.2 and Cond.3 output is acceptable but for Cond.4 it gets distorted and for Cond.5 there is no output (constant low).
The reason for the failure of the circuit is the cross-coupled gates using regenerative feedbacks. In this circuit switching is initialized by the input signal IN and finally controlled and concluded by regenerative feedback. Switching initialization by the input IN has to ensure some threshold voltage reached at the nodes OUT and X, before switching is handed over to regenerative feedback. If the initialization process is weak, then translator will switch late or will not switch and the output OUT will get distorted or stuck to one state (high or low).
For example, when input IN is at low state, N12 is off, Nil is on, node OUT is at logic low and P12 is on, node X is at logic high and P11 is off. It is to be noted the NMOSs N11 and N12 are driven by lower supply voltage and PMOSs P11 and P12 are driven by higher supply voltage. Now when input IN switches from low to high, N12 will switch on and will try to pull-down the node X. But to pull-down this node it has to fight with perfectly on PMOS P12. In turn PMOS P12 will not going to switch off unless node X goes low effectively. In this case if N12 is not strong enough to pull-down the node X effectively, output node OUT will not be pulled-up but get stuck to logic low.
Same thing may happen in case high to low transition, where N11 has to fight with P11 to pull-down the node OUT. If N11 is not strong enough, output node OUT will not be pulled-down but get stuck to logic high.
This condition is very likely to occur in case when difference between higher and lower supply voltage is large, as in case of example shown in Figure-2. Referring to example where lower supply voltage is 1.2 V and higher supply voltage is 3.3 V, NMOSs Nil,
N12 will be switched on with Vgs equal to 1.2 V while PMOSs P11, P12 are on with Vgs equal to -3.3 V. Magnitude of NMOSs 'on' voltage being very small compared to that of PMOSs, makes them very weak. Therefore the sizes of the NMOSs have to be kept relatively very large to ensure proper functioning. But despite of large size of NMOSs, the circuitry still remains very uncertain with variation in operating conditions. When sized nicely to give good results in one operating condition, it gives distorted signals or even no signal in other operating condition. This can seen from Figure-2, that circuitry giving good results in Condition 2, gives distorted signal for Condition 4 and no signal in Condition 5.
The situation becomes even worse when there are bounces on ground plane. This translator circuitry is most likely to be used in I/O circuitry, which are inherently noisy. So ground bounce will be a very common event in this circuitry. If ground bounce occurs at the time of input transitions, effective Vgs of NMOSs will reduced and thus weakening them further. This will cause signal distortion.
The situation of having large difference between higher and lower supply voltage, frequently arrives in case of FPGAs (Field Programmable Gate Arrays) as they are often used for various applications and are therefore interfaced with various devices operating at varied bus standards. Due to vast and diverse field of applications of FPGAs it becomes desirable to have their I/O interface circuits capable of being programmed to operate at various voltage levels.
In reference to the problems discussed above, a need is felt for a voltage translator circuit that does not have any dc current paths to minimize any power dissipation.
Object and Summary of the Invention
The object of the present invention is to obviate the shortcomings of the prior art and provide an improved voltage translator having minimized power dissipation.
Further object of the present invention to provide an improved voltage translator having a feedback circuit to block all the dc current paths during input signal transitions for minimizing power dissipation.
Another object of the present invention to provide a voltage translator having minimum power dissipation with reduced area.
To achieve said objectives the present invention provides an improved voltage translator
comprising:
a plurality of transistors, receiving a common input signal at an input node
of said plurality of transistors and passing the voltage translated output
signal at an output node of said plurality of transistors, wherein,
a latch circuit is connected at a first node to the output node of said
plurality of transistors,
a feedback element is connected between a second node of said latch
circuit and an input side of said plurality of transistors to form a feedback
circuit to minimize power dissipation.
The said latch circuit comprises at least two inverters coupled to form a closed path and said feedback element is a PMOS or NMOS transistor. The plurality of transistors comprises PMOS or NMOS transistors.
This invention further relates to a method for providing an improved voltage translator having minimized power dissipation, the method comprises steps of:
inputting a common signal to a plurality of transistors and outputting the voltage translated output signal at the output node of said plurality of transistors,
connecting a latch circuit between said output node and a feedback element,
sending a feedback signal from said latch circuit to said plurality of transistors to reduce the power dissipation.
Thereby, the present invention provides an improved voltage translator with minimized power dissipation and occupies minimum chip area.
Brief description of the Accompanying diagrams
The invention will now be described with reference to the accompanying drawings.
Figure 1 shows the prior art voltage translator circuit.
Figure 2 shows the prior art simulation results in different operating conditions for voltage translation of 1.2V to 3.3V.
Figure 3 shows the voltage translator circuit according to the present invention.
Figure 4 shows the simulation results of the instant invention in different operating conditions for 1.2V to 3.3V translation.
Detailed Description
Figure 1 & Figure 2 that illustrate the prior art voltage translator circuit and its simulation results respectively have been described under the heading Background of the Invention.
Figure 3 shows the translator of the present invention. IN is low voltage swing input signal to the translator. High voltage swing output of the translator is received at node OUT. VCC is higher voltage power supply. Inverter LV_INV31, which is connected between nodes IN and IN~ operates at lower voltage (core) power supply. IN- signal is the complementary of input signal IN and has same voltage swing as of IN. All other transistors and inverters in the circuitry operates at higher voltage power supply of IOs.
Gate of PMOS P32 is connected to IN, drain to node X and source is connected to I/O power supply VCC. Gate of PMOS P31 is connected to node X, drain to output node OUT, and source is connected to 10 power supply VCC. NMOS N32 has its gate connected to input IN, source is connected to the drain of NMOS N33 and drain is connected to node X. NMOS N33 has its gate connected to net OUTL, drain is connected to the source of N32 and source is connected to the ground potential. Gate of N31 is connected to IN~, drain is connected to output OUT and source is connected to ground. Two inverters HV_INV32 and HV_INV33 form a LATCH as in Figure3. This LATCH is connected between output terminal OUT and net OUTL.
For the ease of explanation, it is assumed here that the lower core supply voltage is 1.2 V and I/O voltage VCC is 3.3V. Translator circuitry in Figure 3 is translating 1.2V core signal into 3.3 V I/O signal. The operation of translator is explained in two separate sections for high-to-low and low-to-high transition of input signal IN.
High-to-low transition of the signal IN: Before high-to-low transition of input signal IN, it is at logic high (1.2V). Output OUT is also at logic high (3.3V) and OUTL at logic low. NMOS N33 is completely off, because OUTL voltage is OV and gate of NMOS N32 is driven by 1.2V. PMOS P32 is partially on because its gate voltage is 1.2V and source is at 3.3V. Being partially on, P32 keeps node X pulled to Voltage 3.3V.
It is be noted here that although gate of NMOS N32 is connected to 1.2V, ground path to node X remains blocked as series connected NMOS N33 is completely off. Node X being at 3.3V, keeps PMOS P31 completely off. NMOS N31 is also completely off as IN- is at logic low. Logic high (3.3V) at output OUT is maintained by the LATCH operating at high I/O supply voltage. So in this steady state situation, no dc path to ground exists, thus nullifying dc power dissipation. Also, both output transistors P31 and N31 are off and signal status at output OUT is maintained by LATCH.
When IN goes high-to-low (1.2V to OV), P32 becomes on (Vgs=-3.3V) and N32 becomes off (Vgs=0V). But this event does not do much job as voltage at node X is already at 3.3V and P31 is already completely off (Vgs=0V).
Operation during high-to-low transition is controlled by NMOS N31, which has its gate connected to IN~. When IN goes high-to-low, IN~ goes low-to-high (OV to 1.2V), switching on NMOS N31 that discharges output terminal OUT to ground.
It is important to point out here that when N31 discharges output terminal OUT to ground, it does not race with any partially or fully on PMOS, because P31 is completely off. While this was not the case in prior art and was one of the main cause of problem. (Note-It is assumed that PMOSs used in LATCH are very weak compared to N31).When OUT goes low, OUTL goes high (3.3V), which turns NMOS N33 completely on (Vgs=3.3V), but N32 is still off.
So after high-to-low switching, when input IN reaches at steady state logic low, again there is no dc path to ground, and therefore no static power dissipation in the translator.
Low-to-high transition of IN: As described already, when IN is at steady state logic low, OUT is at OV, OUTL is at 3.3V, X is at 3.3V. N32 and P31 are completely off, P32, N31 and N33 are on.
When IN changes from low-to-high (OV to 1.2V), NMOS N32 turns on but P32 does not get completely off, and as N33 is already on, this will create a current path between VCC and ground through P32, N32 and N33. But PMOS P32 is kept extremely weak, so the driving strength of ground path (N32 and N33) is more than the strength of supply path (P32). So X discharges close to OV, which turns P31 on. Since IN- is OV, NMOS N31 is off. P31 drives OUT to 3.3V. As OUT becomes 3.3V, OUTL becomes OV, which turns NMOS N33 off. As N33 turns off, again all dc current paths are blocked and there is no static power dissipation, also node X will be pulled back to 3.3V through partially on PMOS P32. This will turn off P31 and OUT will remained latched at 3.3V.
So after low-to-high switching, when input IN reaches at steady state logic high, again there is no static power dissipation in the translator. Also as P31 is off, N31 will easily pull down node OUT in next high-to-low transition.
In low-to-high transition case, a weak PMOS P32 is sufficient to pull back the node X to 3.3 V when N33 goes off. This is because fast rise of voltage at node X is not required, as PMOS P31 is desired to get completely off at any time before the next high-to-low transition at IN. So, as described earlier, a partially on weak PMOS P32 will not going to interfere in pulling down of node X through NMOSs N32 and N33.
It is to be noted that, when IN goes from OV to 1.2V, P31 is on. As OUT becomes 3.3V, OUTL becomes OV, which turns N33 off. So ground path from X is now off and PMOS P31 is partially on (gate voltage is 1.2V), which pulls X to 3.3V and turns PMOS P31 off. During this period, LATCH keeps the output voltage at 3.3V, till the next transition from logic high to logic low occurs. Size of inverters HV_INV32 and HV_INV33 should be sufficient to latch the output. It causes small sized inverters. So when N31 discharging the output terminal OUT, it can easily override the latched voltage.
Figure 4 shows the simulation results of the translator for various operating conditions. Translator of Figure 3 is sized so that, it gives same output results as given by the translator of Figurel under the conditions of supply voltage at 3.3V, temperature at 25°C. Variation in output results of the translator of present invention is less as compared to the variations shown by the prior art, thereby power dissipation is less in the instant invention.
In the present invention complete switching of the translator is controlled by input signal IN and not by any feedback unlike the case in prior art. Feedback in the present invention is used only to block dc current paths. So problems faced in prior art are not seen in present invention.
Although the present invention is described in reference to FPGAs for translating low to high voltage swing signals, where voltage difference is large, it can applied to all the application in CMOS ICs where low to high voltage level translation is required.
The following tables illustrate simulation results of prior art voltage translator and the translator of the present invention. For the translator circuits, delays in typical operating conditions are matched and then performance in different operating conditions is compared:
1. Simulation results of prior art:

(Table Removed)
Translator of prior art fails to operate for Cond.5 and gives poor response for Cond.4. In Cond.5, NMOS becomes slow and PMOS becomes fast which makes the situation worse, because sinking NMOSs are turning on by Vgs=1.2V, whether PMOSs are on by Vgs=-3.3 V. Same thing happens in Slow conditions, where NMOSs and PMOSs are slow and temp and voltages are also slow. In Cond.4 falling of the output becomes very poor, thereby enhancing power dissipation in the circuit.
2. Simulation results of present invention:

(Table Removed)
It can be clearly seen from the above tables that present invention gives good results in different operating conditions also even in Cond.4 and Cond.5. Power dissipation in the present invention is substantially reduced as compared to the prior art voltage translator circuit.
Therefore, we can conclude that present invention provides a voltage translator for translating lower voltage levels (as 1.2V) into higher voltage levels (3.3V), with minimized power dissipation and occupying lesser chip area.

We Claim:
1. An improved voltage translator comprising:
a plurality of transistors, receiving a common input signal at an input node of said plurality of transistors and passing the voltage translated output signal at an output node of said plurality of transistors, wherein, a latch circuit is connected at a first node to the output node of said plurality of transistors, - a feedback element is connected between a second node of said latch circuit and an input side of said plurality of transistors to form a feedback circuit to minimize power dissipation.
2. An improved voltage translator as claimed in claim 1, wherein said latch circuit comprising at least two inverters coupled to form a closed path.
3. An improved voltage translator as claimed in claim 1, wherein said feedback element is a PMOS or NMOS transistor.
4. An improved voltage translator as claimed in claim 1, wherein said plurality of transistors comprising PMOS or NMOS transistors.
5. A method of translating voltage levels with reduced power dissipation, comprising
steps of:
inputting a common signal to a plurality of transistors and outputting the
voltage translated output signal at the output node of said plurality of
transistors,
connecting a latch circuit between said output node and a feedback
element,
sending a feedback signal from said latch circuit to said plurality of
transistors to reduce the power dissipation.
6. A method for providing an improved voltage translator substantially as herein described with reference to the accompanying drawings.
7. An improved voltage translator substantially as herein described with reference to the accompanying drawings.