An Improved Phase Locked Loop (PLL)
Field of the invention
This invention relates to an improved phase locked loop (PLL). that provides controllable lock time, independent of the frequency divider value. The improved PLL also provides bandwidth and damping factor that are indpendent of the frequency divider value when the loop comprises current controlled charge pump and a first order loop filter.
Background of the invention
Phase Locked Loops (PLLs) are critical circuit elements used in various applications including clock generation and clock recovery. Figure 1 shows the block diagram of a conventional PLL circuit which includes a crystal oscillator 01 for generating a low noise reference frequency clock signal (fref). The fref is supplied to one input of a phase detector 03 having a second input to which is supplied the output (fout,/N) of a divide-by-N circuit 08. where N is the frequency divider- value. The output of the phase detector 03 supplies an up-count or a down-count signal to a charge pump circuit 04. Charge pump circuit 04 then supplies a current output to charge or discharge a filter network 05 whose output (in the form of a control voltage) is supplied to the input of a VCO 06, which produces an output clock signal, fout, having a frequency which is equal to (N.fref). The fout signal is supplied to divide-by-N network 08 to produce a feedback signal equal to fout/N which is supplied to the phase detector 03.
Another important aspect of PLL characteristic is to have low-jitter at the output clocks. With reference to Fig. 1. two identified noise sources which may manifest themselves in the form of jitter in fout are. noise nref 02 associated with the reference frequency frcf and noise nvco, 07 associated with VCO 06. Typically. nvco is much greater than nre(- and is the leading cause of jitter at the PLL output. When the VCO noise dominates, it is known [R. E. Best, "Phase Locked Loops", second edition, McGraw Hill Publications. 1993] that the output noise associated with the VCO (and hence. fout) can be reduced by increasing the PLL bandwidth
At the start of the locking procedure, the VCO starts oscillating with a start-up frequency. which is the free-running frequency of the VCO. This frequency changes with time under

control of the feedback loop till the PLL gets locked to the desired frequency. The time which a PLL takes to settle to its stable or locked state, starting from an unlocked and free running state is termed as lock-time, and a small lock-time is always a desirable feature. When the PLL is locked, the frequency difference between reference clock (fret) and the feedback clock (fout/N) is zero. A basic criteria to minimize the lock-time is to minimize the frequency difference between fref and (fout/N). so that minimum time is required for the PLL to reduce the difference to zero. If the start-up frequency or the free-running frequency of the VCO is designated as ffr, where ffr=f0ut at t=0, then the initial frequency difference seen by the PLL. which has to be reduced to zero, could be expressed as ∆ω = |fret - (ffr/N)|. As can be seen. ∆ω is a function of N. Therefore, if the VCO is always started with frequency ffr irrespective of the value N. then the frequency difference increases with N. This results in an increasing lock time, as one goes from lower to higher frequency divider value N and in the worst case the PLL may not get locked at all [R. E. Best. "Phase Locked Loops", second edition. McGraw Hill Publications, 1993].
The lock time also depends on the frequency or phase step-response-time of the system. which is a function of damping factor ζ and the natural frequency ωn of the PLL system. The transient, created by the frequency or phase step, is minimum if ζ=0.7 and if the natural frequency ωn is large.
Thus, it can be concluded that to achieve a constant and small lock-time, and to maintain optimized settling and noise characteristic, an optimally designed PLL should keep the designed value of ∆ω and ΩBW (and hence, ωn and ζ) independent of the division ratio N. throughout its operating regime. However, in many applications, the division ratio. N can not be set always to an optimum value because in those applications N is varied during the operation of the system. Common examples are clock-generator circuits used in microprocessors and communication systems, and PLL based frequency synthesizers. In these applications variation in N results in non-optimal performance of the PLL and causes poor lock-time and settling behaviour, apart from increasing the jitter in the VCO output.
There are no known techniques for making PLL lock time independent of frequency divider value or for minimizing PLL lock time.

US patent 6.163.184 describes an improved phase locked loop (PLL) in which bandwidth is independent of the frequency divider value. In this invention the charge-pump current. ICP or VCO gain, Kvco or loop-filter resistance. R can be programmed to vary as a function of N to render the bandwidth of the PLL independent of the divider ratio N. Implementation of this invention keeps the PLL bandwidth independent of divider ratio N, but without maintaining and keeping the lock-time small as the count increases. This invention controls the programmability by adjusting with the current bias of charge-pump or VCO. This invention does not address the problem of minimizing the lock time. It is an object of the present invention to maintain small lock-time and optimum settling behaviour irrespective of divider-ratio increment, simultaneously reducing the noise-manifested-jitter present at the PLL output.
The object and summary of the invention
An object of this invention is to provide an improved phase locked loop (PLL) in which the lock time is made independent of the frequency divider value. Another object of this invention is to provide an improved PLL in which the bandwidth and damping factor are independent of the frequency divider value when the loop comprises a current control charge punp and a sngle irder loop filter, thereby minimizing jitter at the PLL output.
To achieve the said objective this invention provides an improved phase locked loop (PLL) comprising:
a frequency multiplier including a Voltage Controlled Oscillator (VCO) and having one input connected to a reference frequency signal, its second input connected to a programmable frequency divider network, programmable for dividing an input frequency by an integer value 'N'. and its output connected to the input of said programmable frequency divider network while producing an output signal having a frequency equal to the product of said reference frequency and said integer divider value 'N' characterized in that said VCO includes a control circuit for automatically adjusting its initial free-running frequency in response to changes in said integer divider value such that the frequency difference between initial free-running VCO frequency
divided by said integer divider value and said reference-frequency, is maintained at an
approximately constant defined value, resulting in a controllable lock time that is independent of said integer divider value.
The bandwidth and damping factor are also independent of said integer divider value when said frequency multiplier comprises a current controlled charge pump and single order loop filter, thereby minimizing jitter at the PLL output.
The said VCO initial free-running frequency is adjusted to provide minimum lock time independent of said integer divider value.
The VCO is a ring oscillator comprising a number of voltage-controlled delay elements connected in a loop with the initial free-running frequency being determined by the combined delay of the number of delay elements in the loop while operating at the initial control
voltage.
The initial free-running VCO frequency is altered, by varying the effective number of delav elements connected in the loop.
The number of delay elements in the loop is altered by selectively bypassing the required number of delay elements while forming the loop.
The delay elements are selectively bypassed using a multiplexer circuit having each input connected to the output of one of the decoder elements, and its output connected to the feedback path of the loop.
The present invention further provides a method for improving a phase locked loop (PLL) by automatically adjusting the initial free-running frequency of its voltage controlled oscillator (VCO) in response to changes in the value of the integer frequency divider in the loop such that the initial free-running frequency divided by the integer divider value is maintained at an approximately constant controllable difference relative to the reference frequency, so as to provide a controllable lock time that is independent of said integer divider value.
The bandwidth and damping factor are also made independent of said integer divider value when said PLL uses a current operated charge pump and single order loop filter, thereby minimizing jitter at the PLL output.
The said initial free-running VCO frequency is adjusted to provide minimum lock time independent of said integer divider value.
The said method is applied to a PLL using a VCO that is a ring oscillator comprising a number of voltage controlled delay elements connected in a loop wherein the initial free-running frequency is altered by varying the number of the delay element.
The number of delay elements is altered by selectively bypassing the required number of delay elements in the loop.
Brief description of the drawings
The invention will now be described wth reference to the accompanying drawings.
FIG. 1 is a schematic block diagram of a conventional PLL
FIG. 2 is a schematic of the charge pump and loop filter sections of a conventional PLL
FIG. 3 is a schematic of a conventional ring oscillator based Voltage Controlled Oscillator
(VCO).
FIG. 4 shows a programmable ring oscillator based VCO according to this invention
FIG. 5 is a schematic of block diagram of an improved PLL, according to this invention.
Detailed description of the drawings
Figure 1 is already explained in the background of the invention.
Figure 2 shows the schematic of a current control charge pump and single order loop filter 'On' and 'Up" are complimentary outputs from phase detector 03 which controls switches SI & S2 to provide charging current lup or discharging current Idn to capacitor and resistor network CR of loop filer 05 to generate control voltage Vctrl at the input of VCO 06.
The free-running frequency ωn and the damping factor ζ of a second order PLL system
{comprising a first order loop filter and a first order VCO block) are expressed as:
(Formula Removed)
where. C and R are the filter components and ΩBW is the loop-gain bandwidth of the PLL.
Figure 3 shows a conventional ring oscillator VCO. Delay cells 1-to-M are connected in a loop with the output of final delay cell M. (which is also the final output of the VCO). connected back to the input of the first delay cell 1. Each delay cell is provided with a common control voltage Vctrt, which controls the delay of the cell. Typically, the total number of delay cells M is an odd value integer.
The operating frequency of such a VCO can be expressed as:
(Formula Removed)
where, frco/fctrl=f0 is the frequency of VCO when the control voltage, Vctrl is equal to Vo volts; V0 being the control voltage at the VCO input at the PLL start-up, M is the (odd) number of delay-cells included in the ring-oscillator chain and A is the delay per delay-cell when the control voltage is equal to Vo.
When the VCO control voltage. Vctrl reaches 1.0 volt above V0 (i.e., when Vctrl=V0+l=V1). let us assume per delay-cell delay increases by 5. In such a situation, the operating frequency of the VCO can be expressed as:
(Formula Removed)
Using (3) and (4). the VCO gain. Kvco can. therefore, be expressed as:
(Formula Removed)
The loop-gain bandwidth, or simply the bandwidth, of a PLL system having a charge pump circuit 04 and a first-order loop filter 05, may be expressed as follows:
where. Kvco is the gain of the VCO. ICP is the charge pump current produced at the output of charge pump 04 which flows into or out of (where, it is assumed that lDX=IUP=Icp) the filter network 05; N is the division ratio of the feedback divider network 08: and R is the resistance of filter network 05. The filter network also includes an integrating capacitor C. As evident from (1) and (2). the natural frequency ωn and the damping factor ζ. both are function of N. Since, the PLL bandwidth ΩBW is inversely proportional to N, Ωn and ζ decrease as N increases. Thus, except for the smallest value of N, the PLL will have a suboptimal settling time, and hence non-minimal lock-time. That is. the greater N is made, the lower ΩBW is going to be: and as a result Ωn and ζ will drift from their predesigned optimized values.
Figure 4 show:s the modification of the VCO. according to this invention, where the PLL includes programmable delay length of a ring-oscillator based VCO. programmed to be a function of N. for selectively modifying the initial free-running frequency of the VCO and to make the transfer function of the PLL a function of the divider ratio N.
The free running VCO clock frequency is made a function of the divider ratio N. This is done by making the free running VCO clock frequency. f1.fr equal to (N/N1).f1.fr where f1.fr is the free running VCO clock frequency when N=Ni: N{ being the smallest allowed divider ratio. Since, the ratio (f|.t-r/N1) is a constant and. let us say. equal to C1, therefore the frequency step (Aw) at the time of PLL starting from an unlocked and free running state, becomes independent of divider ratio N and can be expressed as:
As can be seen from (7). Aw is now no longer a function of N and always provides a minimum constant frequency difference to the PLL. This maintains the lock-time small and independent of the divider ratio N. Moreover, the VCO gain Kvco also simultaneously becomes a function of the divider ratio N. In fact. Kvco becomes equal to (N/N1).K1.vco where
K.I.VCO is the VCO gain when N=N|. Since the ratio. (K1.vco/N1) is constant and. say, equal to C\ the bandwidth. ΩBW of the PLL and may be expressed as:
(Formula Removed)
Thus, PLL circuits formed in accordance with the invention have bandwidth which is independent of divider ratio N.
Assume that (5) is the gain of the VCO when the divider ratio N=N1 (N| being the smallest allowed divider ratio) and let this gain be designated as K1.VCO- Also, assume that when the divider ratio N is incremented by an integral value to N1+l. m number of delay-cells are removed from the ring-oscillator chain, thereby modifying (3) and (4). and resulting in (9) and (10):
From (9) and (10). when the divider ratio is N+l, the VCO gain can be expressed as:
(Formula Removed)
It can be seen from (3) and (9) that the VCO frequency at Vctr|=0 is the same as the start-up (or initial free-running) VCO frequency at N=N| and N=N1+l. respectively. Therefore, using (3) and (9), the start-up (or initial free-running) frequency at N=N1 and N=N1+k (k being an integer), can be defined as:
where. fu-r is the initial free-running frequency when K=N1 and ffr is the initial free-running frequency when N=N|+k.
When N=N|. the difference between the initial free-running VCO frequency f1,fr and reference frequency frcf-can be expressed as:
(Formula Removed)
Similarly, when N=N1+k, the difference between the initial free-running VCO frequency ffr and reference frequency fref can be expressed as:

To keep Aco the same in both the cases. (13) and (14) have to be equal to each other. Equalizing (13) and (14), results in the following expression relating f1.t-r and ffr:
Using (12) and (15). the required number of delay-cells to be removed from the delay- chain and can be expressed as:
Therefore, if m number of delay cells, as given by (16), ae removed from the delay chain of the ring-oscillator based VCO, while moving from NI to N|+k, then Aco will remain constant and independent of the divider ratio N.
Applying (16) and (12) in (14). results in the following expression:
where. C2=(f|.rr/N1). Therefore, frequency step. Aco at the start up of PLL from an unlocked and free-running condition is constant, thus maintaining the lock-time to a predesigned small value, irrespective of divider ratio N.
It can also be seen from (5) and (11) that while moving from N to N+l. Kvco increases by a factor. FK expressed as:
To achieve relationship (8). it is necessary to maintain Kvco = (N/N1).K1.vco- where N=N1+k. k is an integer. Therefore, the following expression has to be valid:
(Formula Removed)
On simplifying (19).
(Formula Removed)
As can be seen, (20) is exactly the same as (16). Therefore, while moving from NI to N1+k. if m number of delay-cells, given by (16) or (20), are removed from the delay chain of the ring-oscillator based VCO. then not only is a constant Aw achieved, but simultaneously a constant PLL bandwidth which is also independent of N is also realized.
It can be concluded from the above analysis that to achieve (7), with every integral increment in smallest allowed divider ratio N|, m number of delay-cells, given by (16), have to be removed from the chain of delay-cells used in the ring oscillator based VCO. This methodology of removal of m delay-cells with every increment in N, fulfils (8) as well.
If. say, in the designed PLL. the starting or lowest allowed count is N=N| and final or the highest allowed count is N=NF. Also, assuming, the divider ratio integral increment factor, k varies from 0 to kp. i.e., when N=N1. k=0 and when N=NF, k=kF. Referring Fig.4. it can be seen that, switches Sk=0 to Sk=kf are arranged in a predetermined fashion, such that at a time only one switch gets activated and completes the ring-oscillator loop by feedbacking the output to the input. These switches are controlled by the decoder output, which, in turn, is controlled by the divider ratio programming bits. Therefore, at each count, the binary divider ratio programming bits are first decoded and then the decoded output is used to control a particular switch to include a predetermined set of delay-cells in the ring-oscillator chain. Assuming, the divider ratio starts from N=N1, and at this instance the decoder decodes and selects switch Sk=o and closes it. the rest of the switches (Sk=1 to Sk=kF) are kept open. Closure of Sk=0 switch starts the ring-oscillator (and hence, the VCO) with total M delay cells in the
feedback loop. At the next divider ratio count. N increases to N1+1, because k increases from 0 to 1. At this instance, decoder decodes and selects switch Sk=1, thus removing mk=1 cells from the ring-oscillator and starting the VCO with total (M-mk=1) delay-cells in the feedback loop. Value of mk=1 can be calculated using (14). which is a function of design parameters M. N, and k and, thus, placement of switch Sk=1 is determined. Care has to be taken, however, to maintain an odd count of the total number of delay cells included in the delay chain for every count. Similarly, for the next divider ratio count, total mk=2 delay cells are removed from the delay chain; and so on for rest of the counts as well, every time removing suitable number of delay-cells from the delay chain.
Figure 5 shows the improved PLL, according to this invention. The start-up frequency difference step, ∆ω and the bandwidth. ∆BW of the PLL are made independent of the divider ratio N, whereby the PLL will always run at its minimum predesigned start-up frequency step and maximum predesigned bandwidth: thus, ensuring fast settling and lock time, simultaneously minimizing jitter at the PLL output. The PLL includes the voltage controlled oscillator circuit of figure 4, the start-up frequency and the gain (Kvco) of which may be programmed to be a function of N to provide constant frequency difference step Aco and to render the bandwidth of the PLL substantially independent of the divider ratio N. the selected divider value is simultaneously suuplied to the divider network and the VCO so that the VCO is adjusted suitably whenever the divider value is changed.
Implementation and realization of the present invention in circuital form is straightforward and could be achieved using conventional circuit blocks. The decoder could be any prior art decoder available, and the switches could be any readily available prior art digital switches, like transmission gates.

We claim: -
1. A phase locked loop (PLL) comprising:
- a programmable frequency divider network for dividing an input frequency by an integer value; and
- a frequency multiplier comprising a voltage controlled oscillator (VCO) and having a first input for receiving a reference frequency, a second input connected to an output of said programmable frequency divider network, and an output connected to an input of said programmable frequency divider network, said frequency multiplier generating at the output an output signal having a frequency equal to a product of the reference frequency and the integer value;
said VCO comprising a control circuit for adjusting an initial free-running frequency of said VCO in response to changes in the integer value so that a frequency difference between the initial free-running frequency divided by the integer value and the reference frequency is maintained at an approximately constant value, resulting in a controllable lock time that is independent of the integer value.
2. A PLL as claimed in claim 1 wherein said frequency multiplier comprises a current controlled charge pump and a single order loop filter connected thereto so that a bandwidth and a damping-factor of the PLL are also independent of the integer value for maintaining settling behavior and reducing jitter.
3. A PLL as claimed in claim 1 wherein the initial free running frequency of said VCO is adjusted to provide a reduced lock time that is independent of the integer value.
4. A PLL as claimed in claim 1 wherein said VCO comprises ring oscillator comprising a plurality of voltage controlled delay elements connectable in a loop, the initial free-running frequency of said VCO being determined by a combined delay of said voltage-controlled delay elements connected in the loop.
5. A PLL as claimed in claim 4 wherein the initial free running frequency of said VCO is adjusted by varying the number of said voltage-controlled delay elements connected in the loop.
6. A PLL as claimed in claim 4 wherein the number of said voltage-controlled delay elements connected in the loop is varied by selectively bypassing a required number of delay elements while forming the loop.
7. A PLL as claimed in claim 6 wherein said ring oscillator comprises:

- a decoder having an input for receiving the integer value; and
- a multiplexer circuit having inputs connected to outputs of said decoder, and outputs connected to said plurality of voltage-controlled delay elements via a feedback path of the loop, said multiplexer circuit for selectively bypassing said voltage-controlled delay elements.
8. A method for generating an output signal from a phase locked loop (PLL) comprising
a programmable frequency divider network for dividing an input frequency by an integer
value, and a frequency multiplier comprising a voltage controlled oscillator (VCO) having
an output connected to an input of the programmable frequency divider network, the
method comprising:
- providing a reference frequency to a first input of the frequency multiplier, and providing an output of the programmable frequency divider network to a second input of the frequency multiplier, and generating at the output of the frequency multiplier the output signal having a frequency equal to a product of the reference frequency and the integer value; and
- adjusting an initial free-running frequency of the VCO in response to changes in the integer value so that a frequency difference between the initial free-running frequency divided by the integer value and the reference frequency is maintained at an approximately constant value, resulting in a controllable lock time that is independent of the integer divider value.

9. A method as claimed in claim 8 wherein the frequency multiplier comprises a current
controlled charge pump and a filter connected thereto so that a bandwidth and a
damping-factor of the PLL are also independent of the integer value for reducing jitter.
10. A method as claimed in claim 8 wherein the VCO comprises a ring oscillator comprising a plurality of voltage controlled delay elements connectable in a loop; and wherein the initial free-running frequency of the VCO is adjusted by varying the number of voltage-controlled delay elements connected in the loop.
11. A method as claimed in claim 10 wherein the number of voltage-controlled delay elements is varied by selectively bypassing a required number of delay elements in the loop.