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FORM 2
THE PATENTS ACT 1970
[39 OF 1970]
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[Sec Section 10; rule 13]
'AN INTEGRATED CIRCUIT PACKAGE"
JNTEL CORPORATION, a Delaware corporation, of 2200 Missioa College Boulevard, Santa Clara, California 95052, United States of America,
The following specification particularly describes the invention and the manner in which it is to be performed:

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circuit I and the substrate 3. The differential expansion may induce stresses that can crack the solder bumps 2, The solder bumps 2 carry electrical current between the integrated circuit
1 and the substrate 3 so that any crack in the
bumps 2 may affect the operation of the circuit 1.
The package may include an underfill material 4-that is located between the integrated circuit 1 and the substrate 3. The underfill material 4 is typically an epoxy which strengthens the solder joint reliability and the thermo-mechanical moisture stability of the 1C package.
The package may have hundreds of solder bumps
2 arranged in a two dimensional array across the
bottom of the integrated circuit 1. The epoxy 4
is typically applied to the solder bump interface
by dispensing a single line of uncured epoxy
material along one side of the integrated circuit.
The epoxy then flows between the solder bumps.
The epoxy 4 must be dispensed in a manner that
covers all of the solder bumps 2.
It is desirable to dispense the epoxy 4 at only one side o£ the integrated circuit to insure that air voids are not formed in the underfill. Air voids weaken the structural integrity of the integrated circuit/substrate interface. Additionally, the underfill material 4 must have good adhesion strength with both the substrate 3 and the integrated circuit 1 to prevent

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3
A CONTROLLED COLLAPSE CHIP CONNECTION (C4)
INTEGRATED CIRCUIT PACKAGE WHICH HAS TWO
DISSIMILAR UNDERFILL MATERIALS
BACKGROUND OF TEE INVENTION
1, FIELD OF THE INVENTION
The present invention relates to an integrated
circuit package.
2. BACKGROUND INFORMATION
Integrated circuits are typically assembled into a package that is soldered to a printed circuit board. Figure 1 shows a type of integrated circuit package that is commonly referred to as flip chip or C4 package. The integrated circuit 1 contains a number of solder bumps 2 that are soldered to a top surface of a substrate 3.
The substrate 3 is typically constructed from a composite material which has a coefficient of thermal expansion that is different than the coefficient of thermal expansion for the integrated circuit. Any variation in the temperature of the package may cause a resultant differential expansion between the integrated

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delamination during thermal and moisture loading. The Gpoxy 4 must therefore, be a material which is provided in a state that can flow under the entire integrated circuit/substrate interface while having good adhesion properties.
The substrate 3 is typically constructed from a ceramic material. ceramic materials are relatively expensive to produce in mass quantities. It would therefore be desirable to provide an organic substrate for a CM package. Organic substrates tend to absorb moisture which may be released during the underfill process. The release of moisture during the underfill process may create voids in the underfill material-Organic substrates also tend to have a higher coefficient of thermal expansion compared to ceramic substrates that may result in higher stresses in the die, underfill and solder bumps. The higher stresses in the epoxy may lead to cracks during thermal loading which propagate into the substrate and cause the package to fail by breaking metal traces. The higher stresses may also lead to die failure during thermal loading and increase the sensitivity to air and moisture voiding. The bumps may extrude into the voids during thermal loading, particularly for packages with a relatively high bump density. It. would be desirable to provide a C4 package that utilizes an organic substrate.

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SUMMAKY OF THE INVENTION
One embodiment of the present invention is an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a side view of an integrated circuit package of the prior art;
Figure 2 is a top view of an embodiment of an integrated circuit package of the present invention;
Figure 3 is an enlarged side view of the integrated circuit package;
Figure 4 is a schematic showing a process for assembling the integrated circuit package.
DETAILED DESCRIPTION OF THE INVENTION
Referring to the drawings more particularly by reference numbers, Figures 2 and 3 show an embodiment of an integrated circuit package 10 of the present invention. The package 10 may include a substrate 12 which has a first surface 14 and a

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WE CLAIM:
1. An integrated circuit package, comprising;
an. organic substrate (12);
an integrated circuit (IC, 18) mounted to said organic substrate;
a solder bump (20,22) attached to said integrated circuit (18) and said
organic substrate (12);
a first underfill material (24) attached to a top surface (14) of said
organic substrate (12) and to a bottom surface of said integrated
circuit (18), said first underfill material (24) having a first adhesive
strength; and
a second underfill material (26) that is applied as a circumferential
fillet in a gel form to a side of said integrated circuit (18) and to said
top surface (14) of said organic substrate (12), said second underfill
material (26) being different than said first underfill material (24) and
having a second adhesion strength that is lower than said first
adhesive strength and a higher fracture/crack resistance than said
first underfill material (24).
2. The package as claimed in claim 1, wherein said second underfill material seals said first underfill material
3. The package as claimed in claim 1, wherein said organic substrate is baked at a temperature including 163thC before being mounted to said IC.
4. The package as claimed in claim 1, wherein said first underfill material is an epoxy.
5. The package as claimed in, claim 4, wherein said second underfill material is an anhydride epoxy.
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6. The package as claimed in claim 1, said circumferential fillet that seals edges of said IC (IS) and said first underfill material (24).
7. A process for underfilling an integrated circuit as claimed in claim 1 that is mounted to a substrate comprising the steps of:
heating the substrate;
mounting the integrated circuit to the substrate;
heating a first underfill material to a partial gel state;
dispensing said first underfill material (24) attached to a top surface
(14) of said substrate (12) and to a bottom surface of said integrated
circuit (18), said first underfill material (24) having a first adhesive
strength; and,
dispensing a second underfill material that is applied as a
circumferential fillet in a gel form to a side of said integrated circuit
(18) and to said top surface (14) of said substrate (12), said second
underfill material (26) being different than said first underfill material
(24) and having a second adhesion strength that is lower than said
first adhesive strength and a higher fracture/ crack resistance than
said first underfill material (24).
8. The process as claimed in claim 7, wherein said first underfill material flows between said integrated circuit and said substrate,
9. A process as claimed in claim 8, wherein said substrate moves within an oven while said first underfill material flows between the integrated circuit and the substrate .
10. The process as claimed in claim 7, wherein said second underfill
material is dispensed in a pattern which surrounds said first underfill
material.
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11. The process as claimed in claim 7, wherein the substrate is heated to a temperature that is greater than a temperature of said partially gelled first underfill material.
12. The process as claimed in claim 7, wherein the integrated circuit is mounted to the substrate with a solder bump.
13. The process as claimed in claim 7, wherein the integrated circuit (18) is mounted to the substrate (12) with a solder bump.
Dated this 4^ day of September, 2001.
[
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ABSTRACT OF THE INVENTION
"AN INTEGRATED CIRCUIT PACKAGE"
An Integrated Circuit package comprising:

an organic substrate (12);
an integrated circuit (1C, 18) mounted to said organic substrate; a solder bump (20,22) attached to said integrated circuit (18] and said organic substrate (12);
a first underfill material (24) attached to a top surface (14) of said organic substrate (12) and to a bottom surface of said integrated circuit (18), said first underfill material (24) having a first adhesive strength; and
a second underfill material (26) that is applied as a circumferential fillet in a gel form to a side of said integrated circuit (18) and to said top surface (14) of said organic substrate (12), said second underfill material (26) being different than said first underfill material (24) and having a second adhesion strength that is lower than said first adhesive strength and a higher fracture/crack resistance than said first underfill material (24).