Field of the Invention
The present invention relates to an integrated interface to test and debug failing memory on an Integrated circuit.
Background of the Invention
The increasing complexity on chip is inducing more defects in a System on Chip (SoC) design, which is causing an increase in the testing requirements on the chip.
The yield of SOC is directly linked to the memories on the SOC as there are around 60-70 % of the memories on the chip. Thus the memory yield is directly converted to the chip yield. A robust design and a very well controlled process can reduce the defect level in the memory, but unfortunately in the newer technologies as the gate lengths shrink the defect level goes beyond the control of process and the design as well.
Typically the interfaces which have' being used to test the memory in the current methodologies, add a lot on the input of the memory as well as they don't penetrate much inside the memory hierarchy to increase the observability.
However, the conventional memory interface circuits are additional overheads to the memory. They add some extra timing overhead as well. Further, as these interfaces are not embedded inside the memory, it adds on to the cost of plugging it with the memory and add on to the difficulty of measuring the timing defects between the system flip flops. It is therefore very difficult to predict that whether the fault is in the memory or is it at the interface.
US Patent No. 6,044,481 illustrates a conventional interface for testing memories. The interface comprises a plurality of programmable input pins and output pins besides a logic interfacing means for connecting external signals to the plurality of programmable input and output pins. The external signals are processed by the logic interfacing means and then communicated to a plurality of memory connection pins that couple up to the memory device. The logic component means is capable of being configured in
accordance with one or more memory testing methodologies including a serial built-in-self-test (BIST), a parallel built-in-self-test (BIST), a parallel test, a serial test, and a scan test. The configuring is performed by selectively interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface means in a test mode that operates in one or more memory testing methodologies or a mission mode. The invention disclosed by the aforementioned patent does not take into account area constraints for a typical System on Chip design.
Further, the conventional interfaces, which are being used to test the memory in the current methodologies, add a lot on the input of the memory and they do not penetrate much inside the memory hierarchy to increase the observability. The memory interfaces, which have been proposed and are being used lack the following properties.
In case of multiple memory structure in a chip, it may add on to the complexity by adding multiple test interface structure.
A need is therefore felt for a minimal area and high-speed integrated scan interface for testing memories that minimizes the timing faults of the testing system.
Object and summary of the Invention
It is an object of the present invention to provide a scanable test interface for testing and debugging failing memory on a System- on- Chip
It is another object of the present invention to convert the latched interface into a flip-flop interface during test/scan mode.
It is yet another object of the present invention to measure the timing defects between the latches of the interface to thereby enhance the observation of the system for test and debugging.
It is further an object of the present invention to capture high-speed patterns at the input of the system so that speed binning is possible at the memory interface.
To achieve the aforementioned objectives the present invention provides an integrated scanable interface for testing memory, comprising:
- a selection means for selecting a signal from at least two input signals responsive
to an activation signal;
a first means coupled to said selection means for storing said signal responsive to a
first enable signal and generating an output signal for the memory; said first means
being connected at the input node of the memory, and
a second means coupled to said first means for storing said output signal
responsive to a second enable signal and generating a test signal for testing the
memory,
- said output signal being observed for debugging faults between the integrated
scanable interface and the memory and for debugging faults between said first and
second means.
Further, the present invention provides a method for testing memory by using an integrated scanable interface, said method comprising steps of:
selecting a signal by a selection means from two input signals responsive to an activation signal;
- storing said signal in a first means responsive to a first enable signal;
- generating an output signal;
- observing said output signal for debugging faults between the integrated interface and memory;
storing said output signal in a second means responsive to a second enable signal; producing a test signal from said second means for testing the memory; and observing said output signal for debugging faults between said first and second means.
The present invention also provides a memory device comprising: a plurality of storage cells for storing data;
an address decoding means for receiving an address value and selecting cells from said plurality of storage cells corresponding to said address value;
an input means for storing data in said plurality of storage cells; an output means that outputs data from said plurality of storage cells; a control means for enabling said address decoding means, input means and output means; and
a high speed scan chain interface receiving enabling signals from said control means and coupled to said address decoding means, input means and output means for providing high-speed and minimal area testing of the memory device.
It can be therefore seen that the overall gain is in terms of memory area, where half latch, which is already available at the memory interface, is used to make a scanable Flip-Flop. The same scanable Flip-Flop can be used in different configurations to test and debug the memory for the functional as well as timing failures, within the memory or at its interface.
Brief description of the accompanying drawings
The present invention will now be described with reference to the accompanying
drawings.
Figure 1 illustrates a latch according to the instant invention.
Figure 2 illustrates a high-speed integrated interface for testing memory in accordance with the present invention.
Figure 3 illustrates a high-speed scan chain interface for testing memory according to an embodiment of the present invention.
Detailed Description
The instant invention targets a new high-speed interface for testing and debugging the embedded memories. This interface does not change the timing of the Inputs/Outputs or the memory as well as is seamlessly integrated into the original memory Inputs/Outputs. The basic idea behind such an interface is first to use the latch on the memory input, and subsequently converting the latch to a scan flip-flop.
Figure 1 shows a schematic diagram of latch in accordance with the present invention. As illustrated in the figure, the latch comprises a tri-state inverter connected to a test input signal D-system. A test control signal CKBAR is applied to the tri-state inverter. The output of the tri-state inverter is fed to a pair of logical elements connected in a closed loop. The pair of logical elements comprises a logic inverter and a tri-state inverter connected in series. The tri-state inverter receives a control signal CK, which is the inversion of the signal CK. Eventually; the output, D-Latched from said pair of logical elements is used for observing any timing faults in signal propagation between the latches.
Figure 2 shows the conversion of a latch interface into a scanable flip-flop integrated interface. It includes a pair of tri-state inverters receiving test signals D-scan and D-system and receiving test control signals TEST and TESTBAR respectively. On applying the control signals one of the D-scan or D-system input signals is selected and is applied to the input of a first latch, which has a structure similar to the latch illustrated in figure 1. The latch, which is a slave stage, is further coupled at its output to a second latch to form a scanable flip-flop interface. The test control signals applied to said second latch are CK and CKBAR, wherein CK is applied to the tri-state inverter and CKBAR is applied to the pair of logic elements. The output of the first latch, D-Latched is fed to the
memory to detect any timing failure between the latches and to subsequently detect failures between flip- flops of the scan chain integrated interface.
It can be seen from figure 2 that all the latched inputs at the memory 10 level are first converted to the flip-flops by adding a slave stage, which is enabled through out the normal memory operation. Using the scan chain configuration the value at the D-Latched outputs going to the memory can anytime be observed, thus providing a very good capability of debugging any fault on this interface. The observability at the D-System input also increase as the value at these inputs can be directly captured into these inputs as well as scan out through the scan chain. Any timing faults at these inputs can also be captured by generating the transition fault detection patterns or path delay test patterns, using any Automatic Test Pattern Generation tool. The clock that latches the Master Latch has to be the same as the clock that latches the slave. Thus, a multiplexer has to be put in the memory clock path, which adds a hold in the memory, but that can be compensated by the existing delay in the setup path of the memory.
Figure 3 shows the formation of a scan chain by interconnecting a plurality of integrated interfaces. Referring to figure 3, it can be seen that the outputs DO-Latched, Dl-Latched, D2-Latched are generated for debugging any timing faults in the scan chain that is significant in distinguishing between the fault in memory and the integrated interface. The inputs to the first scan flip-flop being D_Scan (DO) and D_System that generates DO-Latched and D_Test, wherein D_Test is further connected to the DScan input of the second scanable flip-flop. The other input to the second flip-flop is Dl at D_System that generates outputs Dl_Latched and D_Test. Similarly, the outputs from the final flip-flop are D2-Latched and D_Test, wherein D_Test is finally applied for testing failing memory on SoC. The control signals applied to each flip-flop are the clock signal CK and a reset signal RSTN. It can be therefore seen that the path delay faults and the transition fault model can be used to detect timing related defects on the paths at these inputs.
By using the integrated scanable interface on the memory, the testing of memory becomes easier as the memory internal pins can be accessed through the scan chains formed using this interface. The scan chains formed are made by using the existing memory interface, which saves a lot of area and does not put extra impact on the setup -hold of the memory. When it comes to debugging, then also it helps to debug by generating a signal to detect whether the memory is failing due to setup-hold times or there is a hard failure in the memory. The interface is used to capture high-speed input patterns at D-System, so that the speed binning is possible at the memory interface.
Thus, there is no extra timing impact on the memory timings as such. Furthermore, when the block is seamlessly integrated into the memory interface, the delays are very less. The same interface can be built up using pass gate multiplexers and there can be other methodologies of building the logic. Using this Flip-Flop interface, a Psuedo-Random Pattern generation can be done. Even these flip-flops can also be used to latch the memory outputs, to make the output of the memory observable or to they can be used a MISR (Multiple Input Signature Register) to compress memory data. There can be multipurpose usage of these flip-flops at the address inputs also. They also can be turned into Linear Feedback Shift Registers to generate Psuedo random pattern generators, as well as some incrementor or decrementors can be derived from the scanable flip-flops to actually write a known pattern on the memory to test it.

We Claim:
1. An integrated scanable interface for testing memory, comprising:
a selection means for selecting a signal from at least two input signals
responsive to an activation signal;
a first means coupled to said selection means for storing said signal
responsive to a first enable signal and generating an output signal for the
memory; said first means being connected at the input node of the
memory; and
a second means coupled to said first means for storing said output signal
responsive to a second enable signal and generating a test signal for testing
the memory;
said output signal being observed for debugging faults between the
integrated scanable interface and the memory and for debugging faults
between said first and second means.
2. An integrated scanable interface for testing memory as claimed in claim 1, wherein said selection means comprising at least two tri-state inverters.
3. An integrated scanable interface for testing memory as claimed in claim 1, wherein said first means is a latch.
4. An integrated scanable interface for testing memory as claimed in claim 1, wherein said second means is a latch.
5. A method for testing memory by using an integrated scanable interface, said method comprising steps of:
selecting a signal by a selection means from two input signals responsive to an activation signal;
storing said signal in a first means responsive to a first enable signal; generating an output signal;
observing said output signal for debugging faults between the integrated
interface and memory;
storing said output signal in a second means responsive to a second enable
signal;
producing a test signal from said second means for testing the memory;
and
observing said output signal for debugging faults between said first and
second means.
6. A high-speed scan chain interface for testing memory having at least two highspeed interfaces for testing memory, each high-speed interface comprising:
a selection means for selecting a signal from at least two input signals
responsive to an activation signal,
a first means coupled to said selection means for storing said signal
responsive to a first enable signal and generating an output signal for the
memory; said first means being connected at the input node of the
memory; and
a second means coupled to said first means for storing said output signal
responsive to a second enable signal and generating a test signal for testing
the memory;
said output signal being observed for debugging faults between the
integrated scanable interface and the memory and for debugging faults
between said first and second means.
7. A memory device comprising:
a plurality of storage cells for storing data;
an address decoding means for receiving an address value and selecting
cells from said plurality of storage cells corresponding to said address
value;
an input means for storing data in said plurality of storage cells,
an output means that outputs data from said plurality of storage cells;
a control means for enabling said address decoding means, input means and output means; and
a high speed scan chain interface receiving enabling signals from said control means and coupled to said address decoding means, input means and output means for providing high-speed and minimal area testing of the memory device.
8. A memory device as claimed in claim 7, wherein said high speed scan chain
interface having at least two high-speed interfaces for testing memory, each high
speed interface comprising:
a selection means for selecting a signal from at least two input signals
responsive to an activation signal;
a first means coupled to said selection means for storing said signal
responsive to a first enable signal and generating an output signal for the
memory; said first means being connected at the input node of the
memory; and
a second means coupled to said first means for storing said output signal
responsive to a second enable signal and generating a test signal for testing
the memory;
said output signal being observed for debugging faults between the
integrated scanable interface and the memory and for debugging faults
between said first and second means.
9. A method for testing memory by using a high-speed interface substantially as
herein described with reference to and as illustrated by the accompanying
drawings.
10. An integrated scanable interface for testing memory substantially as herein
described with reference to and as illustrated by the accompanying drawings.