Claims:I/We claim
1. An integrated system for performing in-system programming of a hardware platform, wherein the system comprises of:
a means for selecting the hardware platform for configuring by performing in-system programming to suit with the desired application, wherein the hardware platforms includes:
a processor board;
a master FPGA board;
at least four Input/Output (IO) boards;
at least four FPGA’s;
a means for configuring a plurality of models for the selected hardware platform as per the requirement for performing in-system programming;
a means for partitioning the integrated hardware platform into a plurality of sub-systemsfor performing programming depending on the functionality;
a means for generating the synthesizable code for performing in-system programming through a plurality of coders;
a means for downloading the programmed code into one or more of the said sub-systems through a cable;
a means for packetizing the programmed code for downloading into the master FPGA board by loading the code into an SPI flash for performing the programming of master FPGA;
a means for real-time configuring of the IO boards through a PCI-e interface integrated in the master FPGA;
a means for processing and monitoring the real-time data in simulation environment through in-system programming;
a plurality of Simulink libraries integrated in an Integrated Development Environment (IDE) and integrated in a hardware platform for performing primary communication for reading the data and transferring the data through a read model and write model respectively from each channel of each sub-system; and
wherein each library further comprises of a plurality of modules.

2. The models according to claim 1, characterized for performing in-system programming, wherein includes a plurality of simulation software’s include but not limited to:
SIMULINK;
MATLAB;
QNX RTOS;
Eclipse IDE;
Visual basic or any other compilation tool;
Xilinx System Generator; and
Xilinx Synthesis Tool etc. or the like.

3. The integrated system according to claim 1, characterized to be generate the synthesized code through a plurality of coders, wherein the coders includes:
embedded coder/QNX for generating .bin file; and
HDL coder for generating .bit file.

4. The integrated system according to claim 1, characterized for downloading the programmed code into the processor board through an Ethernet.

5. The processing according to claim 1, characterized to be attained in the processor board or master FPGA board based on the design of the hardware platform.

6. The integrated platform according to claim 1, characterized for configuring the master FPGA and the IO boards is attained through a JTAG programming interface.

7. The code generation according to claim 1, characterized for using various programming techniques include but not limited to:
HDL coder;
C/C++ coder;
QNX compilation code;
Xilinx;
.bin file generation; and
.bit file generation.

8. The IDE Simulink libraries according to claim 1, characterized for primary communication for reading the data and transferring the data in read model and write model, wherein the libraries includes:
board HP library comprising at least 33 modules;
board B library comprising at least 29 modules;
board C library comprising at least 36 modules;
board D library comprising at least 25 modules;
masterFPGA interface library comprising at least 4 modules, wherein includes:
PCI-e interface;
Ethernet interface;
DDR2 interface;
Clock interface; and
processor interface library.

9. The hardware platform Simulink libraries according to claim 8, characterized for comprising a plurality of controllers for performing hardware specific programming by communication with the IDE, wherein includes:
processor board library;
master FPGA library;
board HP library;
board B library;
board C library;
board D library;
monitor libraries; and
server and client system libraries.

10. An integrated interface system for programming the hardware platform in whole or its components through a JTAG programming interface, wherein the system comprises of:
a means for creating at least one project for at least one hardware platform for synthesizing;
a means for generating a .bit file for at least one of the FPGA’s;
a means for initiating the download of the software program for generating the .mcs files;
a means for packetizing the .mcs file into UDP packets for transferring to a processor board through an Ethernet;
a means for storing the Ethernet packets received in an SDRAM;
a means for transferring the stored packets to master FPGA through PCI-e interface for performing IO board programming; and
a means for programming into at least four FPGA’s through an SPI programming interface.

11. The UDP packets according to claim 10, characterized for comprising a header for carrying include but not limited to:
an identification header for each FPGA;
a packet number for identifying each data packet of the file to be downloaded;
an IP address of the destination;
an IP address of the source;
a port number;
a length of the data inserted in a single packet;
a check sum error;
a start of a packet sequence;
an end of a packet sequence; and
type of configuration whether command or code.

12. The system according to claim 10, characterized for performing FPGA programming through SPI programming interface, wherein consists of:
a means for the FPGA in master SPI mode for performing programming;
a means for generating the clock pulses after releasing the .bin pin for providing READ COMMAND to SPI flash; and
a means for changing the clock register settings the system generates corresponding clock for reading the data and triggering the DONE pin for indicating the completion of FPGA programming.

13. The system according to claim 10, characterized to control the SPI interface by the master FPGA.

14. An integrated method for performing real-time simulation of in-system programming of a hardware platform, wherein the method comprises of:
selecting the hardware platform for configuring by performing in-system programming to suit with the desired application, wherein the hardware platforms including:
a processor board;
a master FPGA board;
at least four Input/Output (IO) boards;
at least four FPGA’s;
configuring a plurality of models for the selected hardware platform as per the requirement for performing in-system programming;
partitioning the integrated hardware platform into a plurality of sub-systems for performing programming depending on the functionality;
generating the synthesizable code for performing in-system programming through a plurality of coders;
downloading the programmed code into one or more of the said sub-systems through a cable;
packetizing the programmed code for downloading into the master FPGA board by loading the code into an SPI flash for performing the programming of master FPGA;
configuring real-time of the IO boards through a PCI-e interface integrated in the master FPGA;
processing and monitoring the real-time data in simulation environment through in-system programming;
integrating of a plurality of Simulink libraries in an Integrated Development Environment (IDE) and integrated in a hardware platform for performing primary communication for reading the data and transferring the data through a read model and write model respectively from each channel; and
providinga plurality of modules for each channel.

15. The method according to claim 14, wherein performs in-system programming through a plurality of simulation software’s include but not limited to:
SIMULINK;
MATLAB;
QNX RTOS;
Eclipse IDE;
Visual basic or any other compilation tool;
Xilinx System Generator; and
Xilinx Synthesis Tool etc. or the like.

16. The method according to claim 14, wherein uses an Ethernet for downloading the programmed code into the processor board and a PCI-e interface for communicating.

17. The method according to claim 14, wherein uses JTAG programming interface for configuring the master FPGA and IO boards.

18. The method according to claim 14, wherein generated code through a various programming techniques includes:
HDL coder;
C/C++ coder;
QNX compilation code;
Xilinx;
.bin file generation; and
.bit file generation.

19. The method according to claim 15, wherein the IDE Simulink libraries for attaining primary communication for reading the data and transferring the data in read model and write model, wherein the includes:
board HP library comprising at least 33 modules;
board B library comprising at least 29 modules;
board C library comprising at least 36 modules;
board D library comprising at least 25 modules;
master FPGA interface library comprising at least 4 modules, wherein includes:
PCI-e interface;
Ethernet interface;
DDR2 interface;
Clock interface; and
processor interface library.

20. The method according to claim 15, wherein the hardware platform Simulink libraries comprising a plurality of controllers for performing hardware specific programming by communication with the IDE, wherein includes:
processor board library;
master FPGA library;
board HP library;
board B library;
board C library;
board D library;
monitor libraries; and
server and client system libraries.
, Description:Technical Field of the Invention

[0001] Present invention relates to a system for performing in-system programming. More particularly, the present invention relates to a method for performing in-system programming of a hardware platform suitable for a desired application.

Background of the Invention

[0002] Generally, hardware simulation is used to improve cost and safety factors. Software models of the hardware components are cheaper and easy to handle for controlling and monitoring purposes. The simulated system provides flexibility of the system at border line conditions without damaging hardware components. This interfacing of the control system with the simulation model is attained through a set of input-output (“I/O”) commands for simulating responses of the control system and referred as Hardware-In-The-Loop (“HIL”) simulation.

[0003] However, the simulated components may not be operated in real-time. Therefore, a simulation may diverge from the actual response of the controller with a real time model. Furthermore, commercially available software modeling packages used for simulation models have response times that do not minimize the latency for certain modeling demands.

[0004] Therefore, there exists a need to develop a system and a method for performing in-system programming a hardware platform for performing both high speed and low speed simulations based on the requirements.

Brief Summary of the Invention

[0005] The present invention recognizes the limitations of the prior art and the need for systems and methods that are able to provide assistance to users in a manner that overcomes these limitations.

[0006] A principle object of the present invention is to provide an integrated system for performing in-system programming of a hardware platform.

[0007] Another object of the present invention is to select a hardware platform for performing in-system programming to suit with the desired application.

[0008] According to a first aspect of the present invention, an integrated system for performing in-system programming of a hardware platform is disclosed. The system comprises of a means for selecting the hardware platform for configuring by performing in-system programming to suit with the desired application. The hardware platform includes a processor board, a master FPGA board, at least four Input/ Output (IO) boards and at least four FPGA’s for configuring a plurality of models for the selected hardware platform as per requirement for performing in-system programming and partitioning the integrated hardware platform into a plurality of sub-systems for performing programming depending on the functionality.

[0009] In accordance with the first aspect of the present invention, further the system generates a synthesizable code for performing in-system programming through a plurality of codes for downloading the programmed code into one or more sub-systems through a cable. The programmed code is packetized for downloading into the master FPGA board by loading the code into an SPI flash for performing the programming of master FPGA and for real time configuring of the IO boards through a PCI-e interface integrated in the master FPGA.

[0010] In accordance with the first aspect of the present invention, further the system also comprises the real-time data for processing and monitoring in simulation environment through in-system programming. A plurality of Simulink libraries are integrated in an Integrated Development Environment (IDE) and then integrated in a hardware platform for performing primary communication for reading data and transferring data through a read model and write model respectively from each channel of each sub-system and each library further comprises of a plurality of modules.

[0011] In accordance with the first aspect of the present invention, the system further comprises models for performing in-system programming. The models include a plurality of simulation software’s include but not limited to SIMULINK, MATLAB, QNX RTOS, Eclipse IDE, Visual basic or any other compilation tool, Xilinx System Generator and Xilinx Synthesis Tool etc. or the like.

[0012] In accordance with the first aspect of the present invention, wherein the integrated system generates the synthesized code through a plurality of coders. The coders include embedded coder/QNX for generating .bin file and HDL coder for generating .bit file and downloading the programmed code into the processor board through an Ethernet.

[0013] In accordance with the first aspect of the present invention, further the processing is characterized to be attained in the processor board or master FPGA board based on the design of the hardware platform.

[0014] In accordance with the first aspect of the present invention, the integrated platform is characterized for configuring the master FPGA and the IO boards is attained through a JTAG programming interface.

[0015] In accordance with the first aspect of the present invention, the code generation is characterized to use various programming techniques including but not limited to HDL coder, C/C++ coder, QNX compilation code, Xilinx, .bin file generation and .bit file generation.

[0016] In accordance with the first aspect of the present invention, the IDE Simulink libraries is further characterized for primary communication for reading data and transferring data in read model and write model. The libraries includes board HP library comprising at least 33 modules, board B library comprising at least 29 modules, board C library comprising at least 36 modules, board D library comprising at least 25 modules, master FPGA interface library comprising at least 4 modules wherein includes PCI-e interface, Ethernet interface, DDR2 interface, Clock interface and processor interface library.

[0017] In accordance with the first aspect of the present invention, the hardware platform Simulink libraries comprises a plurality of controllers for performing hardware specific programming by communication with the IDE includes processor board library, master FPGA library, board HP library, board B library, board C library, board D library, monitor libraries and
server and client system libraries.

[0018] According to a second aspect of the present invention, an integrated interface system for programming the hardware platform in whole or its components through a JTAG programming interface is disclosed. The system comprises a means for creating at least one project for at least one hardware platform for synthesizing and a means for generating a .bit file for at least one of the FPGA’s.

[0019] In accordance with the second aspect of the present invention, the system further comprises a means for initiating to download the software program for generating the .mcs files and a means for packetizing the .mcs file into UDP packets for transferring to a processor board through an Ethernet.

[0020] In accordance with the second aspect of the present invention, further the system comprises a means for storing the Ethernet packets received in an SDRAM, a means for transferring the stored packets to master FPGA through PCI-e interface for performing IO board programming and a means for programming into at least four FPGA’s through an SPI programming interface.

[0021] In accordance with the second aspect of the present invention, the UDP packets comprises a header for carrying include but not limited to an identification header for each FPGA, a packet number for identifying each data packet of the file to be downloaded, an IP address of the destination, an IP address of the source, a port number, a length of the data inserted in a single packet, a check sum error, a start of a packet sequence, an end of a packet sequence and type of configuration whether command or code.

[0022] In accordance with the second aspect of the present invention, the system is characterized for performing FPGA programming through SPI programming interface. The system consist of the FPGA in master SPI mode for performing programming, generating the clock pulses after releasing the .bin pin for providing READ COMMAND to SPI, changing the clock register setting the system generates corresponding clock for reading the data and triggering the DONE pin for indicting the completion of FPGA programming and control the SPI interface by the master FPGA.

[0023] According to a third aspect of the present invention, an integrated method for performing real-time simulation of in-system programming of a hardware platform is disclosed. The method comprises of selecting the hardware platform for configuring by performing in-system programming to suit with the desired application. The hardware platform including a processor board, a master FPGA board, at least four Input/ Output (IO) boards, at least four FPGA’s for configuring a plurality of models for the selected hardware platform as per the requirement for performing in-system programming and portioning the integrated hardware platform into a plurality of sub-system for performing programming depending on the functionality.

[0024] In accordance with the third aspect of the present invention, further the method comprises of generating the synthesizable code for performing in-system programming through a plurality of coders, downloading the programmed code into one or more of the sub-systems through a cable and packetizing the programmed code for downloading into the master FPGA by loading the code into an SPI flash performing the programming of master FPGA.

[0025] In accordance with the third aspect of the present invention, further also the method comprises steps of configure real-time of the boards through a PCI-e interface integrated in the master FPGA and processing and monitoring the real-time data in simulation environment through in-system programming. Integrating of a plurality of Simulink libraries in an Integrated Development Environment (IDE) and integrated in a hardware platform for performing primary communication for reading the data and transferring the data through a read model and write model respectively from each channel and providing a plurality of modules for each channel.

[0026] In accordance with the third aspect of the present invention, the method performs in-system programming through a plurality of simulation software’s include but not limited to SIMULINK, MATLAB, QNX RTOS, Eclipse IDE, Visual basic or any other compilation tool, Xilinx System Generator and Xilinx Synthesis Tool etc. or the like and uses an Ethernet for downloading the programmed code into the processor board and a PCI-e interface for communication. JTAG programming used interface for configuring the master FPGA and IO boards.

[0027] In accordance with a third aspect of the present invention, the generated code through a various programming techniques includes HDL coder, C/C++ coder, QNX compilation code, Xilinx, .bin file generation and .bit file generation.

[0028] In accordance with the third aspect of the present invention, the IDE Simulink libraries for attaining primary communication for reading data and transferring data in read model and write model wherein includes board HP library comprising at least 33 modules, board B library comprising at least 29 modules, board C library comprising at least 36 modules, board D library comprising at least 25 modules, master FPGA interface library comprising at least 4 modules, wherein includes PCI-e interface, Ethernet interface, DDR2 interface, Clock interface and processor interface library.

[0029] In accordance with the third aspect of the present invention, wherein the hardware platform Simulink libraries comprises a plurality of controllers for performing hardware specific programming by communication with the IDE includes processor board library, master FPGA library, board HP library, board B library, board C library, board D library, monitor libraries and server and client system libraries.

Brief Description of the Drawings

[0030] Various objects and advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments, in conjunction with the accompanying drawings, wherein like reference numerals have been used to designate like elements, and wherein

FIG. 1 illustrates a block diagram depicting the process of in-system programming of integrated development environment (IDE) according to the present invention.

FIG. 2 illustrates a flow chart depicting a step by step process of real time simulation of in-system programming of hardware platform according to the present invention.

FIG. 3 illustrates a block diagram depicting a master FPGA programming through an SPI according to the present invention.

FIG. 4 illustrates a block diagram depicting Input/ Output board programming through backplane architecture according to the present invention.

FIGS. 5a-5l illustrate screenshots of a user interface for selecting desired hardware platform and performing in-system programming according to the present invention.

FIGS. 6a-6f illustrates screenshots of a user interface for performing in-system programming according the present invention.

Detailed Description of the Invention

[0031] The present invention is directed towards an integrated system and method for performing real-time simulation of in-system programming of a hardware platform. Referring to the drawings, wherein like reference numerals designate identical or corresponding systems, preferred embodiments of the present invention are described.

[0032] An integrated system for performing in-system programming of a hardware platform to suit with the desired application. The hardware device is configured and selected for plurality of models as per the requirement. The hardware platform is partitioned for generating the code through coders and downloaded into processor board through an Ethernet. The master FPGA board by loading the code into an SPI flash for performing the programming of master FPGA.

[0033] The IDE Simulink libraries such as board HP, board B, board C and board D are used for primary communication to read data and transfer data in read model and write model. The hardware Simulink libraries comprise a plurality of controllers for performing hardware specific programming by communicating with IDE.

[0034] Referring to drawings, FIG. 1 illustrates a block diagram 100 depicting the process of in-system programming of integrated development environment (IDE) according to the present invention. An integrated development platform (IDE) 102 provides access to all the in-system programming of hardware platform 126. The hardware platform 126 such as a processor board, a master FPGA board, at least four FPGA’s and at least four Input/ Output boards (IO) is selected for configuring 104 by performing in-system programming to suit with the desired application. The model 106 for performing in-system programming for the selected hardware platform 126 as per the requirement include but not limited to Simulink, MATLAB, QNX RTOS, Eclipse IDE, Visual basic or any other compilation tool, Xilinx System Generator and Xilinx Synthesis Tool etc. The hardware platform 126 is partitioned 108 into sub-systems for performing the programming depending on the functionality.

[0035] A synthesizable code is generated 110 through coders for performing programming includes embedded coder/QNX for generating .bin file and HDL coder for generating .bit file and the techniques for code generation HDL coder, C/C++ coder, QNX compilation code, Xilinx, and .bit file generation. The programmed code is downloaded 112 into one or more hardware sub-systems such as processor board 114 through a cable such as Ethernet interface and processing is done on the processor board 114 or the downloading is done on a master FPGA 116 based on the design of the hardware platform 126. The packetized programmed code for downloading into master FPGA board 116 by loading the code into SPI flash (not shown) for performing the programming of the master FPGA 116.

[0036] The downloaded code into the master FPGA 116 is coded into IO boards such as HP board 118, board B 120, board C 122 and board D 124. A plurality of Simulink libraries are integrated in a hardware platform for primary communication and comprising a plurality of controllers for performing hardware specific programming by communication with Integrated Development Environment (IDE) 102 includes processor board library, master FPGA library, board HP library, board B library, board C library, board D library, monitor libraries and server and client system libraries.

[0037] FIG. 2 illustrates a flow chart 200 depicting a step by step process of real time simulation of in-system programming of hardware platform according to the present invention. Integrated development platform (IDE) 202 provides access to all the in-system programming of hardware platform. The hardware platform such as a processor board, a master FPGA board, at least four FPGA’s and at least four Input/ Output boards (IO) is selected for configuring the device 104 by performing in-system programming to suit with the desired application. The model 206 for performing in-system programming for the selected hardware platform as per the requirement include but not limited to Simulink, MATLAB, QNX RTOS, Eclipse IDE, Visual basic or any other compilation tool, Xilinx System Generator and Xilinx Synthesis Tool etc. The hardware platform is partitioned 108 into sub-systems for performing the programming depending on the functionality.

[0038] The synthesizable code is generated 210 through coders for performing programming includes embedded coder/QNX 230 for generating .bin file 232 and HDL coder 234 for generating .bit file 238 and the techniques for code generation uses C/C++ coder 228 and compiled in compilation code 230, generate .bin file 232. And HDL coder 234 and compiled in Xilinx 236 generate .bit file 238. The programmed code is downloaded into one or more sub-systems such as processor board 214 through a cable such as Ethernet and the processing is done on the processor board 214 master FPGA 216 is based on the design of the hardware platform. The packetized programmed code for downloading into master FPGA board 216 by loading the code into SPI flash 240 to configure IO boards for performing the programming of the master FPGA 216.

[0039] The configured hardware plat form or its components are programmed through JTAG programming. JTAG programming comprises one project for hardware platform for synthesizing the code for generating a .bit file for one of FPGA’s. The .mcs file is generated by initiating the downloading of the software programmed. The downloaded .mcs file is packetized into UDP packets for transferring to a processor board 214 through an Ethernet. The UDP packets comprises header for include but not limited to an identification header for each FPGA and packet number for identifying each data packet of the file to be download, an IP address of the destination, an IP address of the source, a port number, a length of the data inserted in a single packet, a check sum error, a start of a packet sequence, an end of a packet sequence and type of configuration whether command or code. These Ethernet packets are stored in SDRAM for transferring to master FPGA 216 through PCI-e interface for performing IO board programming and SPI programming interface 240 for programming into four FPGA’s such as card HP 218, card B 220, card C 222 and card 224. The four FPGA’s are communicated with master FPGA 216 through back plane architecture 242.

[0040] The FPGA programmed through SPI interface 240 for the FPGA in master SPI mode for performing programming. The FPGA programming generating the clock pulse after releasing the .bin pin for providing READ COMMAND to SPI flash and changing the clock register settings the system generates corresponding clock for reading the data and triggering the DONE pin for indicating the completion of FPGA programming. The SPI interface 240 for programming the FPGA is controlled by the master FPGA 216. The real time programming of IO boards are integrated with master FPGA 216 through PCI-e interface.

[0041] The Simulink libraries integrated in an Integrated Development Environent (IDE) 202 and integrated for primary communication for reading the data and transferring the data in read model and write model includes board HP library comprising at least 33 modules, board B library comprising at least 29 modules, board C library comprising at least 36 modules, board D library comprising at least 25 modules, master FPGA interface library comprising at least 4 modules, wherein includes PCI-e interface, Ethernet interface, DDR2 interface, Clock interface and processor interface library. The Simulink libraries integrated in a hardware platform for primary communication and comprising a plurality of controllers for performing hardware specific programming by communication with Integrated Development Environment (IDE) 202 includes processor board library, master FPGA library, board HP library, board B library, board C library, board D library, monitor libraries and server and client system libraries.

[0042] FIG. 3 illustrates a block diagram 300 depicting FPGA programming through SPI according to the present invention. The FPGA 316 is configured in SPI serial flash mode 340 for performing programming. FPGA 316 generates clock and give READ COMMAND to SPI flash. Clock register settings changes FPGA 316 generates corresponding clock for reading the data and triggers DONE pin for indicating the completion of FPGA 316 programming.

[0043] FIG. 4 illustrates a block diagram 400 depicting Input/ Output board programming through back plane architecture according to the present invention. The Io programming comprises four IO boards. Back plane architecture 442 and master FPGA 416. The four FPGA’s 418, 420, 422 and 424 are communicating with master FPGA 416 through back plane architecture 442. The IO board programming is attained through JTAG programming interface. JTAG programming comprises one project for hardware platform for synthesizing the code for generating a .bit file for four FPGA’s 442, FPGA 444, FPGA 446, FPGA 448. The .mcs file is generated by initiating the downloading of the software programmed. The downloaded .mcs file is packetized into UDP packets for transferring to a processor board 114 through an Ethernet.

[0044] The FPGA 442 programmed through SPI interface 440 for the FPGA in master SPI mode for performing programming. The FPGA 442 programming generating the clock pulse after releasing the .bin pin for providing READ COMMAND to SPI flash 440 and changing the clock register settings the system generates corresponding clock for reading the data and triggering the DONE pin for indicating the completion of FPGA 442 programming. The SPI interface 440 for programming the FPGA 442 is controlled by the master FPGA 416. The real time programming of IO boards are integrated with master FPGA 416 through PCI-e interface. Similarly, the programming process as follows for remaining FPGA’s such as FPGA 444, FPGA 446, FPGA 448.

[0045] FIG. 5a illustrates a screen shot 500a depicting controller development platform is integrated with integrated development environment according to the present invention. When clicked on controller development platform the main window of integrated development environment pop up shown.

[0046] FIG. 5b illustrates a screen shot 500b depicting pop up window of controller development platform according to the present invention. The pop up window is a integrated development environment interface for performing programming. Under the tool menu an option of hardware setting is present for selecting the desired hardware.

[0047] FIG. 5c illustrates a screen shot 500c depicting the hardware platform database according to the present invention. The hardware database platform comprises a processor board, a master FPGA board, four Input/Output (IO) boards and four FPGA’s.

[0048] FIG. 5d illustrates a screen shot 500d depicting the hardware tool menu for selecting the desired hardware according to the present invention. The hardware setting option will helps to select the desired hardware and also helps to control several features of the code generation.

[0049] FIG. 5e-5h illustrates a screen shot 500e depicting the required hardware selection and device configuration according to the present invention. The hardware is configured the functionalities of the window is opened. The hardware processor board is selected; the model for performing the programming for specific device is configured. The models include but not limited to SIMULINK, MATLAB, QNX RTOS, Eclipse IDE, Visual basic or any other compilation tool, Xilinx System Generator and Xilinx Synthesis Tool etc. or the like. Similarly, FIG. 5f and FIG. 5g the hardware device FPGA and both are configured. We enable configure button on the function window, a new window configure open where we configure the device.

[0050] FIG. 5i illustrates a screen shot 500i depicting the SIMULINK libraries according to the present invention. A new configures window opens and access the SIMULINK libraries which comprises new models required for the sub systems by selecting particular library.

[0051] FIG. 5j illustrates a screen shot 500j depicting a command window data in text format according to the present invention. The command window data in text format in the configure window and we will see the implementation flow.

[0052] FIG. 5k illustrates a screen shot 500k depicting user interface can help in partitioning the boards according to the present invention. The boards are partitioned in this window depending on the functionality. The programmed code is downloaded into one or more sub systems through an Ethernet.

[0053] FIG. 5l illustrates a screen shot depicting hardware setting window for different applications according to the present invention. Hardware setting window provides hardware creation for desired application and code generation. The code is generated through coders includes HDL coder, C/C++ coder, QNX compilation code, Xilinx, .bin file generation and .bit file generation.

[0054] FIG. 6a-6b illustrates a screen shot 600a depicting code generation window according the present invention. The controller development platform provides code generation options and is interface with integrated development environment. The controller development platform comprises four sub options comprises create interface, create FPGA test, create host table and create application for implement specific operation.

[0055] FIG. 6c illustrates a screen shot 600c depicting .bin file creation according to the present invention. The code is generated through coders for performing programming. The coders generated .bin file.

[0056] FIG. 6d illustrates a screen shot 600d depicting .bit file creation according to the present invention. The code is generated through coders for performing programming and generate .bit file.

[0057] FIG. 6e illustrates a screen shot 600e depicting SIMULATION for the selected hardware according to the present invention. The model is selected for the configured device as per the requirement. The model includes SIMULINK, MATLAB, QNX RTOS, Eclipse IDE, Visual basic or any other compilation tool, Xilinx System Generator and Xilinx Synthesis Tool etc. or the like.

[0058] FIG. 6f illustrates a screen shot depicting the download code through a cable according to the present invention. After completing the simulation the programmed code is downloaded into one or more sub systems such as processor board through Ethernet.

[0059] A detailed description of the above embodiment of the present invention is only for ease of understanding and cited examples should not be construed as limiting the scope of the invention. Any person skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.