FIELD OF THE INVENTION The present invention pertains to the field of computer systems. More particularly, the present invention relates to a method and apparatus for controlling access to a register mapped to the input/output (I/O) address spnee of a computer systems so pe, innr siin, to protect the register. B ACKGROUND OF THE INVENTION Registers mapped to the I/O address space (termed I/O-mappiad registers) are commonly located within interfaces for interfacing between a computer system and a peripheral device. 1/O-mapped registers may also be located in a number of other functional units within a computer system, such as a bus bridge, and may be utilized for a number of functions, including data buffering, status indication and control and configuration functions. I/O-mapped registers are vulnerable to having their contents corrupted or undesirably altered in a number of ways, For example, a "berserk" or malfunctioning program, a virus program or even the operating system itself may attempt to alter Che contents of an 1/O-mapped register in an illegal manner. The corruption of the contents of an I/O-mapped register may have very serious consequences for the functioning of the computer system, and also for the physical integrity of the components and peripheral devices of the computer system. This vulnerability is particularly serious when the contents of an I/O-mapped register, performing a control or configuration function, are modified. At the very least, corruption of the register contents may result in a software failure. Ir a worst case scenario, such ar> where the 1/O-mnpped register stores a value relating to power management, corruption of the contents of the register may cause the processor to over-heat and bum. This worst case scenario poses a considerable threat to the integrity of computer system hardware and software, and even to the safety of a computer system user The vulnerability of I/O- mapped registers also provides authors of virus programs with the opportunity to write virus programs which cause untold mischief and disruption within a computer system. Prior art methods of providing access projection for an I/O-mapped register include providing a 'locking' mechanism whereby a lock/unlock value is written to a dedicated "lock" register associated with an I/O-mapped register. Prior to access of the I/Omapped register, a protection algorithm is executed which determines, by inspection of the "lock" register, whether the I/O-mapped register can be accessed. While this method provides relatively effective protection against an attempt by a malfunctioning program to access the I/O-mapped register, it does not provide adequate protection against an intelligent foe. such as virus program. The virus program may, for example, gain access to, and overwrite, the "lock" register, or may attack and bypass the protection algorithm. A microprocessor architecture (termed Intel Architecture) developed by Intel Corporation of Santa Clara, California, also provides protection mechanisms for I/O-mapped registers. Details of these protection mechanisms are provided m "Pentium® Processor User's Manual, Volume 3: Architecture and Programming Manual", published 1994, pages 12-1 to 12-8, and pages 15-5 to 15-9. Specifically, the Intel architecture makes provision for two I/O access protection mechanisms Under both protection mechanisms, an I/O access is checked in parallel with add)"ess translation tc determine whether it satisfies various protection requirements The first I/O protecdon mechanism recognizes four privilege levels, labeled 0 to 3, under the io-called "protection ring model". A program being executed by the processor has a privilege level, termed the Current Privilege Level (CPL), which is stored ir the lower two bits of the CS segment register. Access to I/O instructions, such as IN and OUT, by an application program is controlled by an Input/Output Protection Level (IOPL), which is compared to the CPL to determine whether the application program can validly access an I/O instruction. This protection mechanism generally allows the operating system, which has a privilege level of 0, and certain device drive rs, which have privilege levels of 1, to access I/O instructions, while blocking access to I/O instructions by applications, and Itss privileged device drivers, which have a privilege level of 3. However, this protection mechanism is not effective against a virus program that manages to obtain a privilege level of 0, or against a poorly written device driver having a level 1 privilege. The second I/O protection mechanism provides an I/O permission bit map which controls access to individual registers mapped to the I/O address space. This protection mechanism is an implementation of the ''locking" mechanism described above Briefly, each bin of the bir map corrspondence to an I/O register byte, and the relevant hit Is tested by the processor before accessing an I/O-mapped register, If the tested bit is set, a general-protection error is generated. On the other hand, if the test bit is net set, the 2/0 operation can proceed. However, this protection mechanism suffers; from the inadequacies detailed above with reference to "locking" mechanisms. The above protection mechanisms also suffer from the drawback of providing either complete access or denying any access to the 1/0 address space. This "all or nothing" approach is inflexible, and does not permit varying degrees or levels of protection to be afforded to an 1/0-mapped register. Finally, aside from the protection issue, it h desirable to facilitate more flexible use of I/O-nmpped registers. Such registers are typically limited to performing a single function and may, depending on the operating condition olf the computer system, comprise an under-utilized resource in certain scenarios, while there may exist a shortage of the re source provided by an 1/0-mapped register in another scenario, SUMMARY OF THE INVENTION According to a first aspect of the invention there is provided a method of providing access to an input/output (VO)-mappcd register of a computer system, the computer system including a processor operable in at least first and second operational modes. The method includes the steps of firstly receiving an access request to the I/O-mapped register. Logic circuitry associated with the J/O-mapped register then determines whether the processor is operating in the first mode, which may be a ssysrem management mode (SMM) If the logic circuitry determines that the processor is operating in the first mode, a first, umestricted type of access by the processor to the i/O-mapped register is provided. Alternatively, if the logic circuitry determines that the processor is operating in the second mode, a second, restricted type of access by the processor to the I/O-mapped register is provided. If the first, unrestricted type of access is provided to the processor, it performs an operation, on the cements of the I/O-mapped register, under the direction of code stored in a dedicated system management memory address space. The step of providing a fir*:i type of access may comprise providing at least read access to the I/O-mapped register, and the step of providing a second type of access may compose preventing access to the I/O-mnpped register. Alternatively, the step of providing a first type of access may comprise providing both read and write access to the I/O-mapped register, and the step of providing a second type of access may comprise providing only read access to the I/O-mapped register. According to a second aspect of the invention there is provided a method of controlling access to a register mapped to an input/output (I/O) address space within a computer system. The computer system defines u memory address space, the I/O address space, and a system management mode (SMM) memory address space. The computer system further includes a processor operable in a system management mode (SMM) in which the processor accesses the SMM memory address space. The method requires receiving a system management request at die processor, and then placing the processor in the system management made in response receiving the system managemnt request. Thereafter, the piccture is provided with a first type of access to the register, and performs an operation on the contents of the register. The processor is then placed out of the system management mode, and provided with a second type of access to the register According to a third aspect of the invention there is provided an interface arrangement for use in a computer system. The computer system is operable in first and second modes of operation. The interface arrangement includes a register mapped to an input/output (I/O) address open, a decoder having an input to receive address data identifying the register, and an output to provide ti select signal to the register, and logic circuitry configured to detect when the computer system is operating in the first mode, and configured to provide a first type of access to the register when the computer system is operating in the first mode, and to provide a second type of access ro the register when the computer system is not operating in the first mode. The invention extends to a computer system including an interface arrangement as described above. Other features of the present invention will be apparent ftnm the accompanying drawings and from the detailed description which follows. Accordingly the present invention relates to a method of providing access to an input/output (I/O)-mapped register 60 1-60 3 of a computer system 18, the computer system 18 including a processor 20 operable in first and second modes of operation, the method including the steps of* receiving a request for access to the I/0-mapped register 60 1-60 3, determining whether the processor 2 0 is operating in the first mode of operation, providing a first type of access to the I/0-mapped register 60 1-60 3 if the processor 20 is operating in the first mode of operation, and providing a second type of access to the I/O-mapped register 60 1-60 3 if the processor 20 is not operating in the first mode of operation. Accordingly the present invention also relates to an interface arrangement for use in a computer system 18, the computer system 18 being operable in first and second modes of operation, the interface arrangement comprising a register 70, 72, 90, 112, 114 mapped to an input/output (I/O) address space of the computer system 18, a decoder 74, 92, 116 having an input coupled to receive address data identifying the register 70, 72, 90, 112, 114 and an output coupled to output a select signal indicating that address data identifies the register 70, 72, 90, 112, 114, and logic circuitry 80, 94, 96, 98, 118, 120, 122 configured to detect when the computer system is operating in the first mode, and configured to provide a first type of access to the register 70, 72, 90, 112, 114 when the computer system is operating in the first mode; and to provide a second type of access to the register 70, 72, 90, 112, 114 when the computer system 18 is not operating in the first mode BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example in the figures of the accompaying drawings, in which like references indicate similar elements and in which: Figure 1 is a state diagram indicating the various modes of operation of a processor. Figure 2 is a block diagram showing a computer system in which the present invention may be realized. Figure 3A is a block diagram showing processor address spade when a processor is not operating in a system management mode. Figure 3B is a block diagram showing processor address space when a processor is operating in a system management mode. Figure 4 is a block diagram showing a computer system incorporating apparatus for controlling access to an l/O-mapped register according to the invention. Figure 5 is a block diagram showing a first embodiment of a circuit arrangement for controlling access la an l/O-mapped register according to the invention. Figure 6 is a block diagram showing a second embodiment of a circuit arrangement for controlling access to an 1/O-mapped register according to the invention. Figure 7 is a block diagram showing a third embodiment of a circuit arrangement for controlling access to an l/O-mapped register according to the invention Figure 8 is a flow-chiirt illustrating one embodiment of a method of controlling access to an I/O mapped register according to the invention Figure 9 is a flow-chart illustrating one embodiment of a method by which a processor obtains unrestricted access to an I/O-mappcd regisrer. Figure 10 is a diagrammatic representation of a system management random access memory (SMRAM) according to the invention. Figures 11A is a diagrammatic representation of the address spaces accessed by & processor in a prior art computer system. Figures I IB is a diagrammatic representation of the address spaces accessed by a processor in a computer system incorporating the present invention. DETAILED DESCRIPTION A method and apparatus for controlling access to a register mapped to in input/output (I/O) address space of a computer sysiem are described. In the following description, for purposes of explanation, numerous specific details sire set forth in order 1 o provide a thorough understanding of the present in venrion It will be evident, however, to one skilled in the art that the present invenlion may be practiced without these specific derails. I/O Address Space Computer systems employing certain processor architectures provide two distinct address spaces, namely a memory address space, and an I/O address space. Registers within I/O interfaces and other functional units are mapped to the I/O address space, and ore referred 10 as I/O-mapped registers. Generally, an I/O port has a dedicated l/O-mapped register associated therewith. However, two or more l/O-mapped registers may share a common port, if appropriate circuitry is provided for directing data between the registers and ports. I/O-mapped registers may perform a number of functions within a computer system, such as data buffering, status and configuration indication, and control functions. In one embodiment, a computer system allows I/O-ports to be addressed in two ways, namely through a memory-mapped I/O operation, where I/O ports appear in the memory address space, and through a separate I/O address space accessed using I/O instructions. These instructions include IN and OUT instructions. Processors within a computer system may be designed to operate in a number of different modes, in which various features and functions are enabled or disabled The enabling and disabling of these feature* may be mod voted by a wide range of considerations including performance optimization, backwards compatibility and function transparency. For example, the Pentium® processor manufactured by Intel Corporation of Santa Clam, California, is capable of operating in any one of the four modes illustrated in Figure 1, namely. 1. a Real-Address Mode 10, 2. a Protected Mode 12; 3. a Virtual 8086 Mode 14; and 4. a System Management Mode (SMM) 16*. Such modes are well-known in the art. The SMM 16 provides high level systems functions, such as power management and security, in a manner transparent to both application software and the operating system. For example, code to power-down a peripheral device after it has been idle for a pre-determlned amount of time is stored in a dedicated SMM address space, termed the system m in&gemem random access memory (SMRAM), This code can be accessed when a processor enters the SMM 16, and executed completely transparently to the operating system, device drivers and application software. This negates the necessity for application and operating system software developers to customize software to incorporate such power mnnagement features Referring to Figure 2, a computer system 18 capable of operating in SMM 16, and within which the present invention can be employed, is shown. The computer system 18 has as its primary components a processor 20, B host bus 22, a host bridge 24, main memory 26, an intermediate bus 28, an expansion bridge 30 and an expansion bus 32. The processor 20 processes signals, performs computations and controls operations. The host bridge 24 provides an interface between the host bus 11 and the intermediate bus .18. In one embodiment, the intermediate bus 28 is a Peripheral Components Interconnect (PCI) bus, and is operated according to the Peripheral Components Interconnect (PCI) Local Bus Specification, Revision 2.1, published June 1,1995. The expansion bridge 30 provides an interface between the intermediate bus 28 and the expansion bus 32, and is viewed by an intermediate bus arbiter (not shown) ah a PCI device. In one embodiment, the expansion bus 32 is either an Industry Standard Architecture (ISA) bus or an Extended industry Standard Architecture (EISA) bus. The host bridge 24 incorporates a memory controller 34 for controlling access to the main memory 26. A PCI device 36.1, which may be an input/output (I/O) device or a further expansion bridge, is coupled to the intermediate bus 28 via an interface 119. Examples of I/O devices are, well-known and may include Small Computer System Interface (SCSI) controllers, Personal Computer Memory Card International Association (PCMCIA) interfaces and keyboard controllers. A graphics controller 36.2 is also coupled to the intermediate bus 28 via an interlace 39, and controls access to a graphics frame buffer 38. An expansion bus master 40.1 and an expansion bus slave 40.2 are coupled ro the expansion bus 32 via interfaces 41. The expansion bus master 40.1 may, for example, be a Direct Memory Access (DMA) controller The expansion bus slave 40.2 may be a floppy disk drive. The interfaces 39 and 41 include a number of registers (not shown), including data-buffering, control ami status registers, and appropriate decoding logic (not shown), which will be described in further detail below. The expansion bridge 30 provides an interface between the intermediate bus 28 and the expansion bus 32. The expansion bndge 30 nviy also include registers of the types described above and decoding logic. Accordingly, for the purposes of this specification, the term "interface arrangement" shall be taken to refei to either interfaces which provide an interface between a computer system and a peripheral device (such as interfaces 39 and 41) or to bus bridges (such as the expansion bridge 30). Furthermore, an interface arrangement could be incorporated Into the computer system or the peripheral device, or urn Id be u discrete functional unit. As shown in Figure 2, the expansion bridge 30, the graphics controller 36.2, the PCI device 36.1, the expansion bus master 40.1 and the expansion bus slave 40.2 are coupled to a provide a system managenment interrupt (SM1#) signal 42 to the processor 20, The SMI# signal 42 is a non-maskable interrupt having a higher priority than all other interrupts, including other non-maskable interrupts. The processor 20 is txiupled to provide a system management interrupt acknowledge (SMIACNf) signal 44 to the memory controller 34, the SMI ACT# signal 44 being asserted in response to the assertion of the SMI# signal 42 The # designation following each signal indicates that the signal is active low, and is accordingly asserted by a low transition. It will be appreciated that any peripheral device, bus bridje, power management circuit or security circuit may be coupled to provide the SMI# signal 42 to die processor 20. When the SMI# signal 42 is asserted, the processor 20, in acknowledgment; asserts the SMSACT* signal 44 to notify the memory controller 34 that the next processor access will be to system management random access memory (SMRAM) 50. Figure 3A shows the processor address space 46 prior to entry into the SMM, while Figure 3D shows the processor address space 48 after assertion of the SMIACT# signal 44. As is i,hown in Figure 311, the SMRAM 50 is mapped to an address range within processor address space 48 After assertion of the SM1# slgnal 42 by a device, the processor 20 waits for all outstanding data write operations to complete, and then saves register sittue information into the SMRAM 50. The processor then enters SMM 16 by setting internal registers to initial SMM state conditions, and begins execution of a SMI handler (not shown) which is stored at o predetermined entry point within the SMRAM 50. While in SMM 16, the processor 20 i& able to access the entire I/O address space, and the entire memory address space, When the SMI hardier is invoked it will firstly examine a status vector to determine the nature and source of the SMI# signal 42, Having identified the nature and source of the request, the SMI handier then executes a SMM routine which addresses and services the request. The SM!# signal 42 may be asserted by a number of devices for a number of reasons, the most common requests being to; (a) power-down an idle device, (b) power-up a device to which access is required; (c) modify the format of data in a register so as to allow compatibility between the computer system 18 and a peripheral device; (d) service mobile computing functions which are not serviceable by the operating system (e.,g, docking functions); (e) throttle clocks and oscillators; (0 s;ive state information for the compu ter system; and (g) power-down the computer system. Other function1: dependent on (he system design may also cause the assertion of the SM1# signal 42. Once the SMI handler has executed the appropriate SMM routine, a return from system management (RSM) instruction Is issued, and the processor suite that was stored upon entry into SMM is restored. Accordingly, SMM 16 provides a transparent and convenient manner of servicing system management functions within the computer system 18. Apparatus Description Turning now to Figure 4, there is shown ihe computer system 18 incorporating one embodiment of the present invention. The expansion bridge 30 is shown 10 include u plurality of registers; 60.1 to 60.3, these registers 60 being mapped to the I/O address space. The registers 60.1 to 60.3 are configured to perform a number of functions, including data-buffering, status indication and various control functions. The expansion bridge 30 also includes a decoder 67. which is coupled to receive address und control information from the intermediate bus 28, and to select one of the registers 60.1 to 60.3 for access by the processor 20 or another device within the computer system 18 Logic circuitry 64 is also shown to be included within the expansion bridge 30. und to be coupled to receive the SMIACT# signal 44 from the processor 20 Accordingly, by monitoring the SMiACT# signal 44, the logic circuitry 64 is able to detect when the processor 20 enters SMM 16. The logic circuitry 64 is functional to provide a first type of access io the registers 60.1 to 60.3 when it detects that the processor 20 IS in SMM 16, and to provide a second type of access to the registers 60.1 to 60.3 when it detects that the processor 20 in not in SMM 16 (i.c in real-address, protected or virtual 8086 mode). More specifically, the logic circuitry 64 allows full read/write access to the registers 60.1 to 60.3 when the processor 20 is detected to be in SMM 16, while preventing, or blocking, access to the registers 60.1 to 60.3 when the processor is not in SMM 16. Figure 4 shows the logic circuitry 64 as being coupled to the decoder 62, and providing an input into the decoder 62 to achieve the functionality described above. It will however be appreciated that die logic circuitry 64 could be incorporated into the decoder 62, or could alternatively be located down-stream ot the decoder 62 to gate a select signal from the decoder 62 when the processor 20 is not in SMM 16. Furthermore, (he first type of access aflowed by the logic circuitry 64 need not be full read/write access, and the second type of access need not be a complete access block For example, the first type of access could be read access only, paired with a second type of access providing a complete access block to a specific register. Alternatively, the first type of access could be full read/write access, paired with a second type of access allowing only read access to a register. The first and second access types described above are effective to provide varying degrees of protection to a register, by either totally preventing, or merely limiting, access to a register when the processor 20 is not in SMM 16. Accordingly, the above described arrangement provides a simple, yet effective, protection against malfunctioning programs, virus programs or even an operating system kernel which may otherwise have been able to access, and illegally modify, the contents of the registers 60, The secure protection afforded to the registers 60 as described above is particularly valuable when any one of the registers 60,1 to 60.3 is used for power management and system configuration purposes, as corruption of data stored in such a register could have serious implications for the integiity of data. software and even physical device within the computer systrrn 18. The first and second types of access need not relate to degrees of access to the registers 60, but can relate to the manner in which the registers 60 themselves operate. For example, the first type of access allowed by the logic circuitry 64 may be to facilitate access to the register 60-1 as a serial port, and the second type of access may be ID allow access to the register 60.1 as a parallel port, or vice versa. Figures 5 to 7 illustrate in more detail rircult arrangements for facilitating the first and second types of access to an l/O-mapped register. Referring firstly to Figure 5, there is shown a circuit arrangement 66, Including a chip 68 having a control/status register 70 and a data (register 72, the registers 70 and 72 being mapped to the I/O address space. The circuit arrangement 66 further includes an address decoder 74, which Is coupled to receive address data from an address bus 76, and a memory/input-ourput (M/lO) signal from a control bus 78. The circuit arrangement 66 also includes logic circuiny in the form of an AND gate 80, which is coupled to receive a SELECT signal 82 from the address decoder 74, and a SMIACT* signal 84 from the Control bus 78, The AND gate SO is also coupled to provide a CHIP SELECT signal 86 to the chip 68. Accordingly, by allowing the AND gate 80 to gate the SELECT signal 82 from the address decoder 74, the AND gate 80 is able to prevent any access to the registers 70 and 72 when a processor, from which the SMIACT# signal 84 originates is not operating in SMM 16. In this way, the register 70 and 72 are protected from corruption or unauthorized modification when the processor is not in SMM 16. Figure 6 shows a further embodiment of the present invention, in which a circuit arrangement K8 includes art l/O-mapped register 90. and an address decoder 92. The address decoder 92 is coupled to receive address data from an address bus 76. and a memory/input-output (M/IO) signal from a control bus 78. The circuit arrangement 88 also includes logic circuitry comprising AND gates 91 and 9