FIELD OF INVENTION
The present invention relates to a new classical-MOSFET-alike n-type Tunnel PET architecture, which offers sub-60mV/decade sub-threshold swing with a significant improvement in ION- The enhancement in IQN is achieved by introducing a thin strained SiGe layer on top of the Silicon Source. With the help of TCAD simulations, we have demonstrated that the proposed device meets the ITRS (International Technology Roadmap for Semiconductors) specifications for the ON current of LSTP (Low STandby Power) applications. Also it is shown that the proposed device is naturally immune to short channel effect (SCE) and can be fabricated with standard CMOS process steps.
BACKGROUND OF PRESENT INVENTION AND PRIOR ART
The switching characteristics of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) have degraded considerably over the years due to relentless scaling. The subthreshold swing (S) of the MOSFET, which determines its switching characteristics and OFF Current (IQFF) is unscalable. Due to the drift-diffusion mode of carrier transport, the S in a MOSFET is theoretically limited to a value of 60mV/decade at the room temperature. In-fact, due to various short channel effects, punchthrough etc., the actual value of S in the present day MOSFET is much higher, which has resulted in an increase of IQFF from generation to generation and thus became a major concern for low-standby power (LSTP) applications. One therefore needs to explore novel device architectures which use other mode of carrier transport (i.e., impact ionization [1], interband tunneling 12] - [14] etc.) in order to achieve sub-60mV/decade values of S. The Impact Ionization MOSFET (I-MOS) [1] appeared to be very promising due to its near ideal switching characteristics. However, due to problems like Threshold Voltage (VTH) shifts caused by hot carrier injection, non rail to rail voltage swings and high operating voltage requirements, it failed to meet the ITRS [18] requirements for LSTP application.
The Tunnel Field effect Transistor (TFET) with perfect saturation in the output characteristics has shown a lot of promise for achieving better scaling without severe

short channel effects [6]. Many variants of the TFET have been proposed till date. Among them, the Vertical channel Tunnel FET with a strained pseudomorphic 8p4 SiGc layer has been the most discussed structure. Due to its complex fabrication steps, routing (layouting) and packaging (not compatible with Classical CMOS), Vertical channel TFET doesn't appear to be practically applicable for LSIT applications. To overcome above difficulties non-Si lateral Tunnel FET has been proposed by Baba [3] and Si Lateral Tunnel FET has been proposed by Reddick [4], which enjoys CMOS compatible process steps. However, in spite of excellent sub-threshold swing and high IGN/IQFF ratio, the very low IQN is the main issue with this device. Recently, ON current improvement in this lateral structure has been reported using high-K gate dielectric in a double gate structure [22]. However, it does not take into account the mobility degradation related to high-K material, gate dielectric breakdown due to high field across the very thin high-K material and fabrication issues related to high-K material involved.
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OBJECTS OF INVENTION
The principle objective of the present invention is to develop an n-type tunnel PET device that will provide ON current in the order of SOOHA/Dm (according to ITRS specs for LSTP applications) and OFP current in the order of fento-amperes. The present invention has met this objective by introducing a strained SiGe layer on the top of the Silicon Source of a conventional tunnel PET.
Another main object of the present invention is a CMOS compatible method of fabricating n-type tunnel PET device with strained SiGe layer at source, said method comprising steps of: doping n drain and gate region with arsenic using photo resist mask followed by annealing, use Nitride mask to mask n, drain and gate and to define source region, etching 40nm silicon at source region by using the Nitride mask, deposit 20nm thin p, silicon with Boron dopant by Molecular Beam Epitaxy (MBE), and deposit 20nm thin SiGe layer with Ge mole fraction x using Molecular Beam Epitaxy (MBE) on the p, silicon in source region.
STATEMENT OF INVENTION

Accordingly the invention provides an n-type tunnel FFf device with strained SiGe layer at source; and a method of fabricating n-type tunnel FET device with strained SiGe layer at source, said method comprising steps of: doping n, drain and gate region with arsenic using photo resist mask followed by annealing, use Nitride mask to mask n, drain and gate and to define source region, etching 40nm silicon at source region by using the Nitride mask, deposit 20nm thin p, silicon with Boron dopant by Molecular Beam Epitaxy (MBE), and deposit 20nm thin SiGe layer with Ge mole fraction x using Molecular Beam Epitaxy (MBE) on the p, silicon in source region.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
Figure 1: shows schematic of the proposed n-type TFET structure with strained SiGe
layer at Source. For all simulations, tox =" 2nm, drain doping (n+) = 5 x 10,, and source
doping (p+) ==1x10 are used.
Figure 2: shows simulated band diagrams (along the cut section A~B in Fig. 1) of the n-
type Conventional (without strained SiGe) TFET in non-conducting and conducting
regions. The large reverse biased barrier insures extremely low IQFF.
Figure 3(a): shows equilibrium Band diagrams of the proposed TFET structure for
various values of Ge mole fraction (x)
Figure 3(b): shows effect of Drain voltage on the device band diagrams. It is seen that
the tunneling width remains nearly independent of the applied drain bias. Thus insuring
high immunity to DIBL
Figure 4(a): shows simulated transfer characteristics of the device for various values of
Ge mole fraction (x) for linear and saturation VDS-
Figure 4(b): shows output characteristics of the TFET with strained SiGe layer at the
Source
Figure 5: The avg. sub-threshold swing (S) and IQN vs. x. IQN increases exponentially
with X. However, the IQFF remains in the order of fA
Figure 6: shows a zoomed view of the tunneling junction of the TFET. 2D simulations
show that the band to band generation is limited to the top 20nm layer of the device
(when it is biased in the operating region)

Figure 7: shows IQN as a function of the depth of SiGe layer (Ld). IQN increases with an
increase in La up to a depth of 20nm. Increasing Ld beyond this value does not help in
increasing IQN as it falls beyond the active region of the device
Figure 8: shows SCE and DIBL in the proposed device. A suppression of SCE is seen
with an increase in x. DIBE also disappears with an increase in x.
Figure 9: Shows effect of Body bias on device performance (Ge mole fraction (x) ,,0.3,
VDS,,I.OV). The ID-VGS characteristics remain un-altered but the bulk current increases
linearly with increase in bulk terminal potential.
Figure 10; shows combination of high-K (G=29) along with the strained SiGe layer at the
source end helps in achieving much better IQN and sub-threshold swing for realistic
physical thickness. Ld=10nm, Tdieiectric , 5nm in this case.
Figure 11: shows band gap of strained SiGe and Relaxed SiGe for different values of Ge
mole fraction. Strain tends to reduce the band gap and thus helps in improving IQN
Figure 12(a): shows drain and gate doping by Ion implantation.
Figure 12(b): shows etching source region to the depth Xj= 40nm.
Figure 12(c): shows partial deposition of p, Source (upto 20nm) using epitaxy with
Boron as impurity.
Figure 12(d): shows deposition of p, strained SiGe layer on top of the p, source using
epitaxy with Boron as impurity.
Figure 13: shows doping profile (along the cut section A-B in Fig. 1) for various doping
methods and dopant materials for the p+ source. Arsenic is the impurity at the n+ drain
for all cases
Figure 14: shows a comparison of performance of three different structures generated by
process simulations with that of an ideal device. The x=0.0 Indium and Boron curves are
for the structure generated by doping using Ion implantation. The x=0.2 is the curve for
the structure generated by doping boron using epitaxy.
Figure 15: shows band to Band generation rate at the tunneling junction (A): Due to the
lateral diffusion of Boron, the tunneling junction is created slightly away from the Si-
SiGe interface resulting in a not so high IQN as the ideal device. (B): Tunneling junction is
at the Si-SiGe interface.

Figure 16: shows a comparison of the performance of device in Fig. 15(A) (Device A) and Fig. 15(B) (Device B) with the Ideal device. Due to the presence of strained SiGc layer at the tunneling junction, the performance of Device B is better than Device A
DETAILED DESCRIPTION OF THE INVENTION
Primary embodiment of the instant invention is an n-type tunnel PET device with strained SiGe layer at source.
In yet another embodiment of the present invention the device is naturally immune to Short Channel Effect (SCE) upto 30nm channel length.
In still another embodiment of the present invention the device is immune to Drain Induced Barrier Lowering (DIBL) effect upto 30nm channel length with Ge mole fraction greater than 0.3.
In still another embodiment of the present invention the strained SiGe layer is placed on top of the silicon source to enhance 'ON' current (ION)-
In still another embodiment of the present invention the device 'ON' current (ION) increases exponentially with increase in Ge mole fraction.
In still another embodiment of the present invention the device coupled with high-k material with thicker gate dielectric gives further boost in drive current and reduction in gate leakage.
In still another embodiment of the present invention the material is selected from the group comprising Si02, Hf02 and ZrOi.
In still another embodiment of the present invention the thickness of gate dielectric is in the order of 5nm.
In still another embodiment of the present invention the device drain current is independent of body bias.
In still another embodiment of the present invention the devices ON current (IQN) ranges from 0.6|aA/|am to 580|aA/|im for Ge mole fraction range from 0 to 0.7 with Voo of about 1.2V.
In still another embodiment of the present invention the device channel length ranges from 30nm to 200nm.

In still another embodiment of the present invention the device sub-threshold swing ranges from 108mv/dec to 13mv/dec and OFF current (Ion) ranges from 0.074fA/|im to 1.038fA/,m for Ge mole fraction of 0 to 0.7 with VDD of about 1.2V.
In still another embodiment of the present invention the device provides reduced OFF current (IOFF) for power applications without compromising on switching speed.
In still another embodiment of the present invention an application demanding low stand-by power (LSTP) using the device.
Another main embodiment of the present invention is method of fabricating n-type tunnel FET device with strained SiGe layer at source, said method comprising steps of;
i. doping n, drain and gate region with arsenic using photo resist mask
followed by annealing,
ii. use Nitride mask to mask n, drain and gate and to define source
region, iii. etching 40nm silicon at source region by using the mask of step(ii), iv. deposit 20nm thin p, silicon with Boron dopant by Molecular Beam
Epitaxy (MBE), and
v. deposit 20nm thin SiGe layer with Ge mole fraction x using Molecular
Beam Epitaxy (MBE) on the p, silicon in source region.
Instant invention is a new classical-MOSFET-alike n-type Tunnel FET architecture, which offers sub-60mV/decade sub-threshold swing with a significant improvement in IQN. The enhancement in IQN is achieved by introducing a thin strained SiGe layer on top of the Silicon Source. With the help of TCAD simulations, we have demonstrated that the proposed device is naturally immune to short channel effect (SCE) and can be febricated with standard CMOS process steps. It is observed that the body bias does not affect the drain current but the body current gets affected. Another original finding is that the introduction of strained SiGe layer makes the device immune to Drain Induced Barrier Lowering (DIBL) effect and the IQN increases exponentially with Ge mole fraction (x). It is noted that if proposed architecture is coupled with high-K material (as proposed in |22]) additional boost in drive current can be achieved with a thicker gate dielectric. An IQN of -0.58mA/|im and a minimum average sub-threshold swing of 13mV/decade is achieved

for lOOnm channel length device with 1.2V supply voltage and 0.7 Ge mole fraction, while maintaining the IQFF in fA range. A fabrication process flow, flilly compatible with the conventional CMOS steps is also designed using 2D process simulations.
DEVICE STRUCTURE AND WORKING PRINCIPLE
The device being investigated is a lateral n-type Tunnel FET with a strained SiGe layer on the top of the source. The l,unnel FET is a gated reverse biased p+ - p - n+ structure which uses the principle of gate controlled band to band tunneling for its operation. The proposed device is shown in Fig. 1. To operate the device, the p+ source is grounded, and positive voltage (IV) is applied to the n+ drain with a positive sweep at gate. The working principle of conventional (without strained SiGe) TFET and band diagrams are shown in Fig. 2. In the absence of a gate voltage (non-conducting region), the tunneling barrier width is large enough to give extremely small current (IOFF). However, on application of positive gate voltage, the bands in the intrinsic (lowly doped) region are pulled downwards and a tunneling barrier is created between source and channel. Due to the reduction in tunneling width and electric fields produced, zener tunneling of electrons takes place from the valance band of the source to the conduction band of the channel and the device turns ON. One should note that this behavior is analogous to NMOS in the CMOS technology. For a Tunnel FET, the ON current is proportional to the electron/hole transmission probability T(E) in the Band to Band tunneling (BTBT) mechanism, which is given by [19]:

where, m* is the carrier effective mass, e is the electron charge, Eg is the bandgap, AO is the energy range over which tunneling can take place, and tox, tSi, Cox and Gsi are the oxide and silicon film thickness and di-electric constants, respectively. This is equation shows decreasing oxide thickness (tox) [21], increasing oxide dielectric constant (Cox), and reducing bandgap (Eg), will enhance the performance of the device, Boucart and

lonescu [22] have proposed the use of high-K materials as the gate dielectric (high Cox in l:q. 1) in order to increase ON current (ION)- In this work, IQN enhancement has been done by modulating the bandgap (Eg) by using a strained SiGe layer at the source end and varying its Ge mole fraction (x). As the electron/hole effective mass m* does not change too much with mole fraction (x), its impact on IQN could be ignored.
The device performance is sensitive to the doping concentration of source and abruptness of doping profile at sourcechannel [9]. The doping of source, substrate and drain regions chosen to optimize IQN respectively axe 1 x 1020, 1 x 1016 and 5 x 1019 cm . Device performance is very sensitive to Gate work function as reported in [21], but we have used n*- Polysilicon compatible to CMOS process flow for gate material. A constant oxide thickness (tox ", 2nm) and channel length (L = lOOnm) is chosen for all simulations.
SIMULATION MODELS AND DEVICE PARAMETERS
2D Device and process simulations were performed in Medici [16] and Tsuprem4 [17] respectively. Field dependent Kane's model [15] avaiiable in Medici is used to model the band to band tunneling generation and recombination rate. Kane's model has been shown to give a good match for band to band tunneling in silicon based tunnel transistors at both high and low temperatures [4]. Since the source region is heavily doped, and tunneling is a strong function of bandgap, the bandgap narrowing model (BGN) is also included in the simulations. Fermi Dirac statistics, although they are computationally less efficient, are used instead of Boltzmann approximations for the same reason. The BTBl' model in Medici is configured in such a way that it uses the average tunneling field while solving the pre-exponential and the path integral field while solving the exponential in the tunneling rate. Also a recursive refinement procedure is used that further improves the accuracy of the simulations. Nonlocal tunneling is enabled which causes the electrons to be generated at the end of the tunneling path as implied by the tunneling physics.
Unlike the MOSFET, where there is a clear transition between the Subthreshold and Strong inversion, in TFET the slope (of logioln) is an exponential llinction of Vos- The slope is very steep for lower VQS but becomes less and less steeper as the gate voltage

increases. Therefore, the threshold voltage (Vn]) cannot be extracted using the standard MOSFET techniques (linear extrapolation, maximum conductance etc.). Hence, as discussed in [20], VTH is calculated by a constant current method at IVT , 10~,A/|im. The average subthreshold swing is extracted by taking the average between the gate voltage at which the ID begins to increase and the threshold voltage. This method has been explained in detail earlier by [21] and [22] and is considered to be a consistent way to define S for TFET. IQN is calculated at VGS ", VQS '-, 1-2V as per the voltages specified by ITRS for LSTP applications at the 65 nm node.
RESULTS AND DISCUSSION
/}. The strained SiGe layer
As discussed earlier, a strained SiGe layer is introduced at the top of the source in the conventional Tunnel FET to achieve an improvement in the ON state current. Fig. 3 shows simulated Band Diagrams of the proposed Tunnel FET architecture in Fig. 1 along the cut section (A-B). Fig. 3(a) shows the effect of varying the Ge mole fraction (x) in the equilibrium band diagrams of the proposed device. As expected, the Bandgap at the source end reduces as we increase the Ge mole fraction (x). This results in a reduction in the tunneling bandgap and consequently an increase in the transmission probability (Eq. 1) and drive current. Fig. 3(b) shows how the bands vary under the effect of drain bias. As can be seen there is negligible change in the tunneling band height and width with increase in Vns.
The transfer and output characteristics of the proposed device are shown in Fig. 4. As expected, in Fig. 4(a) we observe that, the over all drain current and specially the ON current increases as we increase the Ge mole fraction (x). Fig. 4(b) shows the output characteristics of the device. Due to the reverse biased p-i-n structure, the output impedance of the device is very high. This is also seen in the IDS vs. VDS curves where the drain current is almost constant in the saturation region. According to Eq.l, we observe in Fig.5 that, the increase in IQN is exponentially dependent on the reduction in Eg (which reduces linearly with increase in Ge mole fraction (x)). Also, this increase in

I()N leads to a reduction in the average subthreshold swing of the device since now the threshold voltage falls in the sleeper region of the curve. IQN of 58()\\A/\)im, IOFF of 0.52fA/[im and average S of l3mV/decade are achieved for x=0.7 with YOD',J-2V. However, enabling the tunneling through gate oxide, gate leakage current of 3.7mA/cm is observed, which is one decade lower than ITRS specs. It should be noted that IQN is matched with ITRS specs with thicker tox, that enables us lower gate leakage.
B. Depth ofSiGe Layer (L,)
Proposed TFET is a surface tunneling device and the active region of the device is situated right at the surface near the channel-source junction. From 2D device simulations, it is observed that the band to band generation rate is maximum at the surface and has some practical value only in the top 20nm layer of the device (Fig. 6). Therefore, it is believed that increase in IQN can be achieved by reducing bandgap only in this 20nm region right below the surface. This fact is verified in Fig. 7 where we observe that the IQN of the device increases as we increase the depth of SiGe (La) layer to 20nm but does not increase further beyond this value. Any additional increase in the SiGe layer depth only causes an increase in the IQFF of the device. It is also observed in Fig, 7 that the effect of Ld becomes more prominent as the value of the mole fraction (x) is increased.
C SCE and DIBL
The active region of the TFET is only a very thin region near the surface at the channel source interface. This, along with the large reverse biased barrier, makes the TFET a highly scalable device. It is shown that the device can be scaled up to channel lengths as small as 30nm without affecting its performance. Fig. 8 shows the effect of channel length and drain bias on the threshold voltage (VTH) of the device. V-pH values, which are quite high for x=0, agree well with ITRS requirements [18] for higher values of x. Also, it is observed that there is virtually no DIBL for higher values of x (above x=0.3). This is because, the barrier width (which is directly proportional to the tunneling bandgap) is a

much stronger function of x than Vos- Therefore, as we increase the mole fraction (x), the lowering of bandgap by x dominates the lowering of bandgap by Vos-
D. Effect of Body bias
Fig. 9 shows the effect of body bias on the proposed device characteristics. Unlike MOSFET, both positive and negative body bias turn on either Body/Drain or Body/Source diode (forward bias) and generate a significant amount of substrate current. However due to the difference in the effective forward biases, the magnitude of IBULK would be quite different for positive and negative body voltages. It should be noted that in contrast with MOSFET, body bias does not change the threshold voltage and the drive current of the proposed device.
E. Iligh-K material as gate dielectric
In [22], the use of high-K materials to improve the IQN of the device has been reported. The thickness of the dielectric material needed to achieve this improvement in IQN is very small (3nm). It may not be practical to use such thin high-K dielectric as their breakdown voltages are much smaller compared to Si02. However, if the same technology is used with the proposed TFET design, it is possible to achieve better IQN even for a thicker, more realistic physical dielectric thickness (more than 5nm). Fig. 10 shows the transfer characteristics comparing the two devices with different dielectric constants (Hf02 and Si02) for two different values of Ge mole fractions. It is seen that a very high IQN (nearly lmA/|im) can be achieved if both the techniques are combined.
F. Effect of Strain on the channel
The reasons behind adding the strained SiGe layer only to the source region are twofold. First, the active region of the device is located only at the source-channel junction and the drain voltage does not play any role in BTBT tunneling. Second, adding SiGe to the drain also would add strain to the channel from both sides. This strain in the channel may

increase/reduce the carrier mobility. Therefore, it is very difficult to predict the effect of stress and requires further investigation. In fact the proposed device will operate with same efficiency if we use fully Silicon-Germanide source instead of strained SiGe layer on the top of a Si Source. However, we propose strained SiGe layer source in order to minimize the effect of stress on the silicon channel.
G. Effect of Strain on SiGe layer
fhe effect of strain on SiGe bandgap is shown in Fig. 11. The band gap values are extracted from 2D simulations in Medici. It is observed that strain tends to reduce the band gap of the SiGe layer. This further helps in improving the IQN of the device. Thus, it is desirable to have a strained SiGe layer at the source. To obtain 20nm or more thicker layer of strained SiGe over Si with Ge mole fraction x=0.7 is a challenging technology problem (it can be obtained by growing over relaxed SiGe) [23] - [24]. But the same IQN can be obtained with lower Ge mole fraction by decreasing tox (compromising with gate leakage).
1'ABRICATION OF THE PROPOSED DEVICE
The device can be fabricated with slight modifications in the standard CMOS process How after Gate stack formation. The following main changes are needed for fabricating the proposed device:
1) A new set of masks is needed to incorporate a n+ drain and a p-f source in the same device, (unlike the conventional NMOS where we had n+ in both source and drain regions.)
2) To get the SiGe layer at the source, additional steps of etching of Si and epitaxial deposition of SiGe are needed.-5
A. Description of Process steps
Fig. 12 shows the device in various stages of process simulation. Here we show only those steps which are different from the standard CMOS steps. Fig. 12(a) shows the photoresist mask necessary to dope the n+ drain and gate regions. This doping (approx 5

X 10,") is achieved by Ion implantation of Arsenic followed by annealing. After the gate and drain doping, another mask is prepared which covers these two regions. With the help of this mask, silicon in the source region is etched away (Fig. 12(b)). This is followed by epitaxial deposition of Boron doped p+ silicon. As shown in Fig. 12(c), this deposition is only partial and does not form the full source. The rest of the source (the SiGe layer) is deposited using epitaxy of Boron doped silicon with germanium (Fig. 12(d). The epitaxy process helps in achieving abrupt doping profile at the source end which has been shown to achieve better IQN for the silicon TFET [25]. The doping distribution along the channel for different source dopant and doping methods is compared in Fig. 13.
The devices generated using process simulations were simulated in Medici. The performance of these devices is compared with that of the ideal device in Fig. 14. As expected, it is observed that the performance of the device in which doping at the source is done using epitaxy is nearest to that of the ideal device.
B. Effect of Boron diffusion
Lateral diffusion of Boron into the channel leads to formation of tunneling junction away from Si-SiGe interface as shown in Fig. 15(A), which results in less ON current (IQN) enhancement as shown in Fig. 16 (Device A). In order to obtain IQN improvement, Boron diffusion should be reduced so that tunneling junction forms in p+ SiGe Source region as shown in (Fig. 15(B)). The effect of lateral boron diffusion is shown in Fig. 16
CONCLUSION
A novel Silicon Tunnel FFIT architecture with strained SiGe layer at source is proposed and analyzed using 2D device simulations. The proposed device is nearly free of SCE and DIBL and can be scaled upto channel lengths of 30nm. The proposed device shows orders of improvement in ON current over the conventional TFET with the added advantage of compatibility with CMOS febrication steps. A process technique to fabricate the device is also designed using 2D process simulations.

We claim:
1. An n-type tunnel FET device with strained SiGe layer at source.
2. The device as claimed in claim 1, wherein the device is naturally immune to Short Channel Effect (SCE) upto 30nm channel length.
3. The device as claimed in claim 1, wherein the device is immune to Drain Induced Barrier Lowering (DIBL) effect upto 30nm channel length with Ge mole fraction greater than 0.3 .
4. The device as claimed in claim 1, wherein the strained SiGe layer is placed over silicon with p-type dopant to enhance 'ON' current (ION)-
5. The device as claimed in claim 1, wherein the device 'ON' current (ION) increases exponentially with increase in Ge mole fraction.
6. The device as claimed in claim 1 wherein the high-k material with thicker gate dielectric gives further boost in drive current and reduction in gate leakage.
7. The device as claimed in claim 6, wherein the material is selected from the group comprising SiOi, Hf02 and Zr02.
8. The device as claimed in claim 6, wherein the thickness of gate dielectric is in the order of 5nm.
9. The device as claimed in claim 1, wherein the device drain current is independent of body bias.
10. "Trhe device as claimed in claims 1 and 5, wherein the device ON current (ION) ranges from 0.6µA/µm to 580A/m for Ge mole fraction range from 0 to 0.7 with VDD of about 1.2V.
11. The device as claimed in claim I, wherein the device channel length ranges from 30nm to 200nm.
12. The device as claimed in claim 1, wherein the device sub-threshold swing ranges from 108mv/dec to 13mv/dec and OFF current (IOFF) ranges from 0.074fA/|im to 1.038fA/iim for Ge mole fraction of 0 to 0.7 with VDD of about 1.2V.
13. The device as claimed in claim 1, wherein the device provides reduced OFF current (IOFF) for low power applications without compromising on switching speed.

14. An application demanding low stand-by power (LSTP) using the device claimed in claim 1.
15. A method of fabricating n-type tunnel FET device with strained SiGe layer at source, said method comprising steps of:
i. doping n drain and gate region with arsenic using photo resist mask
followed by annealing, ii. use Nitride mask to mask n drain and gate and to define source
region, iii. etching 40nm silicon at source region by using the mask of step(ii), iv. deposit 20nm thin p silicon with Boron dopant by Molecular Beam
Epitaxy (MBE), and
V. deposit 20nm thin SiGe layer with Ge mole fraction x using Molecular
Beam Epitaxy (MBE) on the p silicon in source region.
16. An n-type tunnel FET device with strained SiGe layer at source and method of
fabricating as herein described with reference to the accompanied drawings.