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An Output Overvoltage Protection And Reverse Output Protection Circuit

Abstract: “AN OUTPUT OVERVOLTAGE PROTECTION AND REVERSE OUTPUT PROTECTION CIRCUIT” The present invention provides an output overvoltage protection and reverse output protection circuit (200) that comprises a field-effect transistor, FET (202) whose source terminal is connected to a positive terminal of an input voltage and the drain terminal is connected to one of the output terminal; a resistor (203) whose first end is connected to the gate terminal of the FET (202) and the second end is connected to the positive terminal of the input voltage; a transistor (204) whose collector terminal is connected to the first end of the resistor (203) and to the gate terminal of the FET (202); a resistor (205) whose first end is connected to the base terminal of the transistor (204); a transistor (207) whose collector terminal is connected to the second end of the resistor (205), and the emitter terminal is grounded; a resistor (206) whose first end is connected to the collector terminal of the transistor (207) and the second end is connected to the positive terminal of the input voltage. A voltage regulator circuit (208, 209, 210) connected to the base terminal of the transistor (207), configured to apply a regulated voltage to the transistor (207). A voltage divider circuit (211, 212) connected in series with the voltage regulator circuit, wherein the voltage divider circuit is configured to supply at least a part of input voltage to the voltage regulator circuit during operation, wherein the voltage regulator circuit (208, 209, 210) is operational in an overvoltage condition, and configured to apply a voltage to the base terminal of transistor (207), to turn ON the transistor (207), which further causes the transistor (204) and FET (202) to turn OFF. [Fig. 2]

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
03 October 2018
Publication Number
15/2020
Publication Type
INA
Invention Field
ELECTRICAL
Status
Email
ipo@knspartners.com
Parent Application
Patent Number
Legal Status
Grant Date
2023-03-09
Renewal Date

Applicants

MINDA CORPORATION LIMITED
E-5/2, Chakan Industrial Area, Phase-III, M.I.D.C., Nanekarwadi,Tal: Khed, Dist.Pune-410 501, India

Inventors

1. M. Muthu Saravanan
SPARK MINDA TECHNICAL CENTRE MINDA CORPORATION LIMITED E-5/2, Chakan Industrial Area, Phase-III, M.I.D.C., Nanekarwadi,Tal:Khed, Dist.Pune-410 501 India
2. M. Muthu Meenakshi
SPARK MINDA TECHNICAL CENTRE MINDA CORPORATION LIMITED E-5/2, Chakan Industrial Area, Phase-III, M.I.D.C., Nanekarwadi,Tal:Khed, Dist.Pune-410 501 India

Specification

FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
PROVISIONAL SPECIFICATION (See section 10, rule 13)
“AN OUTPUT OVERVOLTAGE PROTECTION AND REVERSE OUTPUT PROTECTION
CIRCUIT”
MINDA CORPORATION LIMITED, of E-5/2, Chakan Industrial Area, Phase-III, M.I.D.C., Nanekarwadi,Tal: Khed, Dist.Pune-410 501, India
The following specification particularly describes the invention.

FIELD OF THE INVENTION
The present invention relates to an output overvoltage protection and reverse output protection circuit.
BACKGROUND
The information in this section merely provide background information related to the present disclosure and may not constitute prior art(s).
In the recent years, there is an increasing need of electrical and electronic units for household, commercial and industrial use. As it is known, for any electrical or electronic unit to operate safely and satisfactorily, it is required that the nominal voltages provided to power supply are kept within strict boundary values defined by the electrical standards. Consequently, for their correct and safe operation, priority has been given to the appropriate power supply.
Overvoltage occurs when the supply voltage rises above the rated voltage or nominal voltage of an equipment or unit. The overvoltage can cause excessive current to flow as well as creating excessive voltage stresses. In both cases, the functioning of the equipment can be degraded, reducing life or causing damage to the equipment or unit.
Conventionally, many solutions for overvoltage protection are available. For example, such solutions include use of crowbar/shunting methods with shunting MOSFET or SCR. However, these solutions are still not sufficient as failure of these may cause permanent damage to the equipment and replacement of the equipment or unit will only be the solution. Furthermore, these available solutions do not have reverse output protection which may otherwise can damage internal circuitry and power supplies.
Therefore, there is need of the art to provide an output overvoltage protection and reverse output protection circuit that avoids the undesirable effects due to over voltages/reverse voltages as discussed above.
SUMMARY OF THE INVENTION

One or more shortcomings of the prior art are overcome, and additional advantages are provided by the present disclosure. Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the disclosure.
It is to be understood that the aspects and embodiments of the disclosure described above may be used in any combination with each other. Several of the aspects and embodiments may be combined together to form a further embodiment of the disclosure.
In an aspect, the present invention provides an output overvoltage protection and reverse output protection circuit (200). The protection circuit comprises at least one input terminal configured to receive an input voltage applied from a voltage source during operation, the protection circuit further comprising at least one output terminal configured to provide an output voltage to a load during operation. Further, the protection circuit comprises a field-effect transistor, FET (202) having a gate terminal, a source terminal and a drain terminal, the source terminal of the FET is connected to a positive terminal of the input voltage and the drain terminal is connected to one of the output terminal; a resistor (203) having a first end and a second end, the first end of the resistor
(203) is connected to the gate terminal of the FET (202) and the second end is connected to the positive terminal of the input voltage; a transistor (204) having a base terminal, an emitter terminal and a collector terminal, the collector terminal of the of the transistor
(204) is connected to the first end of the resistor (203) and to the gate terminal of the FET (202); a resistor (205) having a first end and a second end, the first end of the resistor
(205) is connected to the base terminal of the transistor (204); a transistor (207) having a base terminal, an emitter terminal and a collector terminal, the collector terminal of the of the transistor (207) is connected to the second end of the resistor (205), the emitter terminal of the transistor (207) is grounded; a resistor (206) having a first end and a second end, the first end of the resistor (206) is connected to the collector terminal of the transistor (207) and the second end is connected to the positive terminal of the input voltage; a voltage regulator circuit (208, 209, 210) connected to the base terminal of the transistor (207), the voltage regulator circuit configured to apply a regulated voltage to the base of the transistor (207) for operation of the protection circuit (200); and a voltage

divider circuit (211, 212) connected in series with the voltage regulator circuit, wherein the voltage divider circuit is configured to supply at least part of input voltage to the voltage regulator circuit during operation; wherein the voltage regulator circuit (208, 209, 210) is operational when an overvoltage is present, and configured to apply a voltage to the base terminal of transistor (207), sufficient to turn ON the transistor (207), which further causes the transistor (204) and FET (202) to turn OFF.
In another aspect, the present disclosure provides a protection circuit wherein the voltage regulator circuit comprises a Zener diode (208) and a resistor (209), wherein the Zener diode (208) is turned ON when the over voltage is present.
In yet another aspect, the present disclosure provides a protection circuit wherein the voltage divider circuit comprising two resistors (211, 212).
In yet another aspect, the present disclosure provides a protection circuit wherein at least one part of high voltage supply from the voltage divider circuit is grounded via a capacitor (210).
In yet another aspect, the present disclosure provides a protection which further comprises a body diode (201) having a negative end and a positive end, wherein the negative end of the diode is connected to the source terminal of the FET (202) and the positive terminal of the body diode (201) is connected to the drain terminal of the FET (202) and to one of the output terminal.
In yet another aspect, the present disclosure provides a protection circuit as claimed in claim 1, wherein the body diode (201) is not operational when a reverse output voltage is present.
BRIEF DESCRIPTION OF DRAWINGS
Further aspects and advantages of the present invention will be readily understood from the following detailed description with reference to the accompanying drawings. Reference numerals have been used to refer to identical or similar functionally similar elements. The figures together with a detailed description below, are incorporated in and

form part of the specification, and serve to further illustrate the embodiments and explain various principles and advantages, in accordance with the present invention wherein:
Fig. 1 illustrates a block diagram for overvoltage protection and reverse output protection circuit connected to a buck converter/inductor according to an aspect of the present invention.
Fig. 2 illustrates a circuit diagram for output overvoltage protection and reverse output protection circuit according to an aspect of the present invention.
DETAILED DESCRIPTION
Referring now to the drawings, there is shown an illustrative embodiment of the invention an output overvoltage protection and reverse output protection circuit. It should be understood that the invention is susceptible to various modifications and alternative forms; specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It will be appreciated as the description proceeds that the invention may be realized in different embodiments.
Before describing in detail embodiments, it may be observed that the novelty and inventive step that are in accordance with the present invention reside in construction of the output overvoltage protection and reverse output protection circuit, accordingly, the drawings are showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having benefit of the description herein.
The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device that comprises a list of components does not include only those components but may include other components not expressly listed or inherent to such setup or device. In other words, one or more elements in a system or apparatus proceeded by "comprises... a" does not, without more constraints, preclude the existence of other elements or additional elements in the system

or apparatus or device. It could be noted with respect to the present disclosure that the terms like "an output overvoltage protection and reverse output protection circuit", "the circuit", "the protection circuit" are interchangeably used throughout the description and refer to the same output overvoltage protection and reverse output protection circuit as described in the disclosure.
According to an aspect of the present invention, the output overvoltage protection and reverse output protection circuit is provided that effectively protects the high-performance power supply from the over-voltage events and reverse voltages. Particularly, an advantage of the present invention is that it keeps constant the desired or nominal voltage supply across the load or equipment and protect the same from reverse voltages. This increases the overall reliability of the equipment. The present disclosure achieves these advantage(s) as described below.
As previously discussed, prior solutions for overvoltage protection include use of crowbar/shunting methods with shunting MOSFET or SCR. However, these solutions are still not sufficient as failure of these may cause permanent damage to the equipment and replacement of the equipment or unit will only be the solution. For example, the crowbar circuit depends only upon the fuse and if such fuse is by passed then excessive damage is caused to the equipment. Furthermore, such solutions also lack reverse output protection.
The present invention provides an effective solution to withstand such over voltages and reverse voltages conditions. According to an exemplary aspect of the present invention, the output overvoltage protection and reverse output protection circuit is described with reference to a buck converter. However, it should be noted that, the circuit can be applied to a variety of generic applications.
Fig. 1 illustrates a block diagram for overvoltage protection and reverse output protection circuit according to an aspect of the present invention. The overvoltage protection and reverse output protection circuit block is connected to the buck inductor/converter and a load. The buck converter is further connected to a control unit of an equipment. As the overvoltage protection and reverse output protection circuit is

connected in between the output of buck converter and the load, it keeps constant the desired or nominal voltage supply across the load or equipment during nominal condition and disconnects output voltage during over voltage as well protect the same from reverse voltages. This ensures correct and safe operation of the equipment.
Fig. 2 illustrates a circuit diagram for output overvoltage protection and reverse output protection circuit (200) according to an aspect of the present invention. The output overvoltage protection and reverse output protection circuit is connected between the buck output voltage and the load.
According to an exemplary aspect of the present invention, the output overvoltage protection and reverse output protection circuit (200) comprises at least one input terminal and at least one output terminal. The at least one input terminal receives an input voltage applied from a voltage source such as buck converter's output voltage when the circuit is operational. The at least one output terminal provides an output voltage to the load during operation of the circuit the protection circuit. The circuit further comprises a combination of a field-effect transistor, P-MOSFET (202) with a body diode (201), resistors (203, 206, 205, 209, 211, 212), transistors (204, 207), a Zener diode (208) and a capacitor (210).
The circuit is now described with reference to these components which are also shown in Fig. 2. The field-effect transistor, P-MOSFET (202) having a gate terminal, a source terminal and a drain terminal, the source terminal of the P-MOSFET is connected to a positive terminal of the input voltage and the drain terminal is connected to one of the output terminal and the resistor (203) having a first end and a second end, the first end of the resistor (203) is connected to the gate terminal of the P-MOSFET (202) and the second end is connected to the positive terminal of the input voltage. The transistor (204) having a base terminal, an emitter terminal and a collector terminal, the collector terminal of the transistor (204) is connected to the first end of the resistor (203) and to the gate terminal of the P-MOSFET (202). The resistor (205) having a first end and a second end, the first end of the resistor (205) is connected to the base terminal of the transistor (204) and the transistor (207) having a base terminal, an emitter terminal and a collector

terminal, the collector terminal of the of the transistor (207) is connected to the second end of the resistor (205), the emitter terminal of the transistor (207) is grounded. The resistor (206) having a first end and a second end, the first end of the resistor (206) is connected to the collector terminal of the transistor (207) and the second terminal is connected to the positive terminal of the input voltage.
Further, a combination of the Zener diode (208), the resistor (209) and capacitor forms a voltage regulator circuit and a combination of the resistors (211, 212) forms a voltage divider circuit. The voltage regulator circuit is (208, 209, 210) connected to the base terminal of the transistor (207), the voltage regulator circuit configured to apply a regulated voltage to the base of the transistor (207) for operation of the protection circuit (200). The voltage divider circuit (211, 212) connected in series with the voltage regulator circuit, wherein the voltage divider circuit is configured to supply at least part of input voltage to the voltage regulator circuit during operation. In case when an over voltage is present the voltage regulator circuit (208, 209, 210) becomes operational and applies a regulated voltage to the base terminal of transistor (207) which is sufficient to turn ON the transistor (207), which further causes the transistor (204) and P-MOSFET (202) to turn OFF. Thus, the circuit keeps the desired or nominal voltage supply across the load and disconnects the load from the buck output supply during overvoltage.
According to an exemplary embodiment of the present invention, the body diode (201) of the FET 202, have a negative end (cathode) and a positive end (anode), wherein the negative end of the diode is connected to the source terminal of the P-MOSFET (202) and the positive terminal of the body diode (201) is connected to the drain terminal of the P-MOSFET (202) and to one of the output terminal. In case when a reverse output voltage is present, the body diode (201) is non- operational and thus protects the circuit from reverse voltages.
In the above manner, the protection circuit ensures correct and safe operation of the equipment in either of the conditions of input over voltage and reverse output voltage.
Modes of operation

When an over voltage condition occurs, the Zener diode (208) is turned ON which further turns ON transistor (207). This causes the transistor (204) to turn OFF. Finally, the P-MOSFET (202) connected to the Zener diode (208) is also turned OFF. Turning OFF of the P-MOSFET (202) disconnects output voltage from the load, thereby preventing transmission of power surges to the load and protecting the equipment/unit from damage.
In a normal operation, if the output voltage drops down below certain voltage, the Zener diode Z turns OFF which further turns OFF transistor (207). This causes transistor (204) and P-MOSFET (202) to turn ON, providing the output voltage to the load.
In case of reverse battery scenario at the output side, the diode connected to the P-MOSFET protects the equipment from failure.
The above operations can be clearly understood from the below table:

Buck Output Over-voltage scenario (> 15V*)
(Output to Load: OFF / Disconnects) Normal operation scenario (< 14V*) (Output to Load: ON)
Buck output voltage >15V* V/IN <14V*
Zener diode 208 ON Zener diode 208 OFF
Transistor 207 ON Transistor 207 OFF
Transistor 204 OFF Transistor 204 ON
P-MOSFET 202 OFF P-MOSFET 202 ON
*this value may vary.
It should be noted that, the components used in the output overvoltage protection and reverse output protection circuit are the preferred components/exemplary components for performing the present disclosure. However, these components should not be construed as limiting examples to implement the proposed circuit and can be selected from any available group of components which are suitable to implement the circuit.

Accordingly, from the above disclosure, it may be worth noted that the present invention provides an output overvoltage protection and reverse output protection circuit that effectively protects the high-performance power supply from the automotive over-voltage events.
The foregoing description of the various embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, and instead the claims should be accorded the widest scope consistent with the principles and novel features disclosed herein.
While the invention has been described with reference to a preferred embodiment, it is apparent that variations and modifications will occur without departing the spirit and scope of the invention. It is therefore contemplated that the present disclosure covers any and all modifications, variations or equivalents that fall within the scope of the basic underlying principles disclosed above.

We claim;
1. An output overvoltage protection and reverse output protection circuit (200) comprising at least one input terminal configured to receive an input voltage applied from a voltage source during operation, the protection circuit further comprising at least one output terminal configured to provide an output voltage to a load during operation, the protection circuit comprising:
a field-effect transistor, FET (202) having a gate terminal, a source terminal and a drain terminal, the source terminal of the FET is connected to a positive terminal of the input voltage and the drain terminal is connected to one of the output terminal;
a resistor (203) having a first end and a second end, the first end of the resistor (203) is connected to the gate terminal of the FET (202) and the second end is connected to the positive terminal of the input voltage;
a transistor (204) having a base terminal, an emitter terminal and a collector terminal, the collector terminal of the of the transistor (204) is connected to the first end of the resistor (203) and to the gate terminal of the FET (202);
a resistor (205) having a first end and a second end, the first end of the resistor
(205) is connected to the base terminal of the transistor (204);
a transistor (207) having a base terminal, an emitter terminal and a collector terminal, the collector terminal of the of the transistor (207) is connected to the second end of the resistor (205), the emitter terminal of the transistor (207) is grounded;
a resistor (206) having a first end and a second end, the first end of the resistor
(206) is connected to the collector terminal of the transistor (207) and the second end is
connected to the positive terminal of the input voltage;
a voltage regulator circuit (208, 209, 210) connected to the base terminal of the transistor (207), the voltage regulator circuit configured to apply a regulated voltage to the base of the transistor (207) for operation of the protection circuit (200); and
a voltage divider circuit (211, 212) connected in series with the voltage regulator circuit, wherein the voltage divider circuit is configured to supply at least part of input voltage to the voltage regulator circuit during operation;
wherein the voltage regulator circuit (208, 209, 210) is operational when an overvoltage is present, and configured to apply a voltage to the base terminal of transistor

(207), sufficient to turn ON the transistor (207), which further causes the transistor ( 204) and FET (202) to turn OFF.
2. The protection circuit as claimed in claim 1, wherein the voltage regulator circuit comprises a Zener diode (208) and a resistor (209), wherein the Zener diode (208) is turned ON when the over voltage is present.
3. The protection circuit as claimed in claim 1, wherein the voltage divider circuit comprising two resistors (211, 212).
4. The protection circuit as claimed in claim 1, wherein at least one part of high voltage
supply from the voltage divider circuit is grounded via a capacitor (210).
5. The protection circuit as claimed in claim 1, further comprising a body diode (201) having a negative end and a positive end, wherein the negative end of the diode is connected to the source terminal of the FET (202) and the positive terminal of the body diode (201) is connected to the drain terminal of the FET (202) and to one of the output terminal.
6. The protection circuit as claimed in claim 1, wherein the body diode (201) is not operational when a reverse output voltage is present.

Documents

Orders

Section Controller Decision Date

Application Documents

# Name Date
1 201821037287-IntimationOfGrant09-03-2023.pdf 2023-03-09
1 201821037287-STATEMENT OF UNDERTAKING (FORM 3) [03-10-2018(online)].pdf 2018-10-03
2 201821037287-PatentCertificate09-03-2023.pdf 2023-03-09
2 201821037287-PROVISIONAL SPECIFICATION [03-10-2018(online)].pdf 2018-10-03
3 201821037287-Response to office action [27-02-2023(online)].pdf 2023-02-27
3 201821037287-POWER OF AUTHORITY [03-10-2018(online)].pdf 2018-10-03
4 201821037287-FORM 13 [29-11-2022(online)].pdf 2022-11-29
4 201821037287-FORM 1 [03-10-2018(online)].pdf 2018-10-03
5 201821037287-Written submissions and relevant documents [29-11-2022(online)].pdf 2022-11-29
5 201821037287-DRAWINGS [03-10-2018(online)].pdf 2018-10-03
6 201821037287-DECLARATION OF INVENTORSHIP (FORM 5) [03-10-2018(online)].pdf 2018-10-03
6 201821037287-Correspondence to notify the Controller [11-11-2022(online)].pdf 2022-11-11
7 201821037287-FORM-26 [11-11-2022(online)].pdf 2022-11-11
7 201821037287-DRAWING [03-10-2019(online)].pdf 2019-10-03
8 201821037287-US(14)-HearingNotice-(HearingDate-15-11-2022).pdf 2022-10-20
8 201821037287-CORRESPONDENCE-OTHERS [03-10-2019(online)].pdf 2019-10-03
9 201821037287-COMPLETE SPECIFICATION [03-10-2019(online)].pdf 2019-10-03
9 201821037287-FER.pdf 2021-10-18
10 201821037287-ORIGINAL UR 6(1A) FORM 1-180221.pdf 2021-10-18
10 Abstract1.jpg 2019-10-18
11 201821037287-FORM 18 [30-01-2020(online)].pdf 2020-01-30
11 201821037287-Response to office action [10-05-2021(online)].pdf 2021-05-10
12 201821037287-CLAIMS [09-02-2021(online)].pdf 2021-02-09
12 201821037287-PETITION UNDER RULE 137 [09-02-2021(online)].pdf 2021-02-09
13 201821037287-COMPLETE SPECIFICATION [09-02-2021(online)].pdf 2021-02-09
13 201821037287-OTHERS [09-02-2021(online)].pdf 2021-02-09
14 201821037287-FER_SER_REPLY [09-02-2021(online)].pdf 2021-02-09
15 201821037287-COMPLETE SPECIFICATION [09-02-2021(online)].pdf 2021-02-09
15 201821037287-OTHERS [09-02-2021(online)].pdf 2021-02-09
16 201821037287-CLAIMS [09-02-2021(online)].pdf 2021-02-09
16 201821037287-PETITION UNDER RULE 137 [09-02-2021(online)].pdf 2021-02-09
17 201821037287-Response to office action [10-05-2021(online)].pdf 2021-05-10
17 201821037287-FORM 18 [30-01-2020(online)].pdf 2020-01-30
18 Abstract1.jpg 2019-10-18
18 201821037287-ORIGINAL UR 6(1A) FORM 1-180221.pdf 2021-10-18
19 201821037287-COMPLETE SPECIFICATION [03-10-2019(online)].pdf 2019-10-03
19 201821037287-FER.pdf 2021-10-18
20 201821037287-CORRESPONDENCE-OTHERS [03-10-2019(online)].pdf 2019-10-03
20 201821037287-US(14)-HearingNotice-(HearingDate-15-11-2022).pdf 2022-10-20
21 201821037287-DRAWING [03-10-2019(online)].pdf 2019-10-03
21 201821037287-FORM-26 [11-11-2022(online)].pdf 2022-11-11
22 201821037287-Correspondence to notify the Controller [11-11-2022(online)].pdf 2022-11-11
22 201821037287-DECLARATION OF INVENTORSHIP (FORM 5) [03-10-2018(online)].pdf 2018-10-03
23 201821037287-DRAWINGS [03-10-2018(online)].pdf 2018-10-03
23 201821037287-Written submissions and relevant documents [29-11-2022(online)].pdf 2022-11-29
24 201821037287-FORM 1 [03-10-2018(online)].pdf 2018-10-03
24 201821037287-FORM 13 [29-11-2022(online)].pdf 2022-11-29
25 201821037287-Response to office action [27-02-2023(online)].pdf 2023-02-27
25 201821037287-POWER OF AUTHORITY [03-10-2018(online)].pdf 2018-10-03
26 201821037287-PROVISIONAL SPECIFICATION [03-10-2018(online)].pdf 2018-10-03
26 201821037287-PatentCertificate09-03-2023.pdf 2023-03-09
27 201821037287-STATEMENT OF UNDERTAKING (FORM 3) [03-10-2018(online)].pdf 2018-10-03
27 201821037287-IntimationOfGrant09-03-2023.pdf 2023-03-09

Search Strategy

1 201821037287SEARCHSTRATEGYAE_27-08-2021.pdf
1 TPOSEARCHSTRATEGY201821037287E_06-09-2020.pdf
2 201821037287SEARCHSTRATEGYAE_27-08-2021.pdf
2 TPOSEARCHSTRATEGY201821037287E_06-09-2020.pdf

ERegister / Renewals

3rd: 05 May 2023

From 03/10/2020 - To 03/10/2021

4th: 05 May 2023

From 03/10/2021 - To 03/10/2022

5th: 05 May 2023

From 03/10/2022 - To 03/10/2023

6th: 11 Aug 2023

From 03/10/2023 - To 03/10/2024

7th: 30 Sep 2024

From 03/10/2024 - To 03/10/2025

8th: 02 Sep 2025

From 03/10/2025 - To 03/10/2026