AN ULTRA COMPACT MULTI-BAND TRANSMITTER WITH ROBUST AM-PM DISTORTION SELF-SUPPRESSION TECHNIQUES REFERENCE TO RELATED APPLICATION [0001] This application claims priority to U.S. application number 15/068,179 filed on March 11, 2016, the contents of which are incorporated by reference in their entirety. BACKGROUND [0002] Modern wireless systems utilize multi-band and multi-mode operations to simultaneously support multiple different communication standards. These rapidly growing demands have posed tremendous challenges for future radio frequency (RF) transmitter development and especially power amplifiers (PA). One popular solution for multi-band PAs is to directly assemble several single-band PAs either in a chip or on a multiple-chip module. This approach, however, can have several drawbacks, such as large chip/module area, increased cost, dedicated antenna interface to each PAs, possible need of off-chip switches and complicated packaging. Tunable passive networks can also be utilized to achieve multi-band impedance matching and power combining for RF PAs. Those tunable components often pose a direct trade-off among passive loss and frequency range and suffer from reliability concerns of tunable components such as varactors and a switch -cap banks. BRIEF DESCRIPTION OF THE DRAWINGS [0003] FIG. 1 illustrates an exemplary communication device comprising at least an exemplary power amplifier in accordance with various aspects described; [0004] FIG. 2 illustrates an exemplary drive circuit and power amplifier in accordance with various aspects described; [0005] FIG. 3 illustrates a power amplifier component in accordance with various aspects described; [0006] FIG. 4 illustrates an example graph of compensation and an output passive network in accordance with various aspects described; [0007] FIG. 5 illustrates an example output passive network in accordance with various aspects described; [0008] FIG. 6 illustrates an example simulation graph of related to an example power amplifier in accordance with various aspects described; [0009] Fig. 7 illustrates a flow diagram of an exemplary method in accordance with various aspects described. [00010] FIG. 8 illustrates an exemplary mobile communication device having a power amplifier component system in accordance with various aspects described. DETAILED DESCRIPTION [00011] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms "component," "system," "interface," and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor, a process running on a processor, a controller, an object, an executable, a program, a storage device, an electronic circuit and/or a computer with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other components can be described herein, in which the term "set" can be interpreted as "one or more." [00012] Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term "comprising". [00013] In consideration of the above described deficiencies and continued objectives, various aspects for a multi-band communication device, such as a transmitter that can be a highly linear dual-band mixed-signal polar power amplifier architecture, can offer a fully integrated single-chip solution in bulk CMOS technology while eliminating or significantly reducing amplitude modulation to phase modulation distortions being generated in the power amplification stages. Embodiments herein disclose a power amplifier with self-suppression or self-compensation bias scheme techniques for communication/mobile devices that involve simultaneous dual-band operation, load-pull impedance matching, parallel power combining and even-order harmonic rejection to maximize power amplifier efficiency with one compact on-chip transformer without any tunable passive elements or switches. [00014] A communication device, for example, can be a transmitter or transceiver of a mobile phone, or other mobile communicating system that can include a power amplifier that self-mitigates phase distortion as part of the amplification modulation, which can be referred to as amplitude modulation to phase modulation (AM-PM) distortion. AM-PM distortion can refer to a form of nonlinear phase distortion caused by nonlinear characteristics of a circuit component (e.g., a power amplifier) as a function of the input amplitude. As the input amplitude is modulated, the phase modulation of the output can behave in a nonlinear manner and then cause increased out-of-band noise, as well as an increase in error vector magnitude (EVM). [00015] The power amplifier system being disclosed, for example, can operate to utilize the inherent parasitic capacitances of the output stage (output passive network) of the power amplifier to minimize the overall capacitance variation responsible for the phase distortion. For example, a power amplifier with a plurality of unit power amplifier cells can receive driver signals according to an operating band of input signals being processed, and an output passive network can combine signals from each unit power amplifier cell, delivering the power to an antenna or antenna port, and further suppressing an AM-PM distortion by utilizing flat-phase response of a multi-resonance structure. [00016] The unit power amplifier cells can include several capacitive units in parallel, which are absorbed by the output passive network and become a part of output passive network. The capacitors can be integrated as part of the different unit power amplifier cells for capacitances across various transistor terminals therein. For example, these capacitors can be across the drain, source and gate terminal of transistors of each unit power amplifier cells, and can be charged and discharged in response to the course of power amplifier. During power back-off mode, certain capacitive cells can be manipulated with a suppression component having transistors that operate at predetermined modes of operation to activate or deactivate. The parasitic capacitances being generated can thus be further controlled in a way that mitigates the AM-PM distortion at the output of the power amplifier with the output passive network in order to implement a self-suppression scheme for suppression of inherent parasitic capacitances causing phase distortion. [00017] In addition, the output passive network of the power amplifier can be coupled to or integrated with the power amplifier as a multi-resonance network to perform impedance matching, power combining, even harmonics suppression and differential to single-ended conversion across a wide frequency range (one octave) with a single transformer footprint. Additional aspects and details of the disclosure are further described below with reference to figures. [00018] Referring to FIG. 1, illustrated is an exemplary communication or mobile device 100 comprising a power amplifier in accordance with various aspects being described. The communication device 100 can comprise a mobile or wireless device, for example, and can further include a digital baseband processor 102, an RF frontend 104 and an antenna port 108 for connecting to an antenna 106. The device 100 can comprise an exemplary power amplifier 110 as a part of the digital baseband processor 102 or the RF frontend 104. The digital baseband processor 102 or the RF frontend 104 can comprise such a power amplifier 110 or multiple power amplifiers operating or coupled in parallel. The RF frontend 104 can be coupled to the digital baseband processor 102 and the antenna port 108, which is configurable with the antenna 106. [00019] In one aspect, the power amplifier 110 can operate to provide a power signal along a transmitter path for transmissions according to various operating bands. The power amplifier 110 can operate in multi-band or multi-mode operations to simultaneously support multiple communication standards with various operating bands. Rapidly growing demands have posed challenges for future radio frequency (RF) transmitter development, especially power amplifiers. One solution for a multi-band power amplifier can be to directly assemble several single-band PAs either in a chip or on a multiple-chip module. However, this can possibly incur large chip/module area, increased cost, a dedicated antenna interface to each power amplifier, possibly the need for off-chip switches or complicated packaging. Additionally, tunable passive networks can also be utilized to achieve multi-band impedance matching and power combining for RF power amplifiers. However, these solutions suffer from the direct trade-off among passive loss and tunning range as well as the reliability concerns. To address at least some of these issues, the power amplifier 110 can comprise a highly linear dual-band mixed-signal polar power amplifier architecture, which offers a fully integrate single-chip solution in bulk CMOS technology according to various aspects or embodiments described. [00020] In one example, the power amplifier 110 can comprise a plurality of power amplifiers components or unit power amplifier cells, each configured to provide the power signal along the transmitter path (e.g., path to antenna port 108) based on driver signals being received according to one or more operating bands or frequencies. The power amplifier 110 can be further integrated to an output passive network that can be a matching network component. This output stage can combine power signals processed from the different unit power amplifier cells / components of the power amplifier 110. This output passive network of the power amplifier 110, for example, can further operate to suppress an AM-PM distortion or phase distortion at an output based on or as a function of the power amplifier 110 operating in a back¬off power mode or a saturation power mode. As such, the output passive network of the power amplifier component 110 can utilize the flat-phase response across the wide frequency range to achieve robust phase response against to the non-linear output capacitance variation of the power amplifier. For example, the power amplifier component 110 can operate to adjust a bias of any number of the unit power amplifier cell components of the power amplifier 110 to minimize an overall drain capacitance variation of along a full operating power range of operation or operational frequency range of operation. As such, the output passive network of the power amplifier 110 can operate as a multi-resonance network to perform impedance matching, power combining, even harmonics suppression and differential to single-ended conversion across a wide frequency range (one octave) with a single transformer footprint. The output passive network (matching resonance network component) of the power amplifier component 110 can further provide a flat-phase response across a wide bandwidth, so that a change in output capacitance leads to minimum signal phase change. Thus, the power amplifier 110 can generate an excellent AM-PM performance across a wide bandwidth. [00021] Referring to FIG. 2, illustrated is an example communication system with a power amplifier (PA) 110' in accordance with various aspects or embodiments. The PA 110' (e.g., a CMOS power amplifier or other PA) can comprise a driver stage component 202, unit PA cell component(s) 204, and an output passive network or an impedance matching network 206 for generating a power signal for transmissions involved in multi-band (e.g., uplink and downlink frequency operating bands) and multi-mode operations concurrently with different communication standards (e.g., LTE, 3GPP, etc.). The PA 110' can generate AM-PM self-suppression to output signals, which exploits the inherent PA output power stage parasitic capacitance to compensate the non-linear capacitance variation. The output passive network 206 can further operate as a multi-resonant matching network with flat-phase response is also used to minimize residual AM-PM distortion throughout operation of the PA 110' over the back-off mode of operation and a saturation mode of operation. For example, the PA 110' can operate to generate an minimized AM-PM distortion or phase distortion due to the non-linear capacitance of one or more unit PA cells, such as by mitigating one or more parasitic capacitances coupled to one or more transistors (e.g., M1-4 as PMOS, NMOS or another transistor type) of each activated unit PA cell 204. [00022] The driver stage 202 comprises one or more driver stage components X1 - X2n"1 along one or more single or differential drive paths for generating driver signals for power amplification at the PA 110'. The driver stage components X1 -X2n"1 process electronic signals (e.g., radio frequency (RF) voltage signals, VRF", VRF+, or the like), and provide a regulated drive signal to the unit PA cell components 204. The driver stage component(s) 202 can each include one or more comparators or amplifiers 208 and 210 associated with a differential drive path, respectively. The driver stage 202 can operate to regulate or control the unit PA cell components 204 by providing bias signals or driver signals to gates of the transistors (e.g., M1 and M2) as well provide a voltage bias (Vbias) to the gates of the thick oxide transistors M3 and M4, for example, according to different modes of operation (e.g., a saturation mode, a back-off power mode) and as a function of one or more different operating bands being processed according to the application of the PA 110'. A drive signal can thus maintain operation of subsequent stages of the PA 110' according to different characteristics of the unit PA cell components 204. [00023] In one example, the unit PA cell components 204 power / driver signals from the driver stage components 202 for operating one or more transistors M3 and M4 in a back-off mode and a saturation mode. The back-off mode can refer herein to a decrease in power being supplied or provided at the unit PA cell components 204 or any group of transistors, such as M3 and M4 together. The saturation mode can refer to an increase in power where the PA components (e.g., each unit PA cell component 204, the PA component 204, transistor M3 or transistor M4) are fully operational or powered, such as above a threshold voltage for thick oxide transistors M3 and M4, or the transistors M1 and M4. Although the PA 110' is illustrated with differential paths, a single transmission path can also be envisioned as one or ordinary skill in the art could appreciate. [00024] The PA 110' could generate AM-PM distortion or phase distortion as a result of changes in the amplitude as well as the fluctuation of various capacitances of the unit PA cell components 204, such as from the capacitances Cgs, Cgd, and Cdb. The capacitors Cgs provides a capacitance across the source terminal and the gate terminal, which receives driver signals for driving or powering the transistors M3 and M4. The capacitors Cgd of the unit PA cell components 204 provides a capacitance between the gate terminal and drain terminals of transistors M3 and M4. [00025] The transistors M3 and M4 can comprise thick-oxide transistors that have a thicker oxide layer than the transistors M1 and M2 comprising thin-oxide transistors having a smaller or thinner oxide layer. For the PA 110' cascode topology as illustrated in FIG. 2, the capacitors Cgd of the thick-oxide transistors M3 and M4 can be the main contributors of the AM-PM distortion of the PA 110' as capacitors Cgd can be more non-linear with respect to the power / voltage swing level and further are directly loaded at the output passive network 206 of the PA 110'. This non-linear capacitance Cgd loading to the output passive network 206 of PA 110' can shift the resonance frequency of the output passive network 206 of the PA 110' (resonance frequency can normally be tuned at the maximum power level), resulting in the phase distortion according to the output power level (as in AM-PM distortion). The capacitance of capacitor Cgd can be related to the width (W) and length (L) of the transistor device (e.g., M3, M4), the gate-drain overlap capacitance per unit width (Cov) and the total gate capacitance (Cgg). [00026] One way to address the AM-PM phase distortion generated from the power amplifier component 110' is to compensate the phase distortion of the unit PA cells 204 at the driver stages 202 using a varactor or capacitor bank based on a look-up table. However, additional memory and processor power could be utilized, which increases the cost and reduces the overall power efficiency, which is especially true for wideband modulated signals (>20MHz). Therefore, the unit PA cell components 204 or output power stage 204 comprises a self-compensating function (e.g., a suppression component) with respect to the non-linear capacitance variations, without introducing extra components: as the power is reduced, the bias of the unit PA cells 204 while in a turned off state (back-off mode) can be adjusted to minimize the overall drain capacitance variation. [00027] In one embodiment, as the voltage swing at the drain node of M3 and M4 is increasing (PA power increasing), the cascode transistors (M3 and M4) or the thick oxide transistors are operated for a longer time in the triode region or mode of operation where each capacitor Cgd presents a larger capacitance (WxCov+WxLxCgg/2) than the capacitances of each Cgd being operated in a saturation region (WxCov) or mode of operation. In other words, when the PA 110' output power is decreasing (back-off mode of operation), the PA 110' effective capacitance (Cdev) at the drain of the cascode transistors (M3 and M4) is decreasing. [00028] In one embodiment, the output power network 204 can self-compensate for the phase distortion for an effective capacitance reduction at the power back-off mode of the PA 110', without additional components, by utilizing the parasitic capacitance Cds of the cascode transistors (M3 and M4) via the suppression component 220 comprising transistors M1 and M2, for example. Rather than compensating for the phase distortion of the PA 110' at the driver stages, such as by using a varactor or capacitor bank together with a look-up table, the unit PA cell components 204 can utilize its own components to self-compensate or mitigate phase distortion. The suppression component utilizes an inherent parasitic capacitance of the power amplifier component 220 to self-compensate a nonlinear capacitance variation at the output. [00029] For example, each of the unit PA cells 204 can include corresponding unit PA cells Y1 - Y2n"1 that can operate in a power-on and a power-off mode depending upon a change in. As such, during operation the unit PA cells Y1 - Y2n"1 with transistors M3 and M4 can fluctuate between increasing in power during a power-on phase or mode and a power-off phase or mode of operating. The power-on mode can comprise saturation mode, for example, in which the PA and any number of output power networks Y1 - Y2n"1 of the output power stage 204 are being fully powered. [00030] Additionally, the power-off phase or mode can be the back-off mode where power is being decreased or the output power network of the unit PA cell components 204 is powered down or off. Incidental to this operation, parasitic capacitance is still being generated, but this parasitic capacitance is not affecting the output because the capacitors Cds can be effectively floating during the back-off mode of operation since both the thin oxide transistors M1 and M2 are powered off. [00031] The suppression component 220 can include the transistors M1 and M2, for example. The suppression component 220 can operate to adjust a bias of transistors of M1, M2, M3, and M4.The capacitor or capacitive unit of Cds across the drain and source of the thick oxide transistors M3 and M4 of each unit PA cell components 204 of Y1 - Y2n"1 are manipulated to minimize an overall capacitance variation in the back-off power mode. The parasitic capacitance of the PA 110' or one or more unit PA cells 204 can have a nonlinear behaviour with respect to a power level where the effective parasitic capacitance is decreasing as power is decreasing. Therefore, the parasitic capacitance varies between the different modes of a back-off mode and a saturation mode of operation. The self-suppression or self-compensation bias scheme generated by the suppression component can linearize the non-linear parasitic capacitance behavior of the PA 110'. The suppression component 220 thus enables a continued base line operation and minimizes an overall capacitance variation to reduce the phase distortion being generated due to the changes in a parasitic capacitance between the different modes of normal operation. Additional details of the operation of the suppression component 220 are illustrated and described below with reference to FIG. 3. [00032] In another embodiment, the output passive network 206 (as an impedance matching network) can be implemented with a single transformer. The single transformer for output passive network 206 include two inductors; one for magnetizing inductance and the other for leakage inductance, parasitic capacitors, and absorb the power amplifier output capacitors to provide a real impedance transformation or a flat-phase response to the PA 110' along a broad bandwidth (e.g., about 2.4 GHz to about 5.5GHz, or other broad band). For example, the output passive network 206 can operate as a multi-resonance network to perform impedance matching, power combining, even harmonics suppression and differential to single-ended conversion across a wide frequency range (one octave) with a single transformer footprint. The output passive network 206 can further generate or provide a flat-phase response across a wide bandwidth or at least two different operating frequency bands (e.g., about 2 GHz and 5.5 GHz), so that a change in output capacitance due to the non-linear capacitance of the power amplifier leads to minimum signal phase change. The flat-phase response generated by the output passive network 206 can effectively suppress the AM-PM distortion. This leads to excellent AM-PM performance across the wide bandwidth range. [00033] An advantage of the PA 110' is it utilizes the PA transistor's (e.g., M3 and M4) inherent parasitic capacitance to self-compensate or linearize the non-linear capacitance variations, which provides a highly efficient and compact scheme at PA back-off modes of operation among or back forth between back-off and saturation mode. Compared to a multi-band PA which uses individual output matching networks, the proposed multi-band PA output stage utilizes only one compact passive transformer as the matching resonance network component 206, which can provide parallel output power combining, output impedance matching, even-order harmonic rejection and differential to single-ended conversion across a wide bandwidth without any lossy tunable passive elements or switches. Another advantage is that the PA 110' can significantly reduce the transmitter area by factor of 2x or more and maximize the PA efficiency. Additionally, for example, the proposed PA 110' architecture achieves excellent AM-PM characteristic (<3°), about 30 ~ 40% power added efficiency (PAE), with 2.05% error vector magnitude (EVM) and 256 quadrature amplitude modulation QAM and can cover the wide frequency range (1:2 range) with ultra-compact area which is the state-of-art performance among CMOS PAs. [00034] Referring to FIG. 3, illustrated is an additional example of a unit PA cell component 204 for a PA in accordance with various aspects or embodiments being described. Further, the PA component 204 or PA 110' discussed herein is not limited to digital PAs and can also be used with analog PAs, or a combination thereof. The example unit PA cell components 204 depicts operation of the output power networks Y1 - Y2n"1 in two different power stages that can change or alternatingly operate during different power levels of operation of the PA 110 or 200. [00035] In one embodiment, the unit PA cell components 204' can operate to generate self-compensation or self-suppression of nonlinearities being generated by the parasitic capacitances generated by the different powering on and off modes (back-off or saturation modes). For example, a first power stage comprises the saturation (active) mode of operation 302 where the output power networks Y1 -Y2n"1 of the unit PA cell components 204 operate with full or complete power above a threshold voltage so that the transistors M3 and M4 of any one of the networks Y1 -Y2n"1 are operational, and a channel has been created for current flow. This allows current to flow between the drain and source. Since the drain voltage is higher than the source voltage, the current flow of electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. [00036] In contrast, a back-off mode 304 of operation occurs when the power is decreased normally and power is backed off so that the transistors M3 and M4 are cut-off or in sub-threshold mode. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there can be a weak-inversion current, sometimes called subthreshold leakage. The subthreshold l-V curve can depend exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage, for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations can complicate optimization for leakage and performance. [00037] The unit PA cells 204 can comprise n-bit binary weighted power cells with a differential cascode amplifier topology. A digital switching PA scheme is illustrated in FIG. 3 that operates to turn-on/off the binary weighted unit power amplifier cells Y1 - Y2n"1 to control the amplitude. For example, when the unit PA cell (Y1) is turned-on in saturation/power mode 302, the cascode transistors (M3 and M4) can be biased at a high voltage (above a threshold voltage or a saturation power level) and the thin- gate transistors (M1 and M2) can be driven differentially (differential pulse 306 and 308 by the driver stage 202 of FIG. 2). When the unit PA cell (Y1) is turned-off in sub-threshold voltage or back-off mode 304, the cascode transistors (M3 and M4) can be biased at a low voltage (below a threshold voltage as LOW < VTH)- However, in response to the thin-gate transistors (M1 and M2) being turned off as well AM-PM distortion can exist. [00038] In one embodiment, the suppression component 220 operates to take into consideration the Cds of the cascode transistors (M3 and M4), when the unit PA cells 204 are turned off (or power is decreasing in back-off mode). During back-off mode of operation only a small portion of Cds is loaded at the drain, as the thin-gate transistors are completely turned off and one terminal of the Cgd is effectively floating. When the power cell is turned-off or in back-off mode 304, the cascode transistors (M3 and M4) can be biased at a low voltage below a threshold voltage (