1. An ultra-wide dynamic range digital receiver, the receiver comprising:
at least one coarse analog to digital convertor and at least one fine analog to digital convertor to receive analog intermediate frequency as a input and convert the received analog intermediate frequency in to 16 bit digital signal at sampling frequency, wherein the coarse ADC receives high level intermediate frequency and the fine ADC receives low level intermediate frequency;
a field programmable gate array (FPGA) coupled to coarse and fine ADC to receive the digitally converted intermediate frequency at sampling rate and implementing architecture of ADC Combiner, Mixer, NCO, Linear phase FIR Filter, Decimator and DPRAM to improve the dynamic range of receiver;
a control and data section device coupled to FPGA which translates the external control signals into FPGA compatible signals and FPGA output data into external device compatible signals;
a regulators section comprising of DC-DC converter and LDOs coupled to FPGA, wherein the regulators section generates the required voltage level for operation of FPGA, ADCs and other ICs of the board;
a plurality of reference clocks signals sections coupled to the FPGA, where the sections are required for generation of sampling clock, other clocks and reference signals required for the Digital Receiver; and
a controller coupled to the FPGA to transfer data from digital receiver to Digital Signal Processor and from radar Controller to the digital receiver.
2. The digital receiver as claimed in claim 1, wherein the coarse ADC receives IF signal from IF receiver with no gain and fine ADC receives IF signal with a gain of 36dB, where the output of the two ADCs (16 bit) is combined to
generate 22 bits in ADC Combiner based on value of Coarse ADC data.
3. The digital receiver as claimed in claim 1, wherein the separation between coarse and fine channel is changed to any value from 24-42dB (in step of 6dB) based on tradeoff between operating near to noise floor and smooth transition from Coarse to Fine channel.
4. The digital receiver as claimed in claim 1, wherein the ADC Combiner selects either Coarse IF signal or Fine IF signal based on the IF signal strength, where any of the 6 MSBs (leaving Sign bit) of the coarse ADC is non-zero (indicating a strong signal), then the coarse ADC value is chosen and 6 zeros are appended at the Least Significant end, and
if all the 6 MSB bits of the coarse ADC are zeros (indicating a weak signal) then the Fine ADC value is chosen and 6 zeros are appended to the Most Significant end by retaining the Sign bit (to compensate 36dB gain provided in receiver front end in Fine channel).
5. The digital receiver as claimed in claim 1, wherein the ADC Combiner in FPGA combines the Coarse and Fine ADC 16 bit data to 22 bit data based on value of Coarse ADC data.
6. The digital receiver as claimed in claim 1, wherein the strength of the signal is determined using previous 5 samples.
7. The digital receiver as claimed in claim 1, wherein the 22 bit data from ADC combiner is piped to the Mixer block, where this block separates the incoming digitized data into its In-phase and Quadrature phase components.
8. The digital receiver as claimed in claim 1, wherein the output from Mixer is passed through a Linear Phase FIR filter to filter out the out of interest band signals (i.e. Sin + SNCO signal).
9. The digital receiver as claimed in claim 1, wherein the output from FIR Filter is passed through decimator which decimates the signal by factor equal to decimation factor, where the decimation factor is again configurable and selected based on mode of operation of Radar to match the output data rate equal to bandwidth of transmitted pulse.
10. The digital receiver as claimed in claim 1, wherein the output from Decimator is fed to DPRAM module which controls the read and writes operations of the DPRAM for proper transfer of data from Digital Receiver to DSP using VME or Ethernet interface.
11. A method to increase dynamic range of Digital Receiver without varying the Receiver front end gain based on return strength, the method comprising:
splitting an analog intermediate frequency signal into a high level intermediate frequency and a low level intermediate frequency with a gain difference of 36dB, where the high level intermediate frequency is allowed to pass through a coarse ADC and the low level intermediate frequency is allowed to pass through a fine ADC;
selecting between coarse and fine ADC output based on the return strength of coarse ADC; and
feeding the selected data to ADC combiner where data is converted into 22bit format based on whether coarse ADC or Fine ADC data is selected.
, Description:FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
(See section 10, rule 13)
“An ultra-wide dynamic range digital receiver“
By
Bharat Electronics Limited,
Central Research Laboratory
Jalahalli P.O., Bangalore – 560013

The following specification particularly describes the invention and the manner in which it is to be performed.

Field of the invention
The present invention mainly relates to digital receiver and more particularly to an ultra-wide dynamic range digital receiver which increases the dynamic range of Digital Receiver without varying the Receiver front end gain based on return strength.
Background of the invention
A digital receiver is well known in the art which is an electronic system for digital communications receiving an analog input signal and providing a digital output signal, and includes an amplifier, a filter, and a digitizer in the analog front-end. The amplifier increases the input dynamic range of the receiver, thus helpfully providing a good level of the analog output signal, the filter limits the noise bandwidth of the receiver, and the digitizer converts the analog input signal into the digital output signal.
The Receiver operating characteristic curve provide information about accuracy of measurement of a receiver in the presence of noise and the ability of receiver to detect weak targets in the presence of noise gives the information about the sensitivity of receiver. The dynamic range of the receiver is the difference of highest signal level detection capability to lowest signal level detection capability.
Earlier Receiver systems were analog but with the advent of digital signal processing technology which possesses many advantages compared to analog counterpart, analog receiver is substantially replaced by digital receiver. In Digital Receiver each analog sensor signals should be converted to digital signals using ADC. The major limiting factor in the dynamic range of Digital receiver is quantization noise introduced by ADC. Effective no of bits (ENOB) of an ADC is given by
ENOB = (SI NAD - 1.76)/6.02.
So, a digital receiver can have a dynamic range of maximum of around 77dB only using 16 bit ADC (typical SINAD is 78dBFS) at nyquist rate, without using any receiver front end gain control techniques. But in Doppler Weather Radar and many other radar applications return target strength typically varies from -10dBm to -110dBm, which requires digital receiver to cater dynamic range of 100dB.
For example, in US3781883 discloses an automatic dynamic range control system that eliminates the effect of dynamic range limitations in the main radar channel and restores the signal amplitude prior to detection. A separate auxiliary measurement channel is provided in parallel with the main IF channel having a logarithmic amplifier or sequential detector with sufficient dynamic range to meet the signal informational requirements.
Further, in US4652882 discloses a monopulse receiver, wherein a desired wide dynamic range is achieved for range gated monopulse sum and difference signals. It uses a multiplexer for time-multiplexing such signals and a second receiver channel responsive to the time-multiplexed Signals, each such channel having a dynamic range less than the desired wide dynamic range and greater than one-half the desired wide dynamic range.
Moreover, in US4804963 discloses a wide dynamic range digital receiver for radar or sonar applications wherein the wide dynamic range is achieved by increasing the sampling rate of the received signals through the use of a special purpose micro programmed digital receiver processor implemented with a plurality of processing elements especially designed for performing sum of products computations on a pipelined basis.
Therefore there is a need in the art with the improved digital receiver to solve the above mentioned limitations.
Summary of the Invention
An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.
Accordingly, in one aspect of the present invention relates to an ultra-wide dynamic range digital receiver, the receiver comprising: at least one coarse analog to digital convertor and at least one fine analog to digital convertor to receive analog intermediate frequency as a input and convert the received analog intermediate frequency in to 16 bit digital signal at sampling frequency, wherein the coarse ADC receives high level intermediate frequency and the fine ADC receives low level intermediate frequency, a field programmable gate array (FPGA) coupled to coarse and fine ADC to receive the digitally converted intermediate frequency at sampling rate and implementing architecture of ADC Combiner, Mixer, NCO, Linear phase FIR Filter, Decimator and DPRAM to improve the dynamic range of receiver, a control and data section device coupled to FPGA which translates the external control signals into FPGA compatible signals and FPGA output data into external device compatible signals, a regulators section comprising of DC-DC converter and LDOs coupled to FPGA, wherein the regulators section generates the required voltage level for operation of FPGA, ADCs and other ICs of the board, a plurality of reference clocks signals sections coupled to the FPGA, where the sections are required for generation of sampling clock, other clocks and reference signals required for the Digital Receiver and a controller coupled to the FPGA to transfer data from digital receiver to Digital Signal Processor and from radar Controller to the digital receiver.
Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.
Brief description of the drawings
The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:
Figure 1 shows a block diagram of UWB Digital Receiver according to one embodiment of the present invention.
Figure 2 shows a block diagram of firmware according to one embodiment of the present invention.
Figure 3 shows a state diagram of ADC Combiner according to one embodiment of the present invention.
Figure 4 shows a simulation plot of input and output signal according to one embodiment of the present invention.
Figure 5 shows a linearity plot of input and output signal power according to one embodiment of the present invention.
Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure.
Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.
Detailed description of the invention
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces.
By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.
Figs. 1 through 5, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way that would limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged communications system. The terms used to describe various embodiments are exemplary. It should be understood that these are provided to merely aid the understanding of the description, and that their use and definitions, in no way limit the scope of the invention. Terms first, second, and the like are used to differentiate between objects having the same terminology and are in no way intended to represent a chronological order, unless where explicitly stated otherwise. A set is defined as a non-empty set including at least one element.
The present invention relates to an effective method to increase the dynamic range of Digital Receiver better than 110dB using two ADC (Coarse and Fine) per channel without varying the Receiver front end gain based on return strength. Further, the present invention completely eliminates the need of conventional STC and AGC circuit. In the present invention the IF signal is first split into Coarse Channel and Fine channel using splitter with 36dB gain difference then they are digitized using two 16 bit ADCs namely Coarse ADC and Fine ADC. Coarse ADC and Fine ADC output combined digitally, using ADC combining logic to extend the dynamic range of receiver. The Combination logic is based on the value of Coarse ADC and due to digital combination of two ADCs data transition region from one ADC to another ADC is very smooth. Using ADC Combiner architecture 110dB dynamic range is achieved with an accuracy of 0.5dB however the dynamic range can be further increased by operating the ADC at sampling rate greater than nyquist rate.
Figure 1 shows a block diagram of Ultra Wide Band (UWB) Digital Receiver according to one embodiment of the present invention.
The figure shows the block diagram of Ultra Wide Band (UWB) Digital Receiver. The input to digital receiver is IF split into Coarse and Fine channel. The channel separation of 36dB is maintained between Coarse and Fine channel, with Coarse at no gain. The coarse channel is used for input signal of maximum strength to 36dB down from maximum while Fine channel is used for last 74dB of dynamic range. So, the combined dynamic range of 110dB is achieved based on ADC Combiner logic implemented in FPGA. The block diagram is divided into five sections namely ADC, FPGA, Control and Data, Regulators and Reference clock and Signals section.
The ADC section contains the Analog to Digital converter (ADC, 16 bit), anti-aliasing filters and all the related circuits. For each channel one ADC is used i.e. one for coarse input and another for Fine input. The ADCs converts an incoming IF analog signal to a 16 bit digital signal, sampling the input signal at sampling frequency. The sampled signal is then processed in FPGA to down convert it digitally. The FPGA is used to implement all the firmware is shown in figure 2.
Figure 2 shows a block diagram of firmware according to one embodiment of the present invention.
The figure shows the block diagram of firmware. A control and data section consists a device which acts as a bridge, that translates the external control signals into FPGA compatible signals and FPGA output data into external device compatible signals. The control signals are used to configure different operating mode of digital receiver. The processed data in the FPGA memory has to be transferred to the Digital Signal Processor (DSP) board through the Control and Data section, which can be either VME or Ethernet interface. Regulators section consist of DC-DC converter and LDOs, which are responsible for generation of all the voltage level required for operation of FPGA, ADCs and other ICs of the board. The reference clocks and other reference signals sections coupled to the FPGA consists of circuitry required for generation of sampling clock, other clocks and reference signals required for the Digital Receiver. The figure shows block diagram of functions implemented in FPGA. The coarse ADC [1] accepts IF signal from IF receiver with no gain and Fine ADC [2] accepts IF signal with a gain of 36dB.The output of the two ADCs (16 bit) is combined to generate 22 bits in ADC Combiner [3].
In one embodiment, the present invention an ultra-wide dynamic range digital receiver, the receiver comprising: at least one coarse analog to digital convertor and at least one fine analog to digital convertor to receive analog intermediate frequency as a input and convert the received analog intermediate frequency in to 16 bit digital signal at sampling frequency, wherein the coarse ADC receives high level intermediate frequency and the fine ADC receives low level intermediate frequency, a field programmable gate array (FPGA) coupled to coarse and fine ADC to receive the digitally converted intermediate frequency at sampling rate and implementing architecture of ADC Combiner, Mixer, NCO, Linear phase FIR Filter, Decimator and DPRAM to improve the dynamic range of receiver, a control and data section device coupled to FPGA which translates the external control signals into FPGA compatible signals and FPGA output data into external device compatible signals, a regulators section comprising of DC-DC converter and LDOs coupled to FPGA, wherein the regulators section generates the required voltage level for operation of FPGA, ADCs and other ICs of the board, a plurality of reference clocks signals sections coupled to the FPGA, where the sections are required for generation of sampling clock, other clocks and reference signals required for the Digital Receiver and a controller coupled to the FPGA to transfer data from digital receiver to Digital Signal Processor and from radar Controller to the digital receiver.
The coarse ADC receives IF signal from IF receiver with no gain and fine ADC receives IF signal with a gain of 36dB, where the output of the two ADCs (16 bit) is combined to generate 22 bits in ADC Combiner. The separation between coarse and fine channel is changed to any value from 24-42dB (in step of 6dB) based on tradeoff between operating near to noise floor and smooth transition from Coarse to Fine channel.
In another embodiment, the present invention relates to a method to increase dynamic range of Digital Receiver without varying the Receiver front end gain based on return strength, the method comprising: splitting an analog intermediate frequency signal into a high level intermediate frequency and a low level intermediate frequency with a gain difference of 36dB, where the high level intermediate frequency is allowed to pass through a coarse ADC and the low level intermediate frequency is allowed to pass through a fine ADC, selecting between coarse and fine ADC output based on the return strength of coarse ADC and feeding the selected data to ADC combiner where data is converted into 22bit format based on whether coarse ADC or Fine ADC data is selected.
Figure 3 shows a state diagram of ADC Combiner according to one embodiment of the present invention.
The figure shows the state diagram of ADC Combiner, where the ADC Combiner chooses either Coarse IF signal or Fine IF signal depending on the IF signal strength. The selection logic is based on the value of Coarse ADC. If any of the 6 MSBs (leaving Sign bit) of this coarse ADC is non-zero (indicating a strong signal) then the coarse ADC value is chosen and 6 zeros are appended at the Least Significant end. If on the other hand all the 6 MSB bits of the coarse ADC are zeros (indicating a weak signal) then the Fine ADC value is chosen and 6 zeros are appended to the Most Significant end by retaining the Sign bit (to compensate 36dB gain provided in receiver front end in Fine channel). The strength of the signal is determined using previous 5 samples (based on sampling point decision cannot be taken on single samples). If any one of the previous 5 samples was chosen to be from a coarse ADC, then the current sample is also chosen from the coarse ADC. The 22 bit data from ADC combiner is piped to Mixer [4] block. This block separates the incoming digitized data into its In-phase and Quadrature phase components. This is achieved by multiplying each incoming signal by SINE and COSINE signals of frequency equal to IF frequency generated locally inside FPGA using NCO [5].This works on the (simplified) mathematical principle:
Frequency (Sin) * Frequency (SNCO) = Frequency (Sin-SNCO) +Frequency (Sin+ SNCO).
where Sin is the input signal (output from ADC Combiner [3]) and SNCO is NCO generated signal (output from NCO [5]).The Mixer [4] essentially shifts the IF data to base band. The output from Mixer [4] is passed through a Linear Phase FIR Filter [6] to filter out the out of interest band signals(i.e. Sin + SNCO
signal).The FIR Filter [6] is configurable (using control word command from Radar Controller) whose coefficients (pre-loaded in the memory of FPGA) are selected based on the mode of operation of RADAR. The number of filter taps is equal to the no of samples in the selected pulse width of RADAR. This allows us to design a filter which effectively carries out a block multiplication. The filter length (number of taps), center frequency, and bandwidth are all adjustable. The design procedure computes two sets of filter coefficients f1and fq such that the instantaneous quadrature samples at given bins are:

where N is the length of the filter. The input samples S (output from Mixer [4]) are centered on the range bin to which the (I, Q) pair is assigned. This module gives an output of 32 bits. The output from FIR Filter [6] is passed through Decimator [7] which decimates the signal by factor equal to decimation factor. The decimation factor is again configurable and selected based on mode of operation of Radar to match the output data rate equal to bandwidth of transmitted pulse. The output from Decimator [7] is fed to DPRAM [8] module which controls the read and writes operations of the DPRAM for proper transfer of data from Digital Receiver to DSP using VME.
Figure 4 shows a simulation plot of input and output signal according to one embodiment of the present invention.
The figure shows the screenshot of input and output signal of Digital Receiver (simulated in MATLAB) in time and frequency domain along with dynamic range linearity plot. The input to Digital Receiver is 30MHz (centre frequency) with 1KHz doppler sampled at 40MHz. The simulated signal frequency is linearly varying from 27.5MHz to 32.5MHz for a pulse width of 12us. As Seen in FIG. 4 the Inphase and Quadrature phase component of output signal of Digital Receiver contains only band of interest signal (Base band signal).
Figure 5 shows a linearity plot of input and output signal power according to one embodiment of the present invention.
The figure shows a linearity plot of input and output signal power of Digital Receiver (simulated in MATLAB) over the dynamic range. The input signal power varies from +12dBm to -108dBm and as seen in FIG. 5 the output signal is constant between +12dBm to +10dBm due to ADC front end saturation and it is almost not changing below-100dBm due to noise. Hence Digital Receiver responds linearly (with an accuracy of 0.5dB) from +10dBm to -100dBm, providing 110dB dynamic range.
Thus, as described the present invention improves the dynamic range of digital Receiver greater than 110dB, without using any analog automatic gain control circuitry, while at the same time restoring the signal to substantially its original condition for highly reliable signal detection. The present invention with improved dynamic range of Digital Receivers may be used in RADARs and also can be utilized to similar requirements.
Those skilled in this technology can make various alterations and modifications without departing from the scope and spirit of the invention. Therefore, the scope of the invention shall be defined and protected by the following claims and their equivalents.
Figs. 1-5 are merely representational and are not drawn to scale. Certain portions thereof may be exaggerated, while others may be minimized. Figs. 1-5 illustrate various embodiments of the invention that can be understood and appropriately carried out by those of ordinary skill in the art.
In the foregoing detailed description of embodiments of the invention, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description of embodiments of the invention, with each claim standing on its own as a separate embodiment.
It is understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined in the appended claims. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively.

We Claim:
1. An ultra-wide dynamic range digital receiver, the receiver comprising:
at least one coarse analog to digital convertor and at least one fine analog to digital convertor to receive analog intermediate frequency as a input and convert the received analog intermediate frequency in to 16 bit digital signal at sampling frequency, wherein the coarse ADC receives high level intermediate frequency and the fine ADC receives low level intermediate frequency;
a field programmable gate array (FPGA) coupled to coarse and fine ADC to receive the digitally converted intermediate frequency at sampling rate and implementing architecture of ADC Combiner, Mixer, NCO, Linear phase FIR Filter, Decimator and DPRAM to improve the dynamic range of receiver;
a control and data section device coupled to FPGA which translates the external control signals into FPGA compatible signals and FPGA output data into external device compatible signals;
a regulators section comprising of DC-DC converter and LDOs coupled to FPGA, wherein the regulators section generates the required voltage level for operation of FPGA, ADCs and other ICs of the board;
a plurality of reference clocks signals sections coupled to the FPGA, where the sections are required for generation of sampling clock, other clocks and reference signals required for the Digital Receiver; and
a controller coupled to the FPGA to transfer data from digital receiver to Digital Signal Processor and from radar Controller to the digital receiver.
2. The digital receiver as claimed in claim 1, wherein the coarse ADC receives IF signal from IF receiver with no gain and fine ADC receives IF signal with a gain of 36dB, where the output of the two ADCs (16 bit) is combined to
generate 22 bits in ADC Combiner based on value of Coarse ADC data.
3. The digital receiver as claimed in claim 1, wherein the separation between coarse and fine channel is changed to any value from 24-42dB (in step of 6dB) based on tradeoff between operating near to noise floor and smooth transition from Coarse to Fine channel.
4. The digital receiver as claimed in claim 1, wherein the ADC Combiner selects either Coarse IF signal or Fine IF signal based on the IF signal strength, where any of the 6 MSBs (leaving Sign bit) of the coarse ADC is non-zero (indicating a strong signal), then the coarse ADC value is chosen and 6 zeros are appended at the Least Significant end, and
if all the 6 MSB bits of the coarse ADC are zeros (indicating a weak signal) then the Fine ADC value is chosen and 6 zeros are appended to the Most Significant end by retaining the Sign bit (to compensate 36dB gain provided in receiver front end in Fine channel).
5. The digital receiver as claimed in claim 1, wherein the ADC Combiner in FPGA combines the Coarse and Fine ADC 16 bit data to 22 bit data based on value of Coarse ADC data.
6. The digital receiver as claimed in claim 1, wherein the strength of the signal is determined using previous 5 samples.
7. The digital receiver as claimed in claim 1, wherein the 22 bit data from ADC combiner is piped to the Mixer block, where this block separates the incoming digitized data into its In-phase and Quadrature phase components.
8. The digital receiver as claimed in claim 1, wherein the output from Mixer is passed through a Linear Phase FIR filter to filter out the out of interest band signals (i.e. Sin + SNCO signal).
9. The digital receiver as claimed in claim 1, wherein the output from FIR Filter is passed through decimator which decimates the signal by factor equal to decimation factor, where the decimation factor is again configurable and selected based on mode of operation of Radar to match the output data rate equal to bandwidth of transmitted pulse.
10. The digital receiver as claimed in claim 1, wherein the output from Decimator is fed to DPRAM module which controls the read and writes operations of the DPRAM for proper transfer of data from Digital Receiver to DSP using VME or Ethernet interface.
11. A method to increase dynamic range of Digital Receiver without varying the Receiver front end gain based on return strength, the method comprising:
splitting an analog intermediate frequency signal into a high level intermediate frequency and a low level intermediate frequency with a gain difference of 36dB, where the high level intermediate frequency is allowed to pass through a coarse ADC and the low level intermediate frequency is allowed to pass through a fine ADC;
selecting between coarse and fine ADC output based on the return strength of coarse ADC; and
feeding the selected data to ADC combiner where data is converted into 22bit format based on whether coarse ADC or Fine ADC data is selected.

Abstract
The present invention mainly relates to digital receiver and more particularly to an ultra-wide dynamic range digital receiver. In one embodiment, the receiver comprising: at least one coarse analog to digital convertor and at least one fine analog to digital convertor to receive analog intermediate frequency as a input and convert the received analog intermediate frequency in to 16 bit digital signal at sampling frequency, wherein the coarse ADC receives high level intermediate frequency and the fine ADC receives low level intermediate frequency, a field programmable gate array (FPGA) coupled to coarse and fine ADC to receive the digitally converted intermediate frequency at sampling rate and implementing architecture of ADC Combiner, Mixer, NCO, Linear phase FIR Filter, Decimator and DPRAM to improve the dynamic range of receiver, a control and data section device coupled to FPGA which translates the external control signals into FPGA compatible signals and FPGA output data into external device compatible signals, a regulators section comprising of DC-DC converter and LDOs coupled to FPGA, wherein the regulators section generates the required voltage level for operation of FPGA, ADCs and other ICs of the board, a plurality of reference clocks signals sections coupled to the FPGA, where the sections are required for generation of sampling clock, other clocks and reference signals required for the Digital Receiver and a controller coupled to the FPGA to transfer data from digital receiver to Digital Signal Processor and from radar Controller to the digital receiver.
Figure 2 (for publication)