Abstract: AN UNDER-SAMPLING APPARATUS FOR ENHANCEMENT IN IF BANDWIDTH OF DIGITAL RECEIVER The present invention relates to a method and an apparatus for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver using under sampling technique. The apparatus comprises a local oscillator (402) that down converts an input electromagnetic signal to an IF signal and the down converted input signal is transmitted to a band pass filter (404). Further, a power divider (410) splits the input signal into two or more signals, wherein one signal is delayed with respect to the other signal by a fixed delay. Further, the split two or more signals are transmitted to two or more analog to digital converters (406a, 406b) for digital conversion of said signals. Further, one of the analog to digital converters (406a, 406b) samples the two or more signals at two or more different sampling rates and said sampled signals are transmitted to two or more FFT blocks (408a, 408b), wherein said sampled signals are Fourier transformed for obtaining frequency bin and phase information. Further, the obtained information is mapped to the look up tables to identify the true frequency without ambiguity. Refer Figure 4A.
DESC:FORM 2
THE PATENTS ACT, 1970
(39 OF 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[SEE SECTION 10, RULE 13]
AN UNDER-SAMPLING APPARATUS FOR ENHANCEMENT IN IF BANDWIDTH OF DIGITAL RECEIVER
BHARAT ELECTRONICS LIMITED
OUTER RING ROAD, NAGAVARA, BANGALORE 560045, KARNATAKA, INDIA
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
TECHNICAL FIELD
The invention is related to an apparatus for frequency measurement using under sampling technique. It helps in enhancing the instantaneous bandwidth of the digital receiver beyond the analog to digital (A/D) converter sample rate in a digital receiver. It also solves the ambiguities in present day under sampling techniques thus provides more unambiguous instantaneous bandwidth.
BACKGROUND
The present invention relates generally to a digital frequency measurement receiver with bandwidth improvement through multiple sampling along with delay line technique for unambiguous measurement.
Traditionally, discrete spectra can be used to measure frequencies of sinusoidal signal components. Such a measurement consists in digitizing a compound signal, performing windowing of the signal samples and computing their discrete magnitude spectrum, usually by means of the FFT algorithm. Frequencies of individual components can be evaluated from their respective locations in the discrete spectrum with a resolution depending on the number of samples.
The basic architecture of a system for measuring frequency by using FFT is shown in Fig. 1A. The input frequency FIN is down converted using a local oscillator to Intermediate Frequency (IF) range that is compatible to the sampling frequency (Fs) and analog to digital converter (ADC) then filtered using a band pass filter to allow only frequencies of required bandwidth. Further, the signal is sampled at a rate Fs and is converted into digital samples using an ADC. These digitized samples are processed using FFT block for frequency measurement. As per Nyquist Shannon theorem, the sampling rate (Fs) must be at least twice the bandwidth of the input signal to avoid aliasing. If the frequency at the input of ADC is more than Fs/2 aliasing happens in the frequency domain thus limiting IF bandwidth to Fs/2. The effect of aliasing is illustrated in the Fig. 1B. Hence, this method provides a limitation on the IF (Intermediate Frequency) bandwidth.
To achieve wide instantaneous bandwidth, sophisticated high sampling rate A/D converters are required which increase system cost. In many receivers, the low pass/ band pass filter preceding the A/D converter limits the signal bandwidth to one half the sample frequency (Fs/2) or less. This eliminates any aliased signals but also limits the receiver bandwidth to no more than Fs/2 in case real sampling and Fs in case of complex sampling. Band folded digital receivers open this bandwidth up and use signal processing techniques to estimate the true frequency of the aliased signals. Band folded digital receiver take advantage of the fact that the input response bandwidth of many A/D converters is many times the sample bandwidth and therefore the corner frequency of the low pass/ band pass filter preceding the A/D can be extended up to the response bandwidth of the A/D converter rather than be limited to the sampling frequency (Fs). The A/D converter response bandwidth is a function of the input sample and hold circuit therein. As an opinion, an external sample and hold component can be provided to further increase their response bandwidth of a given A/D converter. With this as base, we can enhance the instantaneous bandwidth and use under sampling concepts to measure unambiguous frequency.
The following United States patents are of interest. U.S. Pat. No. 5,109,188 is the previous art related to the field of invention, which presents an apparatus for extending the frequency range of digital receiver. In this invention the input channel is divided into two sub channels where one channel is delayed with respect to other channel and are sampled at same clock rate as shown in Fig. 2, this technique overcomes the limitations of conventional digital receivers by providing amplitude as well as phase information for measuring frequencies of much wider input bandwidths than would otherwise be possible. Here as the frequency information is same in both the channels, the magnitude response of FFT’s are identical but the phase response will be varied due to change in the length travelled by the wave in the delayed channel with respect to other channel. For a fixed delay d, the variation in phase (?) is dependent only on frequency (f) as explained by equation,
?=2pdf/c
Where ‘c’ is the velocity of electromagnetic wave, which is a constant.
For resolving the ambiguity using this phase information we should have a look up table having the phase response for different frequencies. By correlating the phase difference obtained from FFTs and the phase information from the lookup table, we can identify the sub-band and thus the frequency precisely. Here the IF bandwidth is increased to a large extent, but this algorithm also has some drawback as mentioned below:
Ambiguities at multiples of sampling frequency.
If more than one frequency falls in the same bin at same instance it is difficult to measure both frequencies without missing.
U.S. Pat. No. 7,482,967 presents an apparatus similar to Fig. 3A for characterizing an input signal within a broad frequency band by comparing the same input signal in a plurality of channels, in order to operate digital Electronic Support Measures (ESM) which requires a broad bandwidth to function. The apparatus comprises one or more signal input bands spread across the broad frequency band, a means of splitting the input signal in each input band into a plurality of separate channels, and a means of sampling each channel, wherein the sampling rate in each channel runs at a different clock rate from sampling rate in each of the other channels within the input bands, so as to remove the ambiguities inherent in frequency aliasing. This invention doesn’t address the ambiguities at crossover points of the folding pattern as shown in Fig. 3B, each of the ambiguities corresponds to set of two or more input frequencies, as it cannot differentiate between these two or more frequencies when occur simultaneously.
Further, there are various conventional techniques for extracting frequency parameters of the IF signal using digital receivers without addressing the ambiguities. The ambiguities are not resolved due the limitations in the techniques. Hence, there is still a need of a better or an alternative invention which will solve the above defined problems.
SUMMARY
This summary is provided to introduce concepts related to digital frequency measurement receiver. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
For example, various embodiments herein may include one or more a method and an apparatus for resolving the ambiguities and enhancing the IF bandwidth of an under sampled digital receiver is provided. The method comprises of having a pre-calculated ambiguity points in a lookup table in order to identify the presence of ambiguity in real time processing. Further, in presence of ambiguity, a process is provided to change over from multiple sampling technique to delay line technique. Further, the method involves using of two lookup tables, one for the frequency bin mapping and other for the phase difference between channels for measurement of input frequency. This is achieved by using a single pole, double throw (SPDT) switch in the path of sampling clock in one of the channels to create an apparatus from the above-mentioned method. This apparatus works as multiple sampling techniques when no ambiguity is present and changes over to delay line technique when an ambiguity is detected.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
Figure 1A is a block diagram showing the basic model of frequency measurement in the prior art, according to an exemplary implementation of the present invention.
Figure 1B illustrates the folding pattern of an under-sampled signal in the prior art, according to an exemplary implementation of the present invention.
Figure 2 is a block diagram showing the architecture of delay line technique in the prior art, according to an exemplary implementation of the present invention.
Figure 3A is a block diagram showing the architecture of multiple sampling technique in the prior art, according to an exemplary implementation of the present invention.
Figure 3B graphically illustrates the frequency bin mapping of multiple sampling technique with Fs1= 1000MHz and Fs2 = 1200MHz in the prior art, according to an exemplary implementation of the present invention.
Figure 4A is a block diagram illustrating a method to enhance the unambiguous IF bandwidth of a wideband receiver, according to an exemplary implementation of the present invention.
Figure 4B graphically illustrates the frequency bin mapping of the present disclosure with Fs1 = 1000MHz and Fs2 = 1024MHz, according to an exemplary implementation of the present invention.
Figure 4C graphically illustrates the phase difference between the two channels with one channel being 2.25cms delayed, according to an exemplary implementation of the present invention.
Figure 5A graphically illustrates the mapping of entire 2-18GHz band to IF bandwidth of 2-6 GHz, according to an exemplary implementation of the present invention.
Figure 5B is a block diagram representing the present invention with an extension to ultrawide band, according to an exemplary implementation of the present invention.
Figure 6 illustrates a flowchart of a method for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver, according to an exemplary implementation of the present invention.
It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present invention. Similarly, it will be appreciated that any flowcharts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
DETAILED DESCRIPTION
In the following description, for the purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
The various embodiments of the present invention provides method and apparatus for bandwidth improvement in a digital frequency measurement receiver through multiple sampling along with delay line technique for unambiguous measurement.
Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
References in the present invention to “one embodiment” or “an embodiment” mean that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
The present invention relates to a method and an apparatus for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver through multiple sampling along with delay line technique for unambiguous measurement. In one of the implementations, a method for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver is provided wherein two channels are sampled at two different sampling rates wherein one of the channels is delayed. These two sampling rates are denoted by Fs1, Fs2 and the delay introduced is denoted by d. The Single Pole Double Throw (SPDT) switch is used to change the clock from Fs1 to Fs2 or vice versa whenever it is required. The method further comprises down converting an input signal RFIN to the IF range using a local oscillator which is then passed through a band pass filter having a required bandwidth. The input signal is split into two channels by a power divider where one channel is delayed with respect to other channel by a fixed length. This delay can also be incorporated in the clock Fs1. The split signals are given to analog to digital converters (ADCs) for digital conversion which are sampled at a sampling frequency Fs1 and Fs2 respectively. The digitized samples obtained from these ADCs are given to the respective FFT blocks. Here both the sampled signals are Fourier transformed for obtaining amplitude information. By using two sampling frequencies, the aliased signals uniquely map into the sample bandwidth up to a maximum unambiguous frequency given by equation,
F_unambiguous=(F_s1*F_s2)/GCF
Where, GCF is a greatest common factor of the sample frequencies.
Here ambiguities at cross over frequencies which are explained using FIG. 3B and FIG. 4B can be overcome using three lookup tables. The first lookup table ‘A’ is generated from peak frequency bin information of two or more channels for each input frequency which forms a unique set for entire bandwidth except at cross over frequencies or ambiguous frequencies when sampled at different clocks. The second lookup table ‘B’ contains the set of frequency bin numbers at crossover frequencies or ambiguous frequencies to identify the presence of ambiguity and the third lookup table is generated from frequency bin along with phase information of two or more channels when sampled at the same clock only at ambiguous frequencies to resolve the ambiguity. All the three lookup tables are to be generated as a part of calibration of apparatus so that the manufacture errors in delay of delay line and minor sampling clock offset errors can be taken care of. Initially this apparatus works as a multiple sampling technique with sampling frequencies as Fs1 for channel 1 and Fs2 for channel 2 and measures the frequencies bin pair set and mapping it to lookup table ‘A’, if obtained frequency bin pair is not detected in lookup table ‘B’ and changes over to delay line technique with sampling frequency as Fs1 in both the channels when the obtained frequency bin pair is detected in lookup table ‘B’. Lookup table ‘B’ is an ambiguity table that gives information about all ambiguity points in the entire operating bandwidth. When an ambiguity is detected by the processor, a control is sent to SPDT switch for changing over the sampling frequency of the ADC of channel 2 from Fs2 to Fs1. Further, the FFT blocks measure phase information along with frequency bin information to measure the frequency corresponding to the ambiguity point. The phase variation with fixed delay between the channels is illustrated in a plot between phase differences to frequency. This change over remains for a brief period until the ambiguity is resolved.
In another implementation, the apparatus can further be extended to increase the band width to 2-18GHz by dividing the entire band into four sub-bands and down converting to Intermediate Frequency between 2-6GHz using respective local oscillators.
Fig. 1A is a block diagram showing the basic model of frequency measurement in the prior art, according to a prior art in the present technical domain. The basic architecture of a system for measuring frequency by using FFT is shown in this figure. The input frequency Fin is down converted using a Local Oscillator (LO) to IF range that is compatible to the sampling frequency and Analog to Digital Converter (ADC) then filtered using a Band Pass Filter (BPF) to allow only required frequencies. Further, the signal is sampled at a rate Fs and is converted into digital samples using an ADC. These digitized samples are processed using the FFT block for frequency measurement.
FIG. 1B illustrates the folding pattern of an under-sampled signal in the prior art, according to a prior art in the present technical domain. In this figure, the effect of aliasing is illustrated. As per the Nyquist Shannon theorem the sampling rate (Fs) must be at least twice the bandwidth of the input signal to avoid aliasing. If the frequency at the input of ADC is more than Fs/2 aliasing happens in the frequency domain thus limiting the IF bandwidth to Fs/2.
FIG. 2 is a block diagram showing the architecture of delay line technique in the prior art, according to a prior art in the present technical domain. This figure discloses an apparatus for extending the frequency range of digital receiver. Here, the input channel is divided into two sub channels wherein one channel is delayed with respect to the other channel and both the channels are sampled at a similar clock rate as shown in the figure. This technique overcomes the limitations of conventional digital receivers by providing amplitude as well as frequency information for much wider input bandwidths than would otherwise be possible.
FIG. 3A is a block diagram showing the architecture of multiple sampling technique in the prior art, according to a prior art in the present technical domain. This figure discloses an apparatus for characterizing an input signal within a broad frequency band by comparing the same input signal in a plurality of channels, in order to operate digital Electronic Support Measures (ESM) which requires a broad bandwidth to function. This apparatus comprises one or more signal input bands that are spread across the broad frequency band, a means of splitting the input signal in each input band into a plurality of separate channels, and a means of sampling each channel, wherein the sampling rate in each channel runs at a different clock rate from sampling rate in each of the other channels within the input bands, so as to remove the ambiguities inherent in frequency aliasing.
FIG. 3B graphically illustrates the frequency bin mapping of multiple sampling technique with Fs1= 1000MHz and Fs2 = 1200MHz in the prior art, according to the prior art in the present technical domain. This figure shows the ambiguities at crossover points of the folding pattern wherein each of the ambiguities corresponds to the set of two input frequencies, as it cannot differentiate between these two frequencies when they occur simultaneously.
FIG. 4A is a block diagram illustrating a method to enhance the unambiguous IF bandwidth of a wideband receiver, according to an exemplary implementation of the invention as disclosed in the present technical disclosure. This architecture provides usage of two channels that are sampled at two different sampling rates wherein input frequency of one of the channels may be delayed. These two sampling rates are denoted by Fs1, Fs2 and the delay introduced is denoted by d. The Single Pole Double Throw (SPDT) switch may be used to change the clock from Fs1 to Fs2 or vice versa when there is a requirement. Further, the input signal RFin is down converted to the IF range using a Local Oscillator (LO) 402 which may be then passed through a Band Pass Filter (BPF) 404 having the required bandwidth. Further, a power divider 410 splits the input signal into two channels wherein one channel may be delayed with respect to the other channel by a fixed length. This delay may also be incorporated in the clock Fs1. The split signals are given to the ADCs (406a, 406b) for digital conversion which are sampled at a sampling frequency Fs1 and Fs2 respectively. The digitized samples obtained from these ADCs (406a, 406b) are given to the respective FFT blocks (408a, 408b). Here both the sampled signals are Fourier transformed for obtaining amplitude information. By using the two sampling frequencies, the aliased signals are mapped into the sample bandwidth up to a maximum unambiguous frequency given by the equation,
F_unambiguous=(F_s1*F_s2)/GCF
where, GCF is a greatest common factor of the sample frequencies.
FIG. 4B graphically illustrates the frequency bin mapping of the present disclosure with Fs1 = 1000MHz and Fs2 = 1024MHz, according to an exemplary implementation of the invention as disclosed in the present technical disclosure. The cross over points in the points are mapping to two or more frequencies thus forming the ambiguity points. These crossover points are tabulated in the entire operating bandwidth forming lookup table ‘B’.
FIG. 4C graphically illustrates the phase difference between the two channels with one channel being 2.25cms delayed, according to an exemplary implementation of the invention as disclosed in the present technical disclosure. When an ambiguity is detected by the processor, a control is sent to SPDT switch for changing over the sampling frequency of ADC from Fs2 to Fs1. Now the FFT blocks (408a, 408b) measure the phase information along with the amplitude information to measure the frequency corresponding to the ambiguity point. This phase variation with fixed delay between the channels is shown in a plot between the phase differences to the frequency in this figure. This change remains for a brief time until the ambiguity is resolved.
FIG. 5A graphically illustrates the mapping of entire 2-18GHz band to IF bandwidth of 2-6 GHz, according to an exemplary implementation of the invention as disclosed in the present technical disclosure. Here, the bandwidth is further increased to 2-18GHz by dividing the entire band into four sub-bands and down converting to IF (2-6GHz) using respective local oscillators.
FIG. 5B is a block diagram representing the present invention with an extension to ultra wide band, according to an exemplary implementation of the invention as disclosed in the present technical disclosure. Here, a Local Oscillator (LO1) with 12GHz may be used to convert 6-10GHz band to 2-6GHz band. Similarly for 10-14GHz band, a 8GHz Local Oscillator (LO2) may be used and for 14-18GHz band, a 12 GHz Local Oscillator (LO3) may be used and operated for attaining the wider bandwidth measurement using same digital receiver as shown in the figure. Here, additional circuitry may be required for obtaining the band code of operation to processor to evaluate the frequency information. This additional information may be obtained by comparing the detector outputs at each band to detect the presence of signal in the particular band.
Figure 6 illustrates a flowchart of a method for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver, according to an exemplary implementation of the present invention. The flowchart 600 of Fig. 6 is explained below with reference to Fig. 4A as described above.
At step 602, down converting an input electromagnetic signal to an IF signal by a local oscillator (402). In another embodiment, the local oscillator (402) is configured to down convert an input electromagnetic signal to an IF signal.
At step 604, transmitting the down converted input signal to a band pass filter (404) by the local oscillator (402), wherein the band pass filter (404) allows a required band of frequencies. In another embodiment, the local oscillator (402) is configured to transmit the down converted input signal to a band pass filter (404).
At step 606, splitting the input signal into two or more signals, wherein one signal is delayed with respect to the other signal by a fixed delay by a power divider (410). In another embodiment, the power divider (410) is configured to split the input signal into two or more signals.
At step 608, transmitting the split two or more signals to two or more analog to digital converters (406a, 406b) for digital conversion of said signals by the power divider (410). In another embodiment, the power divider (410) is configured to transmit the split two or more signals to two or more analog to digital converters (406a, 406b) for digital conversion of said signals.
At step 610, sampling said two or more signals at two or more different sampling rates, wherein the two or more sampling rates are denoted by Fs1 and Fs2 by one of the analog to digital converters (406a, 406b). In another embodiment, one of the analog to digital converters (406a, 406b) is configured to sample said two or more signals at two or more different sampling rates.
At step 612, transmitting said sampled signals to two or more FFT blocks (408a, 408b) by the analog to digital converters (406a, 406b). In another embodiment, one of the analog to digital converters (406a, 406b) is configured to transmit said sampled signals to two or more FFT blocks (408a, 408b), wherein said sampled signals are Fourier transformed for obtaining frequency bin and phase information.
At step 614, transmitting the obtained information to ambiguity resolution block 414 by the two or more FFT blocks (408a, 408b). In another embodiment, the FFT blocks (408a, 408b) are configured to transmit said information to frequency resolution block, wherein obtained information is analyzed for detecting presence of ambiguity & measure frequency unambiguously throughout the band of interest.
In an embodiment, a method for resolving the ambiguities and Enhancing the IF bandwidth of under sampled digital receiver is provided. The method includes a pre-calculated ambiguity points in a lookup table in order to identify the presence of ambiguity in real time processing. Further, the method includes a process to change over from multiple sampling technique to delay line technique in the presence of ambiguity. The method further includes using two lookup tables one of frequency bin mapping and other for phase difference between channels for measurement of input frequency.
It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
,CLAIMS:We Claim:
1. A method for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver, said method comprising:
down converting, by a local oscillator (402), an input electromagnetic signal to an IF signal;
transmitting, by the local oscillator (402), the down converted input signal to a band pass filter (404), wherein the band pass filter (404) has a required bandwidth;
splitting, by a power divider (410), the input signal into two or more signals, wherein one signal is delayed with respect to the other signal by a fixed delay;
transmitting, by the power divider (410), the split two or more signals to two or more analog to digital converters (406a, 406b) for digital conversion of said signals;
sampling, by one of the analog to digital converters (406a, 406b), said two or more signals at two or more different sampling rates, wherein the two or more sampling rates are denoted by Fs1 and Fs2; and
transmitting, by the analog to digital converters (406a, 406b), said sampled signals to two or more FFT blocks (408a, 408b).
2. The method as claimed in claim 1, further comprises:
identifying the presence of a plurality of ambiguities in real time processing by using a pre-calculated ambiguity table from the two or more lookup tables, wherein the lookup tables includes frequency information, phase information and the like;
changing from a multiple sampling technique with sampling rates Fs1 and Fs2 to a delay line technique with sampling rate Fs1 in the presence of one of the plurality of ambiguities;
measuring an input frequency corresponding to one of the plurality of ambiguity points by using two or more lookup tables.
3. The method as claimed in claim 2, wherein measuring an input frequency corresponding to one of the plurality of ambiguity points further comprises changing, by a Single Pole Double Throw (SPDT) switch, the sampling rate of the analog to digital converter from Fs2 to Fs1.
4. The method as claimed in claim 2, wherein the lookup tables further comprises:
generating a first lookup table generated from peak frequency bin information of two or more channels for each input frequency which forms a unique set for entire bandwidth except at cross over frequencies or ambiguous frequencies when sampled at different clocks;
generating a second lookup table contains the set of frequency bin numbers at crossover frequencies or ambiguous frequencies for identifying the presence of ambiguity; and
generating a third lookup table from frequency bin along with phase information of two or more channels when sampled at the same clock only at ambiguous frequencies for resolving the ambiguity.
5. The method as claimed in claim 2, wherein the frequency information is used in a folded pattern.
6. The method as claimed in claim 2, wherein transmitting, by the analog to digital converters (406a, 406b), the sampled signals to two or more FFT blocks (408a, 408b) further comprises obtaining amplitude information by Fourier transforming the sampled signals.
7. The method as claimed in claim 2, wherein the pre calculated ambiguity table gives information about the plurality of ambiguity points in the entire operating bandwidth.
8. The method as claimed in claims 2, wherein the plurality of ambiguity points corresponds to one or more input frequencies for differentiating said ambiguity points based on the two or more lookup tables.
9. An apparatus for enhancing an Intermediate Frequency (IF) bandwidth of a digital receiver, said apparatus comprises:
a local oscillator (402) configured to:
down convert an input electromagnetic signal to an IF signal;
transmit the down converted input signal to a band pass filter (404), wherein the band pass filter (404) has a required bandwidth;
a power divider (410) configured to:
split the input signal into two or more signals, wherein one signal is delayed with respect to the other signal by a fixed delay;
transmit the split two or more signals to two or more analog to digital converters (406a, 406b) for digital conversion of said signals;
one of the analog to digital converters (406a, 406b) configured to:
sample said two or more signals at two or more different sampling rates, wherein the two or more sampling rates are denoted by Fs1 and Fs2; and
transmit said sampled signals to two or more FFT blocks (408a, 408b), wherein said sampled signals are Fourier transformed for obtaining amplitude information.
10. The apparatus as claimed in claim 9, said apparatus is further configured to:
identify the presence of a plurality of ambiguities in real time processing by using a pre-calculated ambiguity table from the two or more lookup tables, wherein the lookup tables include frequency information, phase information and the like;
change from a multiple sampling technique with sampling rates Fs1 and Fs2 to a delay line technique with sampling rate Fs1 in the presence of one of the plurality of ambiguities;
measure an input frequency corresponding to one of the plurality of ambiguity points by using two or more lookup tables.
11. The apparatus as claimed in claim 9, said apparatus further comprises a Single Pole Double Throw switch (SPDT) configured to change the sampling rate of the analog to digital converter from Fs2 to Fs1.
12. The apparatus as claimed in claim 10, wherein the lookup tables are further configured to:
generate a first lookup table generated from peak frequency bin information of two or more channels for each input frequency that forms a unique set for entire bandwidth except at cross over frequencies or ambiguous frequencies when sampled at different clocks;
generate a second lookup table that contains the set of frequency bin numbers at crossover frequencies or ambiguous frequencies to identify the presence of ambiguity; and
generate a third lookup table from frequency bin along with phase information of two or more channels when sampled at the same clock only at ambiguous frequencies to resolve the ambiguity.
13. The apparatus as claimed in claim 9, wherein the analog to digital converters (406a, 406b) are further configured to obtain amplitude information by Fourier transforming the sampled signals.
Dated this 15thday of March, 2019
FOR BHARAT ELECTRONICS LIMITED
(By their Agent)
(D. Manoj Kumar) (IN/PA 2110)
KRISHNA & SAURASTRI ASSOCIATES LLP
| # | Name | Date |
|---|---|---|
| 1 | 201941010245-FORM 13 [19-02-2025(online)].pdf | 2025-02-19 |
| 1 | 201941010245-PROVISIONAL SPECIFICATION [15-03-2019(online)].pdf | 2019-03-15 |
| 2 | 201941010245-FORM 1 [15-03-2019(online)].pdf | 2019-03-15 |
| 2 | 201941010245-POA [19-02-2025(online)].pdf | 2025-02-19 |
| 3 | 201941010245-RELEVANT DOCUMENTS [19-02-2025(online)].pdf | 2025-02-19 |
| 3 | 201941010245-DRAWINGS [15-03-2019(online)].pdf | 2019-03-15 |
| 4 | 201941010245-Response to office action [17-12-2022(online)].pdf | 2022-12-17 |
| 4 | 201941010245-FORM-26 [13-06-2019(online)].pdf | 2019-06-13 |
| 5 | Correspondence by Agent _Power Of Attorney_18-06-2019.pdf | 2019-06-18 |
| 5 | 201941010245-ABSTRACT [05-08-2022(online)].pdf | 2022-08-05 |
| 6 | 201941010245-Proof of Right (MANDATORY) [29-08-2019(online)].pdf | 2019-08-29 |
| 6 | 201941010245-CLAIMS [05-08-2022(online)].pdf | 2022-08-05 |
| 7 | Correspondence by Agent_Form-1_06-09-2019.pdf | 2019-09-06 |
| 7 | 201941010245-COMPLETE SPECIFICATION [05-08-2022(online)].pdf | 2022-08-05 |
| 8 | 201941010245-FORM 3 [12-09-2019(online)].pdf | 2019-09-12 |
| 8 | 201941010245-DRAWING [05-08-2022(online)].pdf | 2022-08-05 |
| 9 | 201941010245-ENDORSEMENT BY INVENTORS [12-09-2019(online)].pdf | 2019-09-12 |
| 9 | 201941010245-FER_SER_REPLY [05-08-2022(online)].pdf | 2022-08-05 |
| 10 | 201941010245-DRAWING [12-09-2019(online)].pdf | 2019-09-12 |
| 10 | 201941010245-OTHERS [05-08-2022(online)].pdf | 2022-08-05 |
| 11 | 201941010245-CORRESPONDENCE-OTHERS [12-09-2019(online)].pdf | 2019-09-12 |
| 11 | 201941010245-FER.pdf | 2022-02-08 |
| 12 | 201941010245-COMPLETE SPECIFICATION [12-09-2019(online)].pdf | 2019-09-12 |
| 12 | 201941010245-FORM 18 [10-02-2021(online)].pdf | 2021-02-10 |
| 13 | 201941010245-COMPLETE SPECIFICATION [12-09-2019(online)].pdf | 2019-09-12 |
| 13 | 201941010245-FORM 18 [10-02-2021(online)].pdf | 2021-02-10 |
| 14 | 201941010245-CORRESPONDENCE-OTHERS [12-09-2019(online)].pdf | 2019-09-12 |
| 14 | 201941010245-FER.pdf | 2022-02-08 |
| 15 | 201941010245-DRAWING [12-09-2019(online)].pdf | 2019-09-12 |
| 15 | 201941010245-OTHERS [05-08-2022(online)].pdf | 2022-08-05 |
| 16 | 201941010245-ENDORSEMENT BY INVENTORS [12-09-2019(online)].pdf | 2019-09-12 |
| 16 | 201941010245-FER_SER_REPLY [05-08-2022(online)].pdf | 2022-08-05 |
| 17 | 201941010245-FORM 3 [12-09-2019(online)].pdf | 2019-09-12 |
| 17 | 201941010245-DRAWING [05-08-2022(online)].pdf | 2022-08-05 |
| 18 | Correspondence by Agent_Form-1_06-09-2019.pdf | 2019-09-06 |
| 18 | 201941010245-COMPLETE SPECIFICATION [05-08-2022(online)].pdf | 2022-08-05 |
| 19 | 201941010245-Proof of Right (MANDATORY) [29-08-2019(online)].pdf | 2019-08-29 |
| 19 | 201941010245-CLAIMS [05-08-2022(online)].pdf | 2022-08-05 |
| 20 | Correspondence by Agent _Power Of Attorney_18-06-2019.pdf | 2019-06-18 |
| 20 | 201941010245-ABSTRACT [05-08-2022(online)].pdf | 2022-08-05 |
| 21 | 201941010245-Response to office action [17-12-2022(online)].pdf | 2022-12-17 |
| 21 | 201941010245-FORM-26 [13-06-2019(online)].pdf | 2019-06-13 |
| 22 | 201941010245-RELEVANT DOCUMENTS [19-02-2025(online)].pdf | 2025-02-19 |
| 22 | 201941010245-DRAWINGS [15-03-2019(online)].pdf | 2019-03-15 |
| 23 | 201941010245-POA [19-02-2025(online)].pdf | 2025-02-19 |
| 23 | 201941010245-FORM 1 [15-03-2019(online)].pdf | 2019-03-15 |
| 24 | 201941010245-PROVISIONAL SPECIFICATION [15-03-2019(online)].pdf | 2019-03-15 |
| 24 | 201941010245-FORM 13 [19-02-2025(online)].pdf | 2025-02-19 |
| 1 | 201941010245E_04-02-2022.pdf |