1. An analog-to-digital converter comprising: a first analog-to-digital conversion cell that quantizes a voltage level of an analog signal within a first quantizat ion range at a first quantization step and outputs a first digital value5 ; a second analog-to-digi tal conversion cel l that quantizes the vol tage level of the analog signal within a second input range at a second quantization step and outputs a second digi tal value; control means for, when a mode specifying signal indicates a first mode, 10 generat ing a control signal that sets the first and second input ranges to the same voltage range and sets first and second sampling clocks to different phases, and when the mode specifying signal indicates a second mode, generating the control signal that sets the first and second input ranges to one cont inuous voltage range and sets the first and second sampling clocks to the same phase; 15 ADC cell control means for controlling the voltage ranges of the first and second input ranges according to the control signal; sampl ing clock generation means for supplying the first and second sampl ing clocks to the first and second analog-to-digital conversion cel ls, respectively, according to the control signal; and 20 an output data processing circuit that merges the first and second digi tal values and outputs output data.

2. The analog-to-digi tal converter wherein the ADC cell control means outputs a first maximum reference voltage that sets a maximum value of the first 25 input range, a first minimum reference vol tage that sets a minimum value of the first input range, a second maximum reference voltage that sets a maximum value of the second input range, and a second maximum reference voltage that sets a minimum value of the second input range, and switches voltage values o f the first and second maximum reference voltages and vol tage values of the first and second 30 minimum reference voltages according to the control signal .

3. The analog-to-digi tal converter according to Claim 1 or 2, further comprising a preprocessing circuit that converts an amplitude of the analog signal to be in a voltage range convertable by the first and second analog-to-digital 45 conversion cells and generates an intermediate analog signal.

4. The analog-to-digi tal converter according to Claim 3, wherein the preprocessing circui t outputs a first conversion input signal obtained by level -shifting a signal level of the intermediate analog signal by a first shif5 t amount according to the voltage range of the first input range and a second conversion input signal obtained by level -shifting the signal level of the intermediate analog signal by a second shift amount according to the voltage range of the second input range, outputs the first conversion input signal to the first 10 analog-to-digital conversion cel l, and outputs the second conversion input signal to the second analog-to-digital conversion cell.

5. The analog-to-digi tal converter according to Claim 4, wherein the ADC cell control means varies a size of each of the first and second shift amount s 15 according to the control signal.

6. The analog-to-digi tal converter according to Claim 5, wherein the ADC cell control means changes an amplification factor of the preprocessing circui t according to the control signal. 20

7. The analog-to-digi tal converter according to any one of Claims 1 to 6, wherein when the control signal that is output corresponding to the first mode is input, the output data processing circuit outputs the first digital value and the 25 second digital value as output data, and when the cont rol signal that is output corresponding to the second mode is input , the output data processing circuit outputs data that is obtained by merging the first and second digi tal values according to a conversion table as the output data. 30 8. The analog-to-digi tal converter according to any one of Claims 1 to 7, wherein when the mode specifying signal indicates a third mode, the control means outputs the control signal that sets the first and second input ranges to the same voltage range and places one of the fi rst and second sampling clocks in a dormant state. 46

9. The analog-to-digi tal converter according to any one of Claims 1 to 8, further comprising: an output data analysis uni t that analyzes a size of an error between the digital values output by the first and second analog-to-digital conversion cells an5 d an ideal value; and a calibration signal generation circuit that generates a calibration signal , wherein when the mode specifying signal indicates a fourth mode, the control means 10 outputs the control signal for instructing one of the first and second analog-to-digital conversion cel ls to perform conversion processing on the analog signal and the other one of the first and second analog -to-digital conversion cells to perform conversion processing on the calibration signal, the output data analysis unit generates a correction value for correcting a 15 deviation between a digital value that is obtained by converting the calibrat ion signal from the output data processing unit based on the control signal that is output corresponding to the fourth mode and an ideal value of the digital value and supplies the correction value to the ADC cell control means, the ADC cell control means corrects at least one of the voltage ranges of 20 the first and second input voltages and an input offset voltage of the analog-to-digital conversion cel l based on the correction value.

10. The analog-to-digital converter according to any one of Claims 1 to 9, wherein when the first and second input ranges are set based on the control si gnal 25 that is output corresponding to the second mode, the ADC cell control means sets the first and second input ranges so that the first input range and the second input range will have an overlapped range where a part of the first input range and a part of the second input range will be the same voltage range, and further, a step boundary value of the first quantizat ion step and a step boundary value of the 30 second quantization step will be different values.

11. The analog-to-digital converter according to any one of Claims 1 to 10, wherein a step width of the first quant ization step and a step width of the second quantization step are set different values. 47

12. The analog-to-digital converter according to any one of Claims 1 to 11, wherein the first quantization step and the second quantization step are different .

13. The analog-to-digital converter according to any one of Claims 1 to 125 , wherein the sampling clock generat ion unit selects whether to output clocks having different phases from among a multiple-phase clock as the first and second sampl ing clocks or to output one clock selected from the multi -phase clock as the first and second sampling clocks. 10

14. The analog-to-digital converter according to Claim 13, wherein when the clocks having different phases from among the mult i -phase clock are output as the first and second sampling clocks, the sampling clock generation unit selects clocks which will be the first and second sampling clocks from the multi -phase 15 clock so that an interval between a f irst sampling timing, which is a sampl ing timing of the first analog-to-digital conversion cell , and a second sampling timing, which is a sampling t iming of the second analog-to-digital conversion cell , wi ll be different from an interval between the second sampl ing timing and the first sampl ing timing. 20

15. The analog-to-digital converter according to any one of Claims 1 to 14, further comprising: a third analog-to-digi tal conversion cell that quantizes a voltage level of the analog signal within a third input range at a third quantization step and outputs 25 a third digital value; and a fourth analog-to-digi tal conversion cel l that quantizes a voltage level of the analog signal within a fourth input range at a fourth quantization step and outputs a fourth digital value, wherein the sampling clock generation unit further outputs third and fourth 30 sampl ing clocks which will be suppl ied to the third and fourth analog -to-digital conversion cells, respectively, and the control means, when the mode specifying s ignal indicates the first mode, outputs the control signal that sets the first to fourth input ranges to the same voltage 48 range, and further, sets the first to fourth sampling clocks to different phases, when the mode specifying signal indicates the second mode, outputs the control signal that sets the first to fourth input ranges to one cont inuous voltage range, and further, sets the first to fourth sampl ing clocks to the same phase, an5 d when the mode specifying signal indicates a fifth mode, outputs the control signal that sets the first and second input ranges to one continuous vol tage range, sets the third and fourth input voltages to one continuous voltage range, sets a first sampling clock group including the first and second sampling clocks havin g 10 the same phase and a second sampling clock group including the third and fourth sampl ing clocks having another same phase to different phases.

16. The analog-to-digital converter according to any one of Claims 1 to 15, further comprising: 15 a conversion cell array that is composed of a plurality of analog -to-digital conversion cells having a function equivalent to that of the first and second analog-to-digital conversion cel ls, wherein the control means outputs the control signal that instructs any one of the plurality of analog-to-digital conversion cel ls to perform an operat ion 20 corresponding to the first and second modes.

17. A method for analog-to-digital conversion, the method comprising steps of: a method for analog-to-digital conversion quantizing a voltage level of an analog signal within a first input range at a 25 first quantization step and outputting a first digital value; quantizing the voltage level of the analog signal within a second input range at a second quantization step and outputtin g a second digi tal value; when a mode specifying signal indicates a first mode, using a first analog-to-digital conversion cel l having a first input range and a second 30 analog-to-digital conversion cel l having a second input voltage, sett ing the first and second input ranges to the same voltage range, quant izing the voltage level of the analog signal , and outputt ing the first digital value and the second digital value at different sampling timings ; when the mode specifying signal indicates a second mode, using the first 49 analog-to-digital conversion cel l and the second analog-to-digital conversion cell, setting the first and second input ranges to one cont inuous voltage range, and output ting the first digi tal value and the second digital value at the same sampling timing; and merging the first and second digital values and output ting output data.

ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL
CONVERSION METHOD
Technical Field
[00015 ]
The present invention relates to an analog-to-digital converter and an
analog-to-digital conversion method for converting an input analog signal into a
digital signal.
10 Background Art
[0002]
The analog-to-digital converter (hereinafter referred to as an ADC as
appropriate) is used in various fields. The required conversion speed and
quantization bit rate of the ADC differ from system to system to which the ADC is
15 appl ied. For example, in the ADC used for a communication purpose, as a signal
band and a required SNR (Signal to Noise Ratio) differ depending on the
communicat ion scheme, the conversion speed and quantization bit rate required for
the ADC also differ from communication scheme to communicat ion scheme. Note
that if the input range stays the same, the greater the quantization bit rate, the
20 higher the conversion accuracy (SNR) of the ADC. That is, the conversion
accuracy of the ADC is an index that depends on the size of the quantization bit
width.
[0003]
Here, Fig. 34 shows an example of a relat ionship between the conversion
25 speed and conversion accuracy required for the ADC. Fig. 34 shows a
relationship between signal bands of three modulatio n schemes, which are BPSK
(Binary Phase-Shift Keying), QPSK (Quaternary Phase-Shift Keying), and 16PSK
(16 Phase-Shift Keying), and SNRs that are required for the respective
communicat ion schemes. In BPSK, the required signal band is wide but the
30 required SNR can be low. Therefore, an ADC with a high conversion speed and a
low SNR is used for BPSK. Meanwhile, in 16PSK, the required signal band is
narrow but the required SNR is high. Therefore, an ADC capable of achieving a
high SNR is used for 16PSK even if a conversion speed thereof is low. Similarly,
in QPSK, an ADC with a conversion speed between the conversion speeds required
3
for BPSK and 16PSK and an SNR between the SNRs required for BPSK and 16PSK
is used. As stated above, the performance required for the ADC differs from
modulation scheme to modulation scheme. Thus, systems have heretofore been
built using ADCs dedicated for the respect ive modulat ion schemes.
[00045 ]
However, there has been a problem that the development cost and capital
investment increase when different systems are used for different modulat ion
schemes. In order to solve this problem, it is necessary to realize a highly
flexible system that supports a plurality of requirement specifications. However,
10 in order to realize a highly flexible system using a known ADC with a fixed
conversion speed and conversion accuracy, an ADC with performance realizing a
high conversion speed and high conversion accuracy at the same time is necessary.
However, i t is extremely difficult to realiz e such a high-speed and highly accurate
ADC for a communication purpose in which the speed has been further accelerated
15 in recent years. Even if such an ADC can be realized, the accuracy and the speed
may be excessively or unnecessar ily high for a certain modulat ion scheme, thereby
leading to a problem of inefficiency and larger power consumption.
[0005]
As a way to solve this problem, related art has already been suggested such
20 as that disclosed in Patent Literature 1. The ADC of Patent Literature 1 uses a
plurality of basic ADCs having the same performance. The ADC of Patent
Li terature 1 includes a time-interleaved configuration that operates the plurality of
basic ADCs at different timings in the time -axis direction to thereby improve an
apparent conversion speed. Moreover, the ADC of Patent Literature 1 includes an
25 output average configuration that operates the plurality of basic ADCs at the same
timing and averages outputs thereof to thereby reduce a random noise component
other than quantization noise and improve the conversion accuracy. Further, the
ADC of Patent Literature 1 arbitrarily combines the time -interleaved configuration
and the output average configuration and flexibly switches the conversion speed
30 and the conversion accuracy. However, the ADC of Patent Literature 1 uses
averaging processing as a way to improve the conversion accuracy. Accordingly,
even if the random noise component can be reduced, the quantization noise cannot
be eliminated. It is therefore not possible to so improve the conversion accuracy
that a quantization bi t rate greater than or equal to the quant izat ion bi t rate of the
4
basic ADC is achieved.
[0006]
Meanwhile, as a simi lar approach, a related technique disclosed in Patent
Li terature 2 is a method for realizing an ADC having a quantization bit rate greater
than or equal to the quant ization bit rate of the basic ADC. In the ADC disclose5 d
in Patent Li terature 2, a plurality of basic ADCs are used to vary or shift a
reference voltage that determines the quantization threshold of the ADC, thereby
realizing an ADC having the quantization bit rate greater than or equal to the
quantization bit rate of the basic ADCs. The configuration that realizes the ADC
10 having the quant ization bit rate greater than or equal to the q uantization bit rate of
the basic ADCs by varying or shifting the reference voltage that determines the
quantization threshold of the ADC in a manner explained above shall be
hereinafter referred to as an ampl itude -interleaved configuration. However, the
amplitude-interleaved configuration disclosed in Patent Literature 2 only improves
15 the accuracy in the amplitude direction, while it is unable to achieve a conversion
speed greater than or equal to the basic ADCs.
Citation List
Patent Literature
20 [0007]
Patent Literature 1: Japanese Unexamined Patent Application Publication No.
2011-009960
Patent Literature 2 Japanese Unexamined Patent Application Publication No.
2009-267808
25
Summary of Invention
Technical Problem
[0008]
As explained above, there is a problem in Patent Literatures 1 and 2 that
30 only one of a high conversion speed and high conversion accuracy is realized, and
the two of them cannot be achieved at the same time. It may be considered
possible to realize a high conversion speed and high conversion accuracy by
combining the t ime-interleaved configurat ion of Patent Literature 1 and the
amplitude-interleaved configuration of Patent Literature 2. However, a problem
5
is that an ADC with a combination of those configurat ions has an excessive
performance for the capacity required for conversion processing, and the power
consumpt ion thus becomes excessively large. For example, in performing the
conversion processing on a signal of the 16PSK communication scheme shown in
Fig. 34, a high conversion speed is unnecessary, and thus a difference between 5 a
conversion cycle necessary for the conversion processing and an actual conversion
cycle wi ll be conversion processing not actually required, thereby consuming
excessive power. Moreover, in performing the conversion processing on a signal
of the BPSK communication scheme shown in Fig. 34, high conversion accuracy is
10 unnecessary, and thus ADCs corresponding to a difference between the number of
ADCs (quantization bit rate) necessary for the conversion processing and the
number of ADCs used in the actual conversion processing will be conversion
processing not actual ly required, thereby consuming excessive power.
[0009]
15 In light of the above problem, an object of the present invention is to
realize an analog-to-digital converter that supports conversion processing of
signals in more communication schemes while suppressing power consumption.
Solution to Problem
20 [0010]
An exemplary aspect of the present invention is an analog-to-digi tal
converter that includes: a first analog-to-digital conversion cell that quantizes a
voltage level of an analog signal within a first quantization range at a first
quantization step and outputs a first digital value; a second analog-to-digital
25 conversion cell that quant izes the voltage level of the analog signal within a
second input range at a second quantization step and outputs a second di gital
value; control means for, when a mode specifying signal indicates a first mode,
generat ing a control signal that sets the first and second input ranges to the same
voltage range and sets first and second sampling clocks to different phases, and
30 when the mode specifying signal indicates a second mode, generating the control
signal that sets the first and second input ranges to one cont inuous voltage range
and sets the first and second sampling clocks to the same phase; ADC cell control
means for controlling the voltage ranges of the first and second input ranges
according to the control signal ; sampling clock generation means for supplying the
6
first and second sampling clocks to the first and second analog -to-digital
conversion cells, respectively, according to the control signal; and an output data
processing circuit that merges the first and second digital values and outputs
output data.
Another exemplary aspect of the present invention is a method fo5 r
analog-to-digital conversion, the method comprising steps of: quant izing a voltage
level of an analog signal within a first input range at a first quantization step and
output ting a first digi tal value; quantizing the voltage level of the analog signal
within a second input range at a second quantization step and outputting a second
10 digital value; when a mode specifying signal indicates a first mode, using a first
analog-to-digital conversion cel l having a first input range and a second
analog-to-digital conversion cel l having a second input range, setting the first and
second input ranges to the same voltage range, quantizing the voltage level of the
analog signal, and outputting the first digi tal value and the second digital value at
15 different sampling timings; when the mode specifying signal indicates a second
mode, using the first analog-to-digital conversion cel l and the second
analog-to-digital conversion cel l, setting the first and second input ranges to one
cont inuous voltage range, and outputting the first digital value and the second
digital value at the same sampling timing; and merging the first and second digi tal
20 values and outputting output data.
Advantageous Effects of Invention
[0011]
The analog-to-digital converter and the analog-to-digital conversion
25 method according to the present invention provide an analog-to-digi tal converter
that supports conversion processing of signals in more communication schemes
while suppressing the power consumption.
Brief Description of Drawings
30 [0012]
Fig. 1 is a block diagram of an analog-to-digital converter according to a
first exemplary embodiment;
Fig. 2 is a diagram showing an example of a configuration table of the
analog-to-digital converter according to the first exemplary embodiment;
7
Fig. 3 is a t iming chart showing an operation in a first mode of the
analog-to-digital converter according to the first exemplary embodiment;
Fig. 4 is a t iming chart showing an operation in a second mo de of the
analog-to-digital converter according to the first exemplary embodiment;
Fig. 5 is a graph showing a relationship between a signal band an5 d
conversion accuracy handled by the analog-to-digital converter according to the
first exemplary embodiment;
Fig. 6 is a block diagram of an analog-to-digital converter according to a
second exemplary embodiment;
10 Fig. 7 is a diagram showing an example of a configuration table of an
analog-to-digital converter according to the second exemplary embodiment ;
Fig. 8 is a t iming chart showing an operation in a first mode of the
analog-to-digital converter according to the second exemplary embodiment ;
Fig. 9 is a t iming chart showing an operation in a second mode of the
15 analog-to-digital converter according to the second exemplary embodiment ;
Fig. 10 is a timing chart showing an operat ion in a fifth mode of the
analog-to-digital converter according to the second exemplary embodiment ;
Fig. 11 is a graph showing a relationship between a signal band and
conversion accuracy handled by the analog-to-digital converter according to the
20 second exemplary embodiment;
Fig. 12 is a block diagram of an analog-to-digital converter according to a
third exemplary embodiment;
Fig. 13 is a block diagram of a preprocessing circuit of the
analog-to-digital converter according to the third exemplary embodiment;
25 Fig. 14 is a diagram showing an example of a configuration table of the
analog-to-digital converter according to the third exemplary embodiment;
Fig. 15 is a timing chart showing an operat ion in a first mode of the
analog-to-digital converter according to the third exemplary embodiment;
Fig. 16 is a timing chart showing an operat ion in a second mode of the
30 analog-to-digital converter according to the third exemplary embodiment;
Fig. 17 is a timing chart showing an operat ion of the preprocessing circuit
in the second mode of the analog-to-digital converter according to the third
exemplary embodiment;
Fig. 18 is a diagram showing an example of assigning input ranges in the
8
second mode of the analog-to-digital converter according to the third exemplary
embodiment;
Fig. 19 is a block diagram of a preprocessing circuit of an analog-to-digital
converter according to a fourth exemplary embodiment;
Fig. 20 is a block diagram of a preprocessing circuit of an analog-to-digita5 l
converter according to a fifth exemplary embodiment ;
Fig. 21 is a diagram showing an example of a configuration table of the
analog-to-digital converter according to the fifth exemplary embodiment;
Fig. 22 is a timing chart showing an operat ion of the analog-to-digital
10 converter according to the fifth exemplary embodiment corresponding to the
configuration table shown in Fig. 21;
Fig. 23 is a diagram showing another example of the configuration table of
the analog-to-digi tal converter according to the fifth exemplary embodiment ;
Fig. 24 is a timing chart showing an operat ion of the analog-to-digital
15 converter according to the fifth exemplary embodiment corresponding to the
configuration table shown in Fig. 23;
Fig. 25 is a diagram showing a modified example of the configuration table
of the analog-to-digital converter according to the present invention;
Fig. 26 is a schematic diagram of input ranges realized by a first modified
20 example shown in Fig. 25;
Fig. 27 is a schematic diagram of input ranges realized by a second
modified example shown in Fig. 25;
Fig. 28 is a schematic diagram of input ranges realized by a third modified
example shown in Fig. 25;
25 Fig. 29 is a schematic diagram of input ranges reali zed by a fourth modified
example shown in Fig. 25;
Fig. 30 is a schematic diagram of input ranges realized by a fifth modified
example shown in Fig. 25;
Fig. 31 is a diagram showing an example of a configuration table
30 corresponding to an operat ion mode that performs conversion processing at
unequal sampling timings;
Fig. 32 is a timing chart showing an operat ion of an analog-to-digital
converter of the present invention corresponding to the configurat ion table shown
in Fig. 31;
9
Fig. 33 is a timing chart showing an operat ion of an analog-to-digital
converter of the present invention that performs conversion processing with
unequal degrees of conversion accuracy; and
Fig. 34 is a graph showing a relationship between a conversion speed and
conversion accuracy required for an analog-to-digital converter5 .
Description of Embodiments
[0013]
Firstly, the terms used in this specification shall be defined. Generally,
10 the term "resolution" is used as an index to indicate the performance of an ADC.
The term "resolution" may indicate the number of stages of a digi tal value obtained
by resolving an analog input voltage, i .e., the number of bits of a digital value
obtained by converting an analog input voltage, or may indicate a range of analog
input voltages which will be converted into the same digital value, i.e., an analog
15 voltage width that can be resolved. In this specification, as it is necessary to
distinguish between the resolution having the former meaning and the resolution
having the latter meaning, the resolution having the former meaning shall be
referred to as "the number of quantization steps", and the resolution having the
latter meaning shall be referred to as a "quant ization step voltage". For example,
20 in the case of a normal two-bit ADC that has a range of an analog input voltage of
3 V and performs linear conversion, the number of quant ization steps will be four,
and the quantizat ion step vol tage will be 1 V. Note that the "quant ization step
voltage" does not necessarily need to be constant thro ugh the entire analog input
voltage range.
25 [0014]
Further, in general , an input voltage range of an ADC is smaller than a
voltage difference between a power supply voltage VDD which will be supplied to
the ADC and a ground voltage GND. However in the present invention, in order
to simplify the explanation, a maximum value of the input voltage range of an ADC
30 shall be the power supply voltage VDD, and a minimum value thereof shall be the
ground voltage GND.
[0015]
First exemplary embodiment
Hereinafter, exemplary embodiments of the present invention shall be
10
explained with reference to the drawings. Fig. 1 is a block diagram of an entire
analog-to-digital converter 1 of the present invention. As shown in Fig. 1, the
analog-to-digital converter 1 according to the first exemplary embodiment includes
analog-to-digital conversion cells (hereinafter referred to as ADC cells) 11 and 12,
a circuit configuration control unit 110, an ADC cell control uni t 111, a samplin5 g
clock generation unit 112, and an output data processing circuit 113.
[0016]
Note that the first exemplary embodiment explains an example in which the
analog-to-digital converter 1 has, as operation modes, a first mode for performing
10 high-speed and low accuracy conversion processing and a second mode for
performing low-speed and high accuracy conversion processing. Moreover, in the
following explanation, conversion accuracy indicates the size of the quantization
step vol tage. That is, a small quantization step voltage is a state of high
conversion accuracy, whereas a large quant ization step voltage is a state of low
15 conversion accuracy. Further, in the following explanation, a conversion speed
indicates the level of a sampling frequency of the ADC cell.
[0017]
The ADC cell 11 is a block corresponding to a first analog-to-digi tal
conversion cell. The ADC cel l 11 quantizes a voltage level of an analog signal
20 within a first input range at a first quantization step and outputs a first digi tal
value. The ADC cel l 12 is a block corresponding to a second analog-to-digital
conversion cell. The ADC cel l 12 quantizes a voltage level of an analog signal
within a second input range in a second quantization step and outputs a second
digital value. Note that as for the analog-to-digital converter 1 according to the
25 first exemplary embodiment, an example in which the ADC cell 11 and the ADC
cell 12 have the same number of quantization steps is described.
[0018]
In response to a mode specifying signal MD, the circuit configurat ion
control unit 110 supplies control signals CNT0, CNT1, and CNT2 to the sampling
30 clock generation unit 112, the ADC cell control unit 111, and the output data
processing circuit 113, respectively. The control signals CNT0, CNT1, and CNT2
specify an input voltage range and a sampling t iming of the ADC cells 11 and 12,
respectively, for the respective sampling clock generation unit 112 and the ADC
cell control uni t 111. Moreover, the control signal CNT2 specifies a processing
11
method of conversion results by the ADC cells 11 and 12 for the output data
processing circuit 113.
[0019]
Associations between the control signals CNT0, CNT1, and CNT2 and the
mode specifying signal MD may be defined in, for example, a configurat ion tabl5 e
or the like that is included in the circuit configuration c ontrol unit 110. Then,
information in the configuration table may be selected according to the mode
specifying signal MD, and the control signals CNT0, CNT1, and CNT2 may be
output .
10 [0020]
The ADC cell control unit 111 controls vol tage ranges of the firs t and
second input ranges. More specifically, the ADC cell control unit 111 outputs a
first maximum reference voltage REF11+ that sets a maximum value of the input
range of the ADC cel l 11 (e.g. , the first input range), a minimum reference vol tage
15 REF11- that sets a minimum value of the first input voltage, a second maximum
reference voltage REF12+ that sets a maximum value of the input range of the
ADC cell 12 (e.g., the second input range), and a minimum reference voltage
REF12- that sets a minimum value of the second input voltage. Then, the ADC
cell control uni t 111 switches the vol tage values of the first and second maximum
20 reference voltages and the first and second minimum reference voltages according
to the control signal CNT0 output by the circuit configurat ion control unit 110.
Note that in the following explanation, the first maximum reference vol tage shall
be referred to as the maximum reference voltage REF11+, the second maximum
reference voltage shall be referred to as the maximum reference voltage REF12+,
25 the first minimum reference voltage shall be referred to as the minimum reference
voltage REF11-, and the second minimum reference voltage shall be referred to as
the minimum reference vol tage REF12-.
[0021]
The sampling clock generation unit 112 supplies a first sampling clock
30 CLK11 and a second sampl ing clock CLK12 respectively to the ADC cells 11 and
12 according to the control signal CNT1. The ADC cel l 11 performs sampling
processing in synchronization with, for example, a rising edge o f the supplied
sampl ing clock.
[0022]
12
The output data processing circuit 113 generates output data using output
values output from the plurality of ADC cells. To be more specific, when the
mode specifying signal MD indicates a first mode, the control signal CNT2 that is
output according to the first mode is input to the output data processing circuit
113. When the control signal CNT2 corresponding to the first mode is input, th5 e
output data processing circuit 113 outputs a first digital value output by the ADC
cell 11 and a second digi tal value output by the ADC cell 12 as output data.
Note that the first digi tal value and the second digital value correspond to input
voltages sampled at different t imings.
10 [0023]
Meanwhile, when the mode specifying signal MD indicates the second
mode, the control signal CNT2 that is output according to the second mode is input
to the output data processing circui t 113. When the control signal CNT2
corresponding to the second mode is input , the output data processing cir cuit 113
15 converts the first digi tal value output by the ADC cel l 11 and the second digital
value output by the ADC cell 12 in accordance with a predetermined rule and
outputs the converted values as the output data.
[0024]
An association between the first digital value and the second digi tal value
20 and the output data may be defined in a conversion table or the like in advance.
Then, the first digital value and the second digital value may be merged according
to the definition in the conversion table, and the merged value may be output as the
output data.
[0025]
25 Here, details of the configurat ion definition table shall be explained. In
the analog-to-digi tal converter 1 according to the first exemplary embodiment ,
when the mode specifying signal MD indicat es the first mode, high-speed and low
accuracy conversion processing is performed, whereas when the mode specifying
signal indicates the second mode, low-speed and high accuracy conversion
30 processing is performed. Thus, in the analog-to-digital converter 1 according to
the first exemplary embodiment , two circuit configuration values are included in
the configuration definition table. The circuit configuration values here are
reflected to the control signal s CNT0, CNT1, and CNT2 and input to the sampling
clock generation unit 112, the conversion range control unit 111, and the output
13
data processing circuit 113. Fig. 2 shows an example of the configuration
definition table according to the first exemplary embodiment .
[0026]
As shown in Fig. 2, the configurat ion definition table according to the first
exemplary embodiment holds values set in the manner shown below as the circui5 t
configuration values when the mode specifying signal MD indicates the first mode
(e.g. , when the value of the mode specifying signal MD is 0). That is, the
maximum reference voltages VREF11+ and VREF12+ are both set to the power
supply voltage VDD, and the minimum reference voltages REF11 - and REF12- are
10 both set to the ground voltage GND. A phase sett ing value of the first samplin g
clock CLK11 is set to 0deg, and a phase set ting value of the second sampling clock
CLK12 is set to -180deg. In conversion to the output data, the configuration table
has a value that selects an output conversion table THR for defining the first and
second digital values to be output as they are.
15 [0027]
Moreover, as shown in Fig. 2, the configuration definition table according
to the first exemplary embodiment holds values set in the manner shown below as
the circuit configurat ion values when the mode specifying signal MD indicates the
second mode (e.g., when the value of the mode specifying signal MD is 1). That
20 is, the maximum reference voltage VREF11+ is set to the power supply voltage,
the minimum reference vol tage VREF11- and the maximum reference voltage
VREF12+ are both set to half of the power supply voltage (VDD/2), and the
minimum reference voltage REF12- is set to the ground vol tage GND. The phase
setting values of the first sampl ing clock CLK11 and the second sampling clock
25 CLK12 are set to 0deg. In conversion to the output data, the configurat ion table
has a value that selects an output conversion table MRG1 for defining the first and
second digital values to be merged and output.
[0028]
That is, when the mode specifying signal MD indicates the first mode, the
30 circuit configuration control unit 110 according to the first exemplary embodiment
outputs the circuit configuration values that set the first and second input ranges to
the same voltage range and the first sampl ing clock CLK11 and the second
sampl ing clock CLK12 to different phases. Meanwhile, when the mode
specifying signal MD indicates the second mode, the circuit configuration control
14
unit 110 outputs the circuit configuration values that set the first and second input
ranges to one continuous vol tage range and the first sampling clock CLK11 and the
second sampling clock CLK12 to the same phase.
[0029]
Next, an operat ion of the analog-to-digital converter 1 according to th5 e
first exemplary embodiment shall be explained. Fig. 3 is a timing chart showing
an operation in the first mode of the analog-to-digital converter 1. As shown in
Fig. 3, in the first mode of the analog-to-digital converter 1, the ADC cel l 11 and
the ADC cell 12 perform a sampling operation alternately. Moreover, the input
10 ranges of the ADC cell 11 and the ADC cel l 12 have the same voltage range.
Thus, in the analog-to-digital converter 1 according to the first exemplary
embodiment, the conversion processing can be performed at twice the conversion
speed that can be achieved by one ADC cell. That is, in the first mode, the
analog-to-digital converter 1 realizes an improvement in the conversion speed by
15 the time-interleaved configuration composed of the ADC cel ls 11 and 12.
[0030]
Moreover, Fig. 4 is a timing chart showing an operation in the second mode
of the analog-to-digital converter 1. As shown in Fig. 4, in the second mode of
the analog-to-digi tal converter 1, the ADC cells 11 and ADC cell 12 perform the
20 conversion processing at the same sampling t imings. Next, the input range of the
ADC cell 11 and the input range of the ADC cell 12 are joined to achieve one input
range. Accordingly, the analog-to-digital converter 1 can realize
analog-to-digital conversion with conversion accuracy which is twice that of one
ADC cell, i.e., with a quantization step vol tage which is half of that of one ADC
25 cell. That is, in the second mode, the analog-to-digital converter 1 improves the
conversion accuracy by the amplitude -interleaved configuration composed of the
ADC cells 11 and 12.
[0031]
Fig. 5 is a graph showing a relationship between a communicat ion scheme
30 that can be supported by the first mode shown in Fig. 3 and a communication
scheme that can be supported by the second mode shown in Fig. 4. The
analog-to-digital converter 1 according to the first exemplary embodiment
supports a high conversion speed by the time -interleaved configuration composed
of the ADC cells 11 and 12 in the first mode. However, in the first mode, only
15
one ADC cell operates in one sampl ing operation, and the conversion accuracy is
thus low. By such an operat ion, the analog-to-digital converter 1 operating in the
first mode can support a first communication scheme that requires a wide signal
band and low conversion accuracy shown in Fig. 5.
[00325 ]
Moreover, the analog-to-digital converter 1 according to the first
exemplary embodiment supports high conversion accuracy by the
amplitude-interleaved configuration composed of the ADC cells 11 and 12 in the
second mode. However, in the second mode, the sampling speed is limited to the
10 conversion speed of one ADC cell, and the conversion speed is thus low. By such
an operation, the analog-to-digital converter 1 operating in the second mode can
support a second communication scheme that requires a narrow signal band and
high conversion accuracy shown in Fig. 5.
[0033]
15 As described above, in the analog-to-digital converter 1 according to the
first exemplary embodiment, the ADC cell control unit 111 switches the input
ranges of the ADC cells 11 and 12 based on the circuit configuration values
selected by the circui t configuration control uni t 110 according to the mode
specifying signal MD, and the sampling clock generation unit 112 switches the
20 sampl ing timings of the ADC cells 11 and 12. Accordingly, the analog-to-digital
converter 1 according to the first exemplary embodiment can support two
communicat ion schemes that require different performance , which are the first
communicat ion scheme that requires high-speed and low accuracy conversion
processing and the second communication scheme that requires low-speed and high
25 accuracy conversion processing.
[0034]
Here, the analog-to-digital converter 1 according to the first exemplary
embodiment performs, by only the ADC cells 11 and 12, the conversion processing
for the two communication schemes that require different performance s. In other
30 words, in the analog-to-digital converter 1 according to the first exemplary
embodiment, there is no ADC cell that is not used for the conversion processing
while ei ther of the two communication schemes that require differen t performances
is being processed. Thus, the analog-to-digital converter 1 according to the first
exemplary embodiment wil l not supply power to a circuit that does not operate in
16
the conversion processing of either of the communicat ion schemes. That is, by
using the analog-to-digital converter 1 according to the first exemplary
embodiment, it is possible to reduce the power consumption whi le supporting a
plurality of communication schemes that require different performances.
[00355 ]
Further, in the analog-to-digital converter 1 according to the first
exemplary embodiment, there is no circuit that does not operate while signals in
either of the communication schemes are being input. The usage efficiency of the
circuits is thus high, and the size of the circuit can be reduced more than the size
10 of the analog-to-digital converter that is configured using a related technique and
supports a plurality of communicat ion schemes can be reduced.
[0036]
Second exemplary embodiment
Fig. 6 is a block diagram of an analog-to-digital converter 2 according to a
15 second exemplary embodiment . As shown in Fig. 6, an analog-to-digital
converter 2 according to the second exemplary embodiment increases the number
of ADC cells in the analog-to-digital converter 1 according to the first exemplary
embodiment to three or more. In the example shown in Fig. 6, n (n is an integer
indicating the number of ADC cells) ADC cells are shown.
20 [0037]
In the analog-to-digital converter 2 according to the second exemplary
embodiment, it is possible to support more communication schemes than are
supported by the analog-to-digital converter 1 according to the first exemplary
embodiment by including more ADC cells than are in the analog-to-digital
25 converter 1. Therefore, in the second exemplary embodiment , a configurat ion
table that defines usage of the ADC cel ls 11 to 1n shall be explained in detai l.
Note that basic functions of the blocks in the analog-to-digital converter 2
according to the second exemplary embodiment are the same as those explained in
the first exemplary embodiment . Thus, a detailed explanation of said functions
30 shall be omitted in the second exemplary embodiment .
[0038]
Fig. 7 shows an example of the configuration table used by the
analog-to-digital converter 2 according to the second exemplary embodiment . In
the example shown in Fig. 7, the number of ADC cells is four. That is, the
17
example shown in Fig. 7 corresponds to the case in which the analog-to-digital
converter 2 includes the ADC cell 11 (e.g. , the first analog-to-digital conversion
cell), the ADC cell 12 (e.g., the second analog-to-digital conversion cel l), an ADC
cell 13 (e.g. , a third analog-to-digital conversion cell), and an ADC cell 14 (e.g., a
fourth analog-to-digi tal conversion cell). Note that the third analog-to-digita5 l
conversion cell quant izes a voltage level of an analog signal within a third input
range at a third quant ization step and outputs a third digital value. The fourth
analog-to-digital conversion cel l quantizes a voltage level of an analog signal
within a fourth input range at a fourth quantization step and outputs a fourth
10 digital value.
[0039]
Moreover, in the analog-to-digital converter 2 corresponding to the
example shown in Fig. 7, the sampling clock generation unit 112 outputs a third
sampl ing clock CLK13 and a fourth sampl ing clock CLK14 which will be supplied
15 to the third and fourth analog-to-digital conversion cells, respectively.
[0040]
In the example shown in Fig. 7, cir cuit configuration values related to three
operation modes are defined. When the value of the mode specifying signal MD
is 00, the circuit configuration control unit 110 outputs the circuit configuration
20 values corresponding to a first operation mode. When the value of the mode
specifying signal MD is 01, the circuit configuration control uni t 110 outputs the
circuit configuration values corresponding to a second operation mode. When the
value of the mode specifying signal MD is 10, the circuit configura tion control
unit 110 outputs the circuit configuration values corresponding to a third operation
25 mode.
[0041]
The circuit configuration values corresponding to the first mode specify
maximum reference voltages and minimum reference voltages so that the i nput
ranges of the ADC cells 11 to 14 wil l be the same voltage, specify the first
30 sampl ing clock CLK11 to the fourth sampling clock CLK14 having phases
different by 90deg, and specify a value that selects the output conversion table
THR for outputting the first and second digi tal values as they are as an output
pattern. That is, in the analog-to-digi tal converter 2 corresponding to the
example shown in Fig. 7, in the first mode, the first to fourth input ranges are set
18
to the same voltage range, and furthe r, the first to fourth sampling clocks CLK11
to CLK14 are set to different phases.
[0042]
The circuit configuration values corresponding to the second mode specify
maximum reference voltages and minimum reference voltages so that the inpu5 t
ranges of the ADC cells 11 to 14 wil l be one continuous input range, specify the
first sampl ing clock CLK1 to the fourth sampling clock CLK14 having the same
phase, and specify a value that selects the output conversion table MRG1 that
merges and outputs the first and se cond digi tal values as an output pattern. That
10 is, in the analog-to-digi tal converter 2 corresponding to the example shown in Fig.
7, in the second mode, the first to fourth input ranges are set to one cont inuous
voltage range, and the first to fourth sampling clocks CLK11 to CLK14 are set to
the same phase.
[0043]
15 The circuit configuration values corresponding to the fifth mode specify
the maximum reference vol tages and the minimum reference vol tages so that the
input ranges of the ADC cells 11 and 12 wi ll be the same continuous input range
and the input ranges of the ADC cells 13 and 14 will be the same cont inuous input
range. As for the sampling clocks, a first sampling clock group including the
20 first and second sampling clocks having the same phase an d a second sampling
clock group including the third and fourth sampling clocks having another same
phase are specified. As for conversion to output data, an output conversion table
MRG2 that merges and outputs the first digi tal value and the second digita l value
and merges and outputs the third digital value and the fourth digi tal value is
25 specified. That is, in the fifth mode of the analog-to-digital converter 2
corresponding to the example shown in Fig. 7, the first and second input ranges
and the third and fourth input ranges are set as cont inuous common voltage ranges,
respectively. Thus, the phases of the first sampling clock group including the
first and second sampling clocks CLK11 and CLK12 having the same phase are
30 different from the second sampl ing clock group including the third and fourth
sampl ing clocks CLK13 and CLK14 having another same phase.
[0044]
Now operations in the first to fifth modes of the analog-to-digi tal converter
2 according to the second exemplary embodiment shall be explaine d in more detail .
19
Fig. 8 is a t iming chart showing an operation in the first mode of the
analog-to-digital converter 2 according to the second exemplary embodiment. As
shown in Fig. 8, in the analog-to-digital converter 2 operating in the first mode,
the ADC cel ls 11 to 14 sequentially perform a sampling operat ion. Moreover, the
input ranges of the ADC cells 11 to 14 have the same vol tage range. Accordingly5 ,
the analog-to-digi tal converter 2 according to the second exemplary embodiment
can perform the conversion processing at a conversion speed four times higher
than that which can be achieved by one ADC cell . That is, in the first mode, the
analog-to-digital converter 1 realizes an improvement in the conversion speed by
10 the time-interleaved configuration composed of the ADC cel ls 11 to 14.
[0045]
Fig. 9 is a t iming chart showing an operation in the second mode of the
analog-to-digital converter 2 according to the second exemplary embodiment. As
shown in Fig. 9, in the second mode, in the analog-to-digital converter 2, the ADC
15 cells 11 to 14 perform the conversion processing at the same sampling timings.
Then, the input ranges of the ADC cell s 11 to 14 are joined to achieve one input
range. Hence, the analog-to-digital converter 2 can realize four times the
conversion accuracy of one ADC cell . That is, the analog-to-digital converter 2
realizes improvement in the conversion accuracy by the ampli tude -interleaved
20 configuration composed of the ADC cel ls 11 to 14 in the second mode.
[0046]
Fig. 10 is a t iming chart showing an operat ion in the fifth mode of the
analog-to-digital converter 2 according to the second exemplary embodiment. As
shown in Fig. 10, in the fifth mode of the analog-to-digital converter 2, a first
25 ADC cell group composed of the ADC cel l 11 and the ADC cell 12 and a second
ADC cell group composed of the ADC cel l 13 and the ADC cell 14 perform a
sampl ing operation al ternately. Then, the input ranges of the first ADC cell
group are set to one continuous input range, and the input range s of the second
ADC cell group are set to one continuous input range. Accordingly, the
30 analog-to-digital converter 2 realizes conversion accuracy that is twice that of one
ADC cell (an intermediate conversion accuracy that is higher than that in the first
mode and lower than that in the second mode) and realizes an intermediate
conversion speed that is lower than that in the first mode and higher than that in
the second mode. That is, in the fifth mode, the analog-to-digi tal converter 2
20
realizes an improvement in the conversion speed and the conversion accuracy by a
combination of the time-interleaved configuration and the amplitude -interleaved
configuration composed of the ADC cel ls 11 to 14.
[0047]
Fig. 11 is a graph showing a relationship between a communicat ion schem5 e
that can be supported by the first mode shown in Fig. 8, a communication scheme
that can be supported by the second mode shown in Fig. 9, and a communication
scheme that can be supported by the fifth mode shown in Fig. 10. The
analog-to-digital converter 2 according to the second exemplary embodiment
10 supports a high conversion speed by the sequent ial sampling operat ions using the
ADC cells 11 to 14 in the first mode. However, in the first mode, only one ADC
cell operates in one sampling operation, thus the conversion accuracy of the first
mode is the lowest among the three modes. By such an operation, the
analog-to-digital converter 2 operating in the first mode can support the first
15 communicat ion scheme that requires a wide signal band and low conversion
accuracy shown in Fig. 11.
[0048]
Moreover, in the second mode of the analog-to-digital converter 2
according to the second exemplary embodiment , one continuous input range is
20 formed by the input ranges of the ADC cel ls 11 to 14, and further, the ADC cells 11
to 14 perform the sampling operation at the same time, thereby supporting high
conversion accuracy. However, in the second mode, the sampl ing speed is limited
to the conversion speed of one ADC cell, and thus the conversion speed of the
second mode is the lowest among the three modes. By such an operation, the
25 analog-to-digital converter 2 operating in the second mode can support the second
communicat ion scheme that requires a narrow signal band and high conversion
accuracy shown in Fig. 11.
[0049]
Moreover, in the fifth mode of the analog-to-digital converter 2 according
30 to the second exemplary embodiment, the input ranges of the first ADC cell group
and the second ADC cell group are respect ively formed as one continuous input
ranges, and further, the first ADC cell group and the second ADC cell group
perform the sampling operation alternately, thereby supporting the intermediate
conversion accuracy and the intermediate conversion speed. By such an
21
operation, the analog-to-digital converter 2 operat ing in the fifth mode can support
the third communicat ion scheme that requires an intermediate signal band and
intermediate conversion accuracy shown in Fig. 11.
[0050]
As explained above, in the analog-to-digital converter 2 according to th5 e
second exemplary embodiment , the ADC cell control unit 11 switches the input
ranges of the ADC cells 11 to 1n based on the circuit configurat ion values selected
by the circuit configurat ion control unit 110 according to the mode specifying
signal MD, and the sampling clock generation unit 112 switches the sampl ing
10 timings of the ADC cells 11 to 1n. At this time, as the analog-to-digital converter
2 according to the second exemplary embodiment includes more ADC cel ls than
are in the analog-to-digital converter 1 according to the first exemplary
embodiment, the analog-to-digital converter 2 can real ize more combinations of
the ADC cells than are realized by the analog-to-digital converter 1. With more
15 combinations of the ADC cells, the analog-to-digital converter 2 can support more
communicat ion schemes than are supported by the analog-to-digital converter 1.
[0051]
Here, the analog-to-digital converter 2 according to the second exemplary
embodiment realizes a performance conforming to characteristics of signals used
20 in the respective communication schemes by rearranging the input ranges and
sampl ing timings of the ADC cell s 11 to 1n. In other words, in the
analog-to-digital converter 2 according to the second exemplary embodiment, there
is no ADC cell that is not used for the conversion processing while any of the
plurality of communication schemes that require different performance s is being
25 processed. Thus, the analog-to-digital converter 2 according to the second
exemplary embodiment wil l not suppl y power to a circuit that does not operate in
the conversion processing of any of the communicat ion schemes. That is, by
using the analog-to-digital converter 2 according to the second exemplary
embodiment, it is possible to reduce the power consumption whi le supporting a
30 plurality of communication schemes that require different performance s.
[0052]
Furthermore, in the analog-to-digital converter 2 according to the second
exemplary embodiment, there is no circuit that does not operate while signals in
any of the communication schemes are being input. The usage efficiency of the
22
circuits is thus high, and the size of the circuit can be reduced more than the size
of the analog-to-digital converter that is configured using a related technique and
supports a plurality of communicat ion schemes can be reduced.
[0053]
Third exemplary embodimen5 t
Fig. 12 is a block diagram of an analog-to-digital converter 3 according to
a third exemplary embodiment . As shown in Fig. 12, the analog-to-digital
converter 3 further includes, in addition to the circuits in the analog-to-digital
converter 2 according to the second exemplary embodiment , preprocessing circui ts
10 11p to 1np. Moreover, the analog-to-digi tal converter 3 supplies maximum
reference voltages and minimum reference voltages, which are the same voltages
respectively, to the ADC cells 11 to 1n. Therefore, in Fig. 12, a maximum
reference voltage REF+ and a minimum reference vol tage REF- are supplied to all
of the ADC cells 11 to 1n. Thus, as a variation range of an analog signal which
15 will be input to the analog-to-digital converter 3, a range larger than the input
voltage ranges of the respective ADC cells 11 to 1n, that is, a range larger than a
range between the maximum reference voltage REF+ and the minimum ref erence
voltage REF- can be supported. The method shall be explained below.
[0054]
20 The preprocessing circuits 11p to 1np convert amplitudes of analog signals
to be in the voltage range convertable by first to nth analog -to-digital conversion
cells and output the analog signals as intermediate analog signals. For example,
when the number of the ADC cells is two, the preprocessing circuit 11p generates a
first signal for conversion PreOUT1 that is obtained by level -shifting a signal level
25 of the intermediate analog signal by a first shift amount corresponding to the
voltage range of the first input range, and the preprocessing circuit 12p generates a
second signal for conversion PreOUT2 that is obtained by level -shifting a signal
level of the intermediate analog signal by a second shift amount corresponding to
the voltage range of the second input range. Then, the preprocessing circui t 11p
30 outputs the first signal for conversion to the ADC cell 11, and the preprocessing
circuit 12p outputs the second signal for conversion to the ADC cell 12. In this
case, as the signals for conversion PreOUT1 to n which wil l be input to the first to
nth analog-to-digital conversion cells are obtained by level -shifting the original
analog voltages, there is no change in the amplitude. Accordingly, it might be
23
possible to input a voltage outside the convertable range t to the respect ive
analog-to-digital conversion cel ls. Processing in the case when a vol tage outside
the convertable range is input to the analog-to-digital conversion cel l shall be
explained later.
[00555 ]
Note that , in the analog-to-digital converter 3 shown in Fig. 12, n
preprocessing circui ts are shown corresponding to the number of ADC cells for
ease of explanation. However, the preprocessing circui t may be provided as one
circuit block. In this case, the preprocessing circuit amplifies or attenuates the
10 amplitudes of the analog signals to be in the voltage range convertable by the first
to nth analog-to-digital conversion cells , to thereby generate the intermediate
analog signals and level -shift the signal levels of the intermediate analog signals
to generate the signals for conversion PreOUT1 to PreOUTn. Then, the
preprocessing circui t supplies the plurality of the signals for conversion PreOUT1
15 to PreOUTn to the ADC cells, respectively.
[0056]
As the preprocessing circuits 11p to 1np have the same circuit
configuration, a detai led explanation of only the preprocessing circuit 11p is given
as an example. Fig. 13 is a block diagram of the preprocessing circuit 11p. As
20 shown in Fig. 13, the preprocessing circuit 11p includes a variable gain ampl ifier
120 and a variable level -shift circuit 121. Note that if only the level -shifting will
be performed without amplitude adjustment, the variable gain amplifier 120 may
be removed.
[0057]
25 The variable gain amplifier 120 determines the size of an amplification
factor according to a value of an ampli tude control signal AC11. Then, the
variable gain amplifier 120 ampl ifies an analog signal according to the determin ed
amplifier and generates an intermediate analog signal MOUT. Note that the
amplification factor of the variable gain amplifier 120 is set so that a maximum
30 amplitude of the intermediate analog signal MOUT will be in a voltage range
convertable by a plurality of ADC cells at one sampling timing.
[0058]
The variable level -shift circuit 121 level -shifts a signal level of the
intermediate analog signal MOUT according to a value of a DC bias control signal
24
SFT11 and generates the first signal for conversion PreOUT1.
[0059]
Moreover, in the analog-to-digital converter 3 according to the third
exemplary embodiment, the circuit configuration values of the configuration table
of the circuit configurat ion control unit 110 include a value specifying the value o5 f
the amplitude control signal AC11 and a value specifying the value of the DC bias
control signal SFT11. Fig. 14 shows an example of the configuration table used
by the analog-to-digi tal converter 3 according to the third exemplary embodiment.
[0060]
10 In the example shown in Fig. 14, the number of ADC cells is four.
Moreover, the example shown in Fig. 14 is the case in which the analog-to-digital
converter 3 has the first mode and the second mode. The first mode shown in Fig.
14 (when the value of the mode specifying signal MD is 0) is for performing an
operation the same as that performed by the first mode of the analog-to-digital
15 converter 2 according to the second exemplary embodiment . In the example
shown in Fig. 14, 0dB is defined as a circuit configuration value corresponding to
the amplitude control signals AC11 to AC14 in the first mode, and 0V is defined as
a circuit configuration value corresponding to the DC bias control signals SFT11
to SFT14.
20 [0061]
The second mode shown in Fig. 14 (when the value of the mode specifying
signal MD is 1) is for performing an operat ion the same as that performed by the
second mode of the analog-to-digital converter 2 according to the second
exemplary embodiment. In the example shown in Fig. 14, in the second mode ,
25 0dB is defined as a circuit configuration value corresponding to the amplitude
control signals AC11 to AC14, -3VDD/4 is defined as a circuit configurat ion value
corresponding to the DC bias control signal SFT11, -VDD/2 is defined as a circuit
configuration value corresponding to the DC bias control signal SFT12, -VDD/4 is
defined as a circuit configurat ion value corresponding to the DC bias control
30 signal SFT13, and 0V is defined as a circui t configuration value corresponding to
the DC bias control signal SFT14. Moreover, in the analog-to-digi tal converter 3
according to the third exemplary embodiment, VDD/4 is defined as a circui t
configuration value that specifies the maximum reference voltage REF+, and GND
is defined as a circuit configurat ion value that specifies the minimum reference
25
voltage REF-. That is, in the second mode according to the third exemplary
embodiment, the input range of the analog-to-digital converter 3 from the ground
voltage GND to the power supply voltage VDD is realized using th e ADC cel ls 11
to 14.
[00625 ]
The ADC cell control unit 111 varies the amplification factor of the
variable gain amplifier 120 according to the above -mentioned circuit configuration
values and also varies the shift amount of the variable level -shift circui t.
[0063]
10 Next, operations in the first and second modes of the analog-to-digi tal
converter 3 according to the third exemplary embodiment, respectively, shall be
explained in more detail. Fig. 15 is a timing chart showing an operation in the
first mode of the analog-to-digital converter 3 according to the third exemplary
embodiment. As shown in Fig. 15, in the analog-to-digital converter 3 operating
15 in the first mode, the ADC cell s 11 to 14 sequent ially perform a sampling
operation. Moreover, the input ranges of the ADC cells 11 to 14 have the same
voltage range. Accordingly, the analog-to-digital converter 3 according to the
third exemplary embodiment can perform the conversion processing at a
conversion speed that is four times the conversion speed that can be achieved by
20 one ADC cell. That is, in the first mode, the analog-to-digital converter 3
realizes an improvement in the conversion speed by the time -interleaved
configuration composed of the ADC cel ls 11 to 14.
[0064]
Fig. 16 is a timing chart showing an operat ion in the second mode of the
25 analog-to-digital converter 3 according to the third exemplary embodiment . As
shown in Fig. 16, in the second mode of the analog-to-digital converter 3, the ADC
cells 11 to 14 perform the conversion processing at the same sampling timings.
Further, in the analog-to-digital converter 3, the input ranges of the ADC cell s 11
to 14 are the same voltage range, but by level -shifting the signal levels of the
30 signals for conversion according to the respective ADC cell s, the conversion
processing is performed on all ranges of the signals for conversion. Hence, the
analog-to-digital converter 3 can realize conversion accuracy that is four t imes the
conversion accuracy of one ADC cell . That is, the analog-to-digital converter 3
realizes an improvement in the conversion accuracy by the ampl itude -interleaved
26
configuration composed of the ADC cel ls 11 to 14 in the second mode.
[0065]
An operation of the preprocessing circuits 11p to 1np shall now be
explained in more detai l. An example in which the number of ADC cells is four is
explained here. Fig. 17 is a timing chart showing an operation of th5 e
preprocessing circuit in the second mode of the analog-to-digital converter. Note
that in the first mode, as the shift amount is 0V in all the preprocessing circuits, an
explanation of the operation in the first mode shall be omit ted.
[0066]
10 As shown in Fig. 17, in the second mode, an analog signal Vin is input.
Moreover, this analog signal Vin has an amplitude center voltage Vcm. As the
amplitude control signals AC11 to AC14 are 0dB, the preprocessing circuits 11p to
1np use this analog signal as the intermediate analog signal MOUT. Next, the
preprocessing circui ts 11p to 1np level -shift the intermediate analog signal MOUT
15 according to the DC bias control signals SFT11 to SFT14 and generate the signals
for conversion PreOUT1 to PreOUT4.
[0067]
At this time, as -3VDD/4 is specified as the value of the DC bias control
signal SFT11, a DC bias level of the signal for conversion PreOUT1 is lower than
20 that of the intermediate analog signal by -3VDD/4. As -VDD/2 is specified as the
value of the DC bias control signal SFT12, a DC bias level of the signal for
conversion PreOUT2 is lower than that of the intermediate analog signal by
-VDD/2. As -VDD/4 is specified as the value of the DC bias control signal
SFT13, a DC bias level of the signal for conversion PreOUT3 is lower than that of
25 the intermediate analog signal by -VDD/4. As 0V is specified as the value of the
DC bias control signal SFT14, the signal level of the signal for conversion
PreOUT1 is the same as that of the intermediate analog signal.
[0068]
Next, a relationship between the signals for conversion PreOUT1 to
30 PreOUT4 and the input ranges of the ADC cell s 11 to 14 shal l be explained. Fig.
18 shows an example of assigning the input ranges of the analog-to-digital
converter according to the third exemplary embodiment in the second mode. As
shown in Fig. 18, in the third exemplary embodiment , the signals for conversions
obtained by level -shifting the intermediate analog signal MOUT are suppl ied to the
27
ADC cells 11 to 14. Then, an upper quarter of the intermediate analog signal is
assigned to the input range of the ADC cell 11, a port ion of the intermediate analog
signal from an upper quarter to an upper half thereof is assigned to the input range
of the ADC cell 12, a portion of the intermediate analog signal from a lower half to
a lower quarter thereof is assigned to the input range of the ADC cell 13, and 5 a
lower quarter of the intermediate analog signal is assigned to the input range of the
ADC cell 14.
[0069]
Note that as mentioned above, it may be possible to input a vol tage outside
10 the convertable range to the respective ADC cells. For example, in Fig. 18, there
is a period for the ADCs 11 to 14 in which analog signals outside the ranges
convertable by the respective ADC 11 to 14 are input. In such a period, digital
values output by the ADCs 11 to 14 are invalid. In general , the ADC cel l has a
function that outputs an over-range signal if a signal exceeds an upper limit of the
15 convertable range and outputs an under -range signal if a signal fal ls below a lower
limit of the convertable range. It is thus easily realizable to adopt only effect ive
digital values using these signals. Alternatively, the ADC cells 11 to 14 may
output a signal indicating the effectiveness of the digital value together with the
digital value. In a further alternative, when an analog signal outside the
20 convertable range is input, the ADC cells 11 to 14 may clip the analog signal to
predetermined digital values such as a minimum value and a maximum value,
output a clipping monitor signal indicating the clipped state thereof, and when a
different ADC is outputting an effective digi tal value, may adopt the effective
digital value.
25 [0070]
According to the above explanation, in the analog-to-digital converter 3
according to the third exemplary embodiment, the preprocessing circuit
level -shifts the analog signal , to thereby control assignment of the ranges of the
signal levels in which the plurality of ADC cells perform the conversion
30 processing. That is, the analog-to-digital converter 3 according to the third
exemplary embodiment is a form of controlling assignment of the input ranges in
which the ADC cells perform the conversion processing, which is different from
that of the second mode in the first and second exemplary embodiments.
[0071]
28
Note that , although in the above-mentioned explanation, the input range of
the analog-to-digital converter 3 in the first mode is set to be the same as the input
range of the analog-to-digital converter 3 in the second mode, the input range of
the analog-to-digital converter 3 in the second mode may be greater than that in the
first mode. For example, the input range of the analog-to-digi tal converter 3 i5 n
the second mode can be four times greater than that of the analog-to-digital
converter 3 in the first mode. In this case, the circuit setting values
corresponding to the second mode are: AC11 to AC14=12dB; SFT11=-3VDD;
SFT12=-2VDD; SFT13=-VDD; SFT14=0V; VREF+=VDD; VREF-=GND; and
10 CLK11 to CLK14=0deg.
[0072]
Fourth exemplary embodiment
Fig. 19 is a block diagram of an analog-to-digital converter 4 according to
a fourth exemplary embodiment . As shown in Fig. 19, the analog-to-digital
15 converter 4 according to the fourth exemplary embodiment further includes , in
addi tion to the circui ts in the analog-to digi tal converter 2 according to the second
exemplary embodiment, an output data analysis unit 114 and a calibration signal
generat ion circuit 115. Moreover, in the analog-to-digital converter 4 according
to the fourth exemplary embodiment , in order to support a calibrat ion operation, an
20 ADC cell control unit 116 is provided in place of the ADC cell control unit 111,
and ADC cells 11a to 1na are provided in place of the ADC cells 11 to 1n. The
case in which the number of ADC cells n is two shall be explained below.
[0073]
The output data analysis unit 114 analyzes the size of an error between
25 digital values output by the ADC cells 11a and 12a and an ideal value. When the
mode specifying signal MD indicates the fourth mode, the circuit configuration
control unit 110 according to the fourth exemplary embodiment outputs the circuit
configuration values instructing one of the ADC cells 11a and 12a to perform the
conversion processing on the analog signal, and the other one of the ADC cells 11a
30 and 12a to perform the conversion processing on a cal ibration signal . Then, the
output data analysis unit 114 generates a correction value that corrects a deviation
between the digital value, which is a digital value obtained by converting the
calibration signal from the output data processing unit 113 based on the circuit
configuration values that are output corresponding to the fourth mode, and the
29
ideal value of the said digi tal value, and supplies the correction value to the ADC
cell control uni t 115.
[0074]
The calibration signal generation circuit 115 generates the calibration
signal. Note that the analog-to-digital converter 4 includes a switch circuit tha5 t
selects whether to supply the analog signal supplied from outside or the calibration
signal to the ADC cel ls.
[0075]
The ADC cell control unit 116 switches a signal which will be selected by
10 the switch circuit based on the circuit configuration values output by the circuit
configuration control unit 110. Moreover, the ADC cel l control unit 116 corrects
at least one of the voltage ranges of the first and second input ranges and input
offset voltages of the ADC cells 11a and 12a based on the correction value.
[0076]
15 The ADC cells 11a and 12a include a function to vary the input offset
voltages based on values of offset adjustment signals OFS11 and 12 that are output
from the ADC cell control unit 116.
[0077]
In the analog-to-digital converter 4 according to the fourth exemplary
20 embodiment, some of the plural ity of ADC cells are used to perform the conversion
processing on the analog signal. Meanwhile, in the analog-to-digital converter 4
according to the fourth exemplary embodiment , the calibration signal is supplied
to the ADC cells different from the ones used for the conversion processing, to
thereby perform calibrat ion processing. Then, the ADC cell that has been
25 performing the calibration processing and the ADC cell that has been performing
the conversion processing are switched at regular interval s. Note that a detailed
explanation of the calibration processing is provided in Japanese Unexamined
Patent Application Publication No. 2011-49646 that has been filed by the present
inventors.
30 [0078]
Hence, the analog-to-digital converter 4 according to the fourth exemplary
embodiment can cont inuously perform the conversion processing with few errors.
The conversion error will become greater due to the influence of environmental
changes, such as temperature and deterioration of the semiconductor elements ,
30
even when the conversion processing is continuously performed. Accordingly,
correcting the conversion error by such cal ibration processing has a considerable
significance.
[0079]
Note that when there is a period in which the conversion processing is no5 t
performed on the input analog signal , such as at the time of startup of the
analog-to-digital converter 4, calibration signals may be supplied to all the ADC
cells and the calibration processing may be performed in such a period.
[0080]
10 Fifth exemplary embodiment
Fig. 20 is a block diagram of an analog-to-digital converter 5 according to
a fifth exemplary embodiment . As shown in Fig. 20, the analog-to-digital
converter 5 according to the fifth exemplary embodiment includes an ADC cell
array in which a plurality of ADC cells having a funct ion the same as that of the
15 ADC cells 11 and 12 are arranged in an array. The example shown in Fig. 20
illustrates an ADC cell array of n rows and m columns (n is an integer indicat ing
the number of rows of the cell array, and m is an integer indicating the number of
columns of the cell array). Moreover, in the example shown in Fig. 20, ADC cel ls
11 to 1n are defined as a first sub-ADC cell array 101, ADC cel ls 21 to 2n are
20 defined as a second sub-ADC cell array 102, and ADC cells m1 to mn are defined
as an mth ADC cell array 10m.
[0081]
The analog-to-digital converter 5 according to the fifth exemplary
embodiment includes the circui t configuration control unit 110, the ADC cell
25 control unit 111, the sampl ing clock generation unit 112, and the output data
processing circuit 113. As the basic functions of these circuit blocks are the same
as those of the blocks of the analog-to-digi tal converter 1 according to the first
exemplary embodiment, an explanation thereof is omitted here.
[0082]
30 A configurat ion table of the circuit configuration control unit 110
according to the fifth exemplary embodiment includes the circuit configuration
values that specify one of the plurality of ADC cells used to perform the operation
corresponding to the first and second modes (or other mode s). Fig. 21 shows an
example of the configuration definit ion table of the analog-to-digital converter 5
31
according to the fifth exemplary embodiment. The example of the configuration
definition table shown in Fig. 21 assumes n=4 and m=4. The configuration
definition table shown in Fig. 21 is for arranging the ADC cells in the
amplitude-interleaved configuration by using the ADC cell array and arranging the
plurality of sub-ADC arrays in the time-interleaved configuration5 .
[0083]
Fig. 22 is a timing chart showing an operat ion of the analog-to-digital
converter 5 according to the fifth exemplary embodiment based on the
configuration definit ion table shown in Fig. 21. As shown in Fig. 22, the
10 analog-to-digital converter 5 that operates based on the configurat ion definition
table shown in Fig. 21 operates the respective sub -ADC cell arrays in the
amplitude-interleaved configurations, to thereby perform the conversion
processing with higher accuracy than in the conversion processing by one ADC
cell. Moreover, the analog-to-digital converter 5 that operates based on the
15 configuration table shown in Fig. 21 operates the sub -ADC cel l arrays in the
time-interleaved configuration, to thereby perform the conversion processing at an
operation speed that is higher than that at which the conversion processing by one
ADC cell is performed. That is, the analog-to-digital converter 5 that operates
based on the configuration definition table shown in Fig. 21 can achieve operation
20 characteristics with the highest conversion accuracy and the highest conversion
speed in the graph shown in Fig 11.
[0084]
Fig. 23 shows another example of the configuration defini tion table of the
analog-to-digital converter 5 according to the fifth exemplary embodiment . The
25 example of the configuration definit ion table shown in Fig. 23 assumes n=4 and
m=4. The configuration definit ion table shown in Fig. 23 forms an amplitude
interleaved configuration by the ADC cells 11 and 12, which are the first sub -ADC
array, forms an ampli tude-interleaved configuration by the ADC cells 31 and 32,
which are a third sub-ADC cell array 103, and places other ADC cells in a dormant
30 state. That is, when n=2 and m=1, the configuration definition table of the circuit
configuration control unit 110 includes the circuit configurat ion values, which
correspond to when the mode specifying signal MD indicates the third mode, that
set the first and second input ranges to the same voltage range and place one of the
first and second sampling clocks CLK11 and CLK12 in the dormant state, thereby
32
enabling some of the ADC cells to be in the dormant state.
[0085]
Note that the above "dormant state" of the ADC cells indicates that the
ADC cells have stopped analog-to-digital conversion and have lower power
consumpt ion than in the state where performing of the conversion processing i5 s
possible. There are various methods for placing the ADC cel ls in such a dormant
state, such as stopping supply of power or clocks to the ADC cel ls or disconnection
of the circuit through which current flows regularly. For example, generally,
when the supply of sampling clocks to the ADC cells is stopped, the powe r
10 consumpt ion of the ADC cells is reduced but cannot be eliminated. Meanwhile,
when the power to the ADC cel ls is blocked to place the ADC cells in the dormant
state, it is necessary for the circuit configuration control unit 110 to supply a
dormant signal to the ADC cells and switch the ADC cel ls to the dormant mode.
[0086]
15 Fig. 24 is a timing chart showing an operat ion of the analog-to-digital
converter 5 according to the fifth exemplary embodiment based on the
configuration definit ion table shown in Fi g. 23. As shown in Fig. 24, the
analog-to-digital converter 5 that operates based on the configurat ion definition
table shown in Fig. 23 operates the ADC cells 11 and 12 in the
20 amplitude-interleaved configuration and the ADC cells 31 and 32 in the
amplitude-interleaved configuration, to thereby perform the conversion processing
with accuracy higher than that in the conversion processing by one ADC cell. At
this time, as shown in Fig. 24, the analog-to-digital converter 5 forms the
amplitude interleaved configurat ion by the two ADC cells, thereby having the
25 conversion accuracy equivalent to that of the fifth mode in Fig. 11. Moreover, the
analog-to-digital converter 5 that operates based on the configurat ion definition
table shown in Fig. 23 operates the f irst sub-ADC cell array 101 and the third
sub-ADC cel l array 103 in the time-interleaved configuration, thereby performing
the conversion processing at an operating speed higher than that in the conversion
30 processing by one ADC cell . At this time, as shown in Fig. 24, the
analog-to-digital converter 5 forms the amplitude interleaved configurat ion by the
two ADC cells, thereby having the conversion accuracy equivalent to the fifth
mode in Fig. 11. That is, the analog-to-digi tal converter 5 that operates based on
the configuration definition table shown in Fig. 23 can achieve operating
33
characteristics equivalent to those of the fifth mode in the graph shown in Fig. 11.
Further, when achieving the operating characteristics equivalent to those of the
fifth mode, the analog-to-digital converter 5 can reduce the power consumption by
placing the unused ADC cells in the dormant state.
[00875 ]
As described above, the analog-to-digital converter 5 according to the fifth
exemplary embodiment defines the input ranges and operation t imings of the ADC
cells by the circuit configurat ion values in the circuit configuration table and sets
these definitions according to the operation mode. Hence, the analog-to-digital
10 converter 5 according to the fifth exemplary embodiment can realize the minimal
configuration that can achieve the operation characteristics necessary for
converting an input analog signal and place the unused ADC cel ls in the dormant
state. That is, the power consumption of the analog-to-digi tal converter 5
according to the fifth exemplary embodiment can consist only of the power
15 consumed by the ADC cells that are necessary to achieve the required operat ion
performance.
[0088]
Sixth exemplary embodiment
The above exemplary embodiments employ a method for redu cing the
20 quantization step voltage or increasing the number of quantization steps by joining
the input ranges of the plurality of ADC cells so they become one input range.
However, there are various methods for reducing the quantization step voltage or
increasing the number of quantization steps other than the above -mentioned
method. Therefore, in the sixth exemplary embodiment, a modified example of a
25 method of combining the plurality of ADC cells shall be explained.
[0089]
Fig. 25 shows a modified example of the configurat ion table that sets input
ranges of the analog-to-digital conversion cells in the analog-to-digi tal converter
according to the present invention. Fig. 25 shows only the values related to the
30 input ranges of the analog-to-digital conversion cells from among the circuit
configuration values of the configuration definition table. Moreover, Fig. 25
shows the circuit configuration values of the maximum reference voltages and the
minimum reference voltages for first to fifth modified exampl es. The modified
examples which wi ll be explained in the sixth exemplary embodiment include an
34
overlapped range where a part of a first input range and a part of a second input
range wil l be the same voltage range, and further, the first and second input ranges
are set so that a step boundary value of the first quantizat ion step and a step
boundary value of a second quant ization step will be different values. Here, the
step boundary value is a value indicat ing a threshold at which a digital valu5 e
obtained as a conversion result changes.
[0090]
First, in the first modified example, a voltage range corresponding to a
voltage difference between the power supply vol tage VDD and the ground voltage
10 GND shall be an input range of the analog-to-digital converter 2 according to the
second exemplary embodiment . The input range of the analog-to-digital
converter 2 according to the second exemplary embodiment is realized by a
combination of the ADC cel l s 11 to 14. In the first modified example, each of the
ADC cells 11 to 14 has an input range corresponding to the vol tage difference
15 between the power supply voltage VDD and the ground voltage GND, and absolute
values of the input ranges are set to differ by one LSB from each other. Note that
the quantization step vol tage of one LSB in the first modified example is set to the
size obtained by dividing the input range realized by the combination of the ADC
cells 11 to 14 (e.g. , the power supply voltage VDD) by the number of quantization
20 steps 32, which will be (VDD/32).
[0091]
Fig. 26 shows a relationship between the input ranges of the respective
ADC cells 11 to 14 that are set based on such circuit configurat ion values as
described above and the input range of the analog-to-digital converter 2 realized
25 by the combinat ion of the ADC cells 11 to 14. As shown in Fig. 26, the ADC
cells 11 to 14 that are set based on the first modified example have eight levels of
the number of quantization steps and the quant ization step voltage of VDD/8.
However, as the absolute values of the input ranges of the ADC cells 11 to 14 are
set to differ by one LSB from each other, the quantization step voltages between
30 the ADC cells are set to complement each other. Further, the input range of the
analog-to-digital converter 2 according to the second exemplary embodiment has
32 levels of the number of quantization steps and the quantization step voltage of
VDD/32.
[0092]
35
Next, in the second modified example, a voltage range corresponding to the
voltage difference between the power supply vol tage VDD and the ground voltage
GND shall be the input range of the analog-to-digital converter 2 according to the
second exemplary embodiment . The input range of the analog-to-digital
converter 2 according to the second exemplary embodiment is realized b y th5 e
combination of the ADC cell s 11 to 14. In the second modified example, each of
the ADC cells 11 to 14 has a voltage range which is half of that of the power
supply voltage VDD. That is, in the second modified example, each of the ADC
cells 11 to 14 has a quant ization step voltage of VDD/16. The ADC cells 11 and
10 12 perform the conversion processing for an upper half of the input range of the
analog-to-digital converter 2, and the ADC cells 13 and 14 perform the conversion
processing for a lower half of the input range of the analog-to-digital converter 2.
Moreover, in the second modified example, the absolute value of the input range of
the ADC cell 11 and the absolute value of the input range of the ADC cell 12 are
15 set to differ by one LSB from each other, and the absolute value of the input range
of the ADC cell 13 and the absolute value of the input range of the ADC cell 14 are
set to differ by one LSB from each other. Note that the one LSB of the
quantization step voltage in the second modified example is set to a size that is
obtained by dividing the input voltage real ized by the combination of the ADC
20 cells 11 to 14 (e.g. , the power supply voltage) by the number of quantization steps
32, which will be (VDD/32).
[0093]
Fig. 27 shows a relationship between the input ranges of the respective
ADC cells 11 to 14 that are set based on such circuit configurat ion values and the
25 input range of the analog-to-digital converter 2 realized by the combination of the
ADC cells 11 to 14. As shown in Fig. 27, the ADC cel ls 11 to 14 that are set
based on the second modified example have eight levels of the number of
quantization steps and the quantizat ion step voltage of VDD/16. However, as the
absolute values of the input ranges of the ADC cells 11 and 12 are set to differ by
30 one LSB, and the absolute values of the input ranges of the ADC cells 13 and 14
are set to differ by one LSB, the quantizat ion step vol tages between the ADC cel ls
are set to complement each other. Moreover, the ADC cells 11 and 12 are in
charge of performing the conversion processing for the upper half of the input
range of the analog-to-digital converter 2, and the ADC cells 13 and 14 are in
36
charge of performing the conversion processing for the lower half of the input
range of the analog-to-digital converter 2. Thus, the input range of the
analog-to-digital converter 2 according to the second exemplary embodiment has
32 levels of the number of quantization steps and VDD/32 of the quantizat ion step
voltage5 .
[0094]
In the first and second modified examples, the absolute values of the input
ranges are set so that the input ranges of the plurality of ADC cells are overlapped,
and the quantizat ion step vol tages of the plurality of ADC cells are complement
10 each other. Hence, i t is possible to reduce the quantization step voltage of the
digital values obtained by the analog-to-digi tal converter 2, whi le increasing the
quantization step voltages of the plurality of ADC cells. Increasing the
quantization step voltages for the respective ADC cel l s enables a reduction in an
input offset of a comparator that evaluates a size relationship between a signal
15 level of an analog signal and a reference voltage in the ADC cel l and a reduction in
influences on the digital value, such as noise generated inside the ADC cells.
[0095]
Next, the third to fifth modified examples shall be explained. In the first
and second modified examples, the input range of the analog-to-digi tal converter 2
20 is quant ized equally, however in the third to fifth modified examples, the input
range of the analog-to-digital converter 2 is quant ized unequally.
[0096]
In the third modified example, the voltage range corresponding to the
voltage difference between the power supply vol tage VDD and the ground voltage
25 GND shall be the input vol tage of the analog-to-digital converter 2 according to
the second exemplary embodiment . The input range of the analog-to-digital
converter 2 according to the second exemplary embodiment is realized by the
combination of the ADC cell s 11 to 14. In the third modified example, each of
the ADC cel ls 11 and 14 has a voltage range of a third of the power supply vol tage
30 VDD, and each of the ADC cells 12 and 13 has a voltage range of 1/6 of the power
supply voltage VDD. That is, in the third modified example, each of the ADC
cells 11 and 14 has a quantization step voltage of VDD/24, and each of the ADC
cells 12 and 13 has a quantization step voltage of VDD/48. That is, in the third
modified example, the minimum quantizat ion step vol tage is set to VDD/48.
37
Then, the ADC cell 11 performs the conversion processing for a upper third of the
input range of the analog-to-digital converter 2, the ADC cells 12 and 13 perform
the conversion processing for a middle third of the input range of the
analog-to-digital converter 2, and the ADC cell 14 performs the conversion
processing for a lower third of the input range of the analog-to-digital converter 5 2.
Moreover, the ADC cell 12 performs the conversion processing for an upper half of
the middle third of the input range of the analog-to-digital converter 2, and the
ADC 13 performs the conversion processing for a lower half of the middle third of
the input range of the analog-to-digital converter 2.
10 [0097]
Fig. 28 shows a relationship between the input ranges of the resp ective
ADC cells 11 to 14 that are set based on such circuit configurat ion values and the
input range of the analog-to-digital converter 2 realized by the combination of the
ADC cells 11 to 14. As shown in Fig. 28, the ADC cel ls 11 to 14 that are set
15 based on the third modified example each have eight levels of the number of
quantization steps, the quantizat ion step voltages of the ADC cells 11 and 14 are
set to VDD/24, and the quantization step voltages of the ADC cells 12 and 13 are
set to VDD/48. Further, different voltage ranges in the input range of the
analog-to-digital converter 2 are assigned as the input ranges of the ADC cell s 11
20 to 14. Hence, the analog-to-digital converter 2 according to the second
exemplary embodiment can set small quantization step voltages in a part of the
input range whi le having 32 levels of the number of quant ization steps as a whole.
[0098]
Next, the fourth modified example shall be explained. In the fourth
25 modified example, the voltage range corresponding to the volta ge difference
between the power supply voltage VDD and the ground voltage GND shall be the
input voltage of the analog-to-digital converter 2 according to the second
exemplary embodiment. The input range of the analog-to-digital converter 2
according to the second exemplary embodiment is realized by the combination of
30 the ADC cells 11 to 14. In the fourth modified example, the input ranges are set
so that parts of the input ranges of the ADC cells 11 and 12 are overlapped.
Moreover, in the fourth modified example, in the overlapped input range, the
quantization step voltage of the ADC cell 11 and the quantization step voltage of
the ADC cell 12 are set to complement each other. Here, in the fourth modified
38
example, the minimum quantization step voltage (LSB) shall be VDD/25. The
maximum reference voltage of the ADC cell 11 is set to VDD, the minimum
reference voltage is set to GND+9LSB, the maximum reference voltage of the ADC
cell 12 is set to VDD-9LSB, and the minimum reference voltage is set to GND.
Therefore, in the input range of the analog-to-digital converter 2 that is set base5 d
on the fourth setting example, nine levels in the middle part of the input range
have VDD/25 of the quantization step voltage, and the input ranges above and
below the nine levels have 2VDD/25 of the quantizat ion step width and the
numbers of levels thereof is four. That is, in the fourth setting example, the input
10 range of the analog-to-digital converter 2 is divided unequally into 17 levels.
[0099]
Fig. 29 shows a relat ionship between the input ranges of the respective
ADC cells 11 and 12 that are set based on such circui t configuration values and the
input range of the analog-to-digital converter 2 realized by the combination of the
15 ADC cells 11 and 12. As shown in Fig. 29, in the input range of the
analog-to-digital converter 2 that is set based on the fourth sett ing example, nine
levels in the middle part of the input range have VDD/25 of the quantization step
voltage, and the input ranges above and below the nine lev els have 2VDD/25 of the
quantization step width and the numbers of levels thereof is four. Hence, the
20 analog-to-digital converter 2 according to the second exemplary embodiment can
set small quantization step voltages in a part of the input range while ha ving 17
levels of the number of quantization steps as a whole.
[0100]
Next, the fifth modified example shall be explained. In the fifth modified
25 example, the voltage range corresponding to the voltage difference between the
power supply voltage VDD and the ground voltage GND shall be the input voltage
of the analog-to-digital converter 2 according to the second exemplary
embodiment. The input range of the analog-to-digital converter 2 according to
the second exemplary embodiment is realized by the combi nation of the ADC cell s
30 11 to 14. Here, in the fifth modified example, the input ranges are set so that
parts of the input ranges of the ADC cells 11 and 12 are overlapped and parts of the
input ranges of the ADC cells 13 and 14 are overlapped. Further, in the fifth
modified example, the ADC cel ls 11 and 12 perform the conversion processing for
the upper half of the input range of the analog-to-digital converter 2, and the ADC
39
cells 13 and 14 perform the conversion processing for the lower half of the input
range of the analog-to-digital converter 2. Furthermore, in the fifth modified
example, in the overlapped input range, the quantizat ion step voltages of the ADC
cells 11 and 12 are set to complement each other, and the quantization step
voltages of the ADC cells 13 and 14 are set to complement each other. Here, i5 n
the fourth modified example, the minimum quantization step vol tage (LSB) shal l
be VDD/48, and further, the entire number of quantization steps shall be 32 levels.
[0101]
Fig. 30 shows a relationship between the input ranges of the respective
10 ADC cells 11 to 14 that are set based on such circuit configurat ion values and the
input range of the analog-to-digital converter 2 realized by the combination of the
ADC cells 11 to 14. As shown in Fig. 30, in the input range of the
analog-to-digital converter 2 that is set based on the fifth setting example, regions
where the quant ization step voltage will be VDD/48 are set to two parts of the
15 input ranges. That is, the analog-to-digital converter 2 according to the second
exemplary embodiment can set a small quantization step voltage in a plurality of
ranges of the input ranges while having 32 levels of the number of quantization
steps as a whole.
[0102]
20 By setting unequal intervals between the quant ization step voltages based
on the circuit configurat ion values of the third to fifth modified examples, it is
possible to achieve a quantization step voltage that is smaller than the quantization
step vol tage obtained by dividing the power supply voltage by the total number of
the quantization steps of the plural ity of ADC cells having the same number of
25 quantization steps.
[0103]
As shown in the examples shown in Figs. 28 to 30, sett ing unequal
sampl ing accuracy (e.g., the quantizat ion step vol tage) in t he amplitude direction
produces an effect of quantizing only important components wi th high accuracy
30 using ADC cells having poor performance in the signal processing. In a
communicat ions system, important information for the signal processing in the
information included in signals may be unevenly distributed. In such a case,
when all the input ranges are processed with the conversion accuracy for the
important information, it is necessary to improve the performance of all the
40
plurality of ADC cells, thereby causing a problem that the circuit size increases.
However, by convert ing only the important parts with high accuracy, it is possible
to simplify the configurations of the plurality of ADC cells and thus reduce the
circuit size. Moreover, the reduction in the circuit size leads to a reduction in the
power consumption5 .
[0104]
Seventh exemplary embodiment
In the seventh exemplary embodiment, a modified example of a method for
control ling sampling timings shall be explained. More particularly, in this
10 modified example, circuit configuration values having unequal sampl ing intervals
to thereby vary the sampling accuracy in the time -axis direction will be explained.
[0105]
Fig. 31 shows an example of the circuit configuration values that set
unequal sampling intervals. The example shown in Fig. 31 is an example in
15 which the sampling clock generation unit 112 generates an eight -phase sampling
clock and selects the first to fourth sampling clocks CLK11 to CLK14 from the
eight-phase sampling clock. As shown in Fig. 31, in these circuit configuration
values, the size of the input range of the ADC cells 11 to 14 shall be the voltage
difference between the power supply voltage VDD and ground voltage GND.
20 Further, the circuit configurat ion values specify: 0deg c lock is selected as the first
sampl ing clock CLK11; -90deg clock is selected as the second sampling clock
CLK12; -135deg clock is selected as the third sampling clock CLK13; and -315deg
clock is selected as the fourth sampl ing clock CLK14.
[0106]
25 Fig. 32 is a timing chart showing an operat ion of the analog-to-digital
converter 2 based on the circuit configurat ion values shown in Fig. 31. As shown
in Fig. 32, in the analog-to-digital converter 2 that operates based on the circuit
configuration values of Fig. 31, when the sampl ing clock generation unit 112
outputs clocks having different phases from among a multiple-phase clock as the
30 first sampl ing clock CLK11 and the second sampling clock CLK12, the sampling
clock generation unit 112 selects the clocks whi ch will be the first to fourth
sampl ing clocks CLK11 to CLK14 from the multiple -phase clock so that the
sampl ing timings of the ADC cell s 11 to 14 will be unequal. In the region wi th
close sampling intervals, the resolution in the time -axis direction can be high,
41
whereas in the region with distant sampling intervals, the resolution in the
time-axis direction can be low.
[0107]
Note that in Fig. 32, an example of performing a sampling operation using
four ADC cells is explained. However an operation at unequal sampl ing interval5 s
can be realized by using only two ADC cells. In such a case, when clocks having
different phases from among the mult iple-phase clock are output as the first and
second sampling clocks, the sampling clock generation unit 112 select s the clocks
from the multiple-phase clock as the first and second sampling clocks so that the
10 sampl ing timings of the first and second analog-to-digital conversion cells wi ll be
unequal.
[0108]
Next, another modified example that varies the sampl ing accuracy in the
time-axis direction shall be explained. In the above explanation, an example in
15 which all of the ADC cell s 11 to 14 have the same number of quant ization steps
(bit accuracy) has been explained. However in the modified example explained
below, the ADC cells 11 and 14 and the ADC cells 12 and 13 have different
numbers of quantizat ion steps. More specifically, the ADC cells 11 and 14 have
the number of quantization steps of 3-bit accuracy (eight levels), and the ADC
20 cells 12 and 13 have the number of quantization steps of 4-bit accuracy (16 levels).
[0109]
Fig. 33 is a timing chart showing an operat ion in the first mode of the
analog-to-digital converter 2 according to another modified example. As shown
in Fig. 33, the analog-to-digital converter 2 according to this modified example
25 outputs digital values quantized by the number of quantization steps that differ
from sampl ing timing to sampling timing.
[0110]
As in the examples shown in Figs. 32 and 33, unequal sampl ing accuracy in
the time-axis direction (the quant ization timing or the quantizat ion step vol tage)
30 produces an effect that makes it possible to quant ize only the important
components wi th high accuracy using ADC cells having poor performance in the
signal processing. In a communications system, important information for the
signal processing in the information included in signals may be unevenly
distributed. In such a case, when all the input ranges are processed with the
42
conversion accuracy for the important information, it is nec essary to improve the
performance of all the plurality of ADC cells, thereby causing a problem that the
circuit size increases. However, by converting only the important parts with high
accuracy, it is possible to simplify the configurations of the plural ity of ADC cells
and thus reduce the circuit size. Moreover, the reduction in the circuit size lead5 s
to reduction in the power consumption.
[0111]
Note that the ADC cells wi th different degrees of conversion accuracy can
realize the setting example of the input range in the second mode shown in Fig. 28
10 by using three ADC cells. For example, the input range shown in Fig. 28 can be
realized by using the three ADC cells 11, 12, and 14 and placing the ADC cell 13
in the dormant state.
[0112]
The present invention has been explained so far with reference to the
15 exemplary embodiments, however the present invention is not limited by the
above. Various modifications obvious to a person skilled in the art can be made
to the configuration and details of the present invention within the scope of the
invention.
[0113]
20 The present application claims priority rights of and is based on Japanese
Patent Application No. 2011-216427 filed on Sep 30, 2011 in the Japanese Patent
Office, the entire contents of which are hereby incorporated by reference.
Reference Signs List
25 [0114]
1-5 ANALOG-TO-DIGITAL CONVERTER
11, 12, and 13, 1n ADC CELL
11p, 12p, and 13p, and 1np PREPROCESSING CIRCUIT
11a, 12a, and 13a, 1na ADC CELL
30 21, 22, and 23, 2n ADC CELL
m1, m2, m3, and mn ADC CELL
101, 102, and 10m SUB-ADC CELL ARRAY
110 CIRCUIT CONFIGURATION CONTROL UNIT
111, 116 ADC CELL CONTROL UNIT
43
112 SAMPLING CLOCK GENERATION UNIT
113 OUTPUT DATA PROCESSING CIRCUIT
114 OUTPUT DATA ANALYSIS UNIT
115 CALIBRATION SIGNAL GENERATION CIRCUIT
5
44

WE CLAIM:
1. An analog-to-digital converter comprising:
a first analog-to-digital conversion cell that quantizes a voltage level of an
analog signal within a first quantizat ion range at a first quantization step and
outputs a first digital value5 ;
a second analog-to-digi tal conversion cel l that quantizes the vol tage level
of the analog signal within a second input range at a second quantization step and
outputs a second digi tal value;
control means for, when a mode specifying signal indicates a first mode,
10 generat ing a control signal that sets the first and second input ranges to the same
voltage range and sets first and second sampling clocks to different phases, and
when the mode specifying signal indicates a second mode, generating the control
signal that sets the first and second input ranges to one cont inuous voltage range
and sets the first and second sampling clocks to the same phase;
15 ADC cell control means for controlling the voltage ranges of the first and
second input ranges according to the control signal;
sampl ing clock generation means for supplying the first and second
sampl ing clocks to the first and second analog-to-digital conversion cel ls,
respectively, according to the control signal; and
20 an output data processing circuit that merges the first and second digi tal
values and outputs output data.
2. The analog-to-digi tal converter wherein the ADC cell control means
outputs a first maximum reference voltage that sets a maximum value of the first
25 input range, a first minimum reference vol tage that sets a minimum value of the
first input range, a second maximum reference voltage that sets a maximum value
of the second input range, and a second maximum reference voltage that sets a
minimum value of the second input range, and switches voltage values o f the first
and second maximum reference voltages and vol tage values of the first and second
30 minimum reference voltages according to the control signal .
3. The analog-to-digi tal converter according to Claim 1 or 2, further
comprising a preprocessing circuit that converts an amplitude of the analog signal
to be in a voltage range convertable by the first and second analog-to-digital
45
conversion cells and generates an intermediate analog signal.
4. The analog-to-digi tal converter according to Claim 3, wherein the
preprocessing circui t outputs a first conversion input signal obtained by
level -shifting a signal level of the intermediate analog signal by a first shif5 t
amount according to the voltage range of the first input range and a second
conversion input signal obtained by level -shifting the signal level of the
intermediate analog signal by a second shift amount according to the voltage range
of the second input range, outputs the first conversion input signal to the first
10 analog-to-digital conversion cel l, and outputs the second conversion input signal
to the second analog-to-digital conversion cell.
5. The analog-to-digi tal converter according to Claim 4, wherein the ADC
cell control means varies a size of each of the first and second shift amount s
15 according to the control signal.
6. The analog-to-digi tal converter according to Claim 5, wherein the ADC
cell control means changes an amplification factor of the preprocessing circui t
according to the control signal.
20
7. The analog-to-digi tal converter according to any one of Claims 1 to 6,
wherein
when the control signal that is output corresponding to the first mode is
input, the output data processing circuit outputs the first digital value and the
25 second digital value as output data, and when the cont rol signal that is output
corresponding to the second mode is input , the output data processing circuit
outputs data that is obtained by merging the first and second digi tal values
according to a conversion table as the output data.
30 8. The analog-to-digi tal converter according to any one of Claims 1 to 7,
wherein when the mode specifying signal indicates a third mode, the control means
outputs the control signal that sets the first and second input ranges to the same
voltage range and places one of the fi rst and second sampling clocks in a dormant
state.
46
9. The analog-to-digi tal converter according to any one of Claims 1 to 8,
further comprising:
an output data analysis uni t that analyzes a size of an error between the
digital values output by the first and second analog-to-digital conversion cells an5 d
an ideal value; and
a calibration signal generation circuit that generates a calibration signal ,
wherein
when the mode specifying signal indicates a fourth mode, the control means
10 outputs the control signal for instructing one of the first and second
analog-to-digital conversion cel ls to perform conversion processing on the analog
signal and the other one of the first and second analog -to-digital conversion cells
to perform conversion processing on the calibration signal,
the output data analysis unit generates a correction value for correcting a
15 deviation between a digital value that is obtained by converting the calibrat ion
signal from the output data processing unit based on the control signal that is
output corresponding to the fourth mode and an ideal value of the digital value and
supplies the correction value to the ADC cell control means,
the ADC cell control means corrects at least one of the voltage ranges of
20 the first and second input voltages and an input offset voltage of the
analog-to-digital conversion cel l based on the correction value.
10. The analog-to-digital converter according to any one of Claims 1 to 9,
wherein when the first and second input ranges are set based on the control si gnal
25 that is output corresponding to the second mode, the ADC cell control means sets
the first and second input ranges so that the first input range and the second input
range will have an overlapped range where a part of the first input range and a part
of the second input range will be the same voltage range, and further, a step
boundary value of the first quantizat ion step and a step boundary value of the
30 second quantization step will be different values.
11. The analog-to-digital converter according to any one of Claims 1 to 10,
wherein a step width of the first quant ization step and a step width of the second
quantization step are set different values.
47
12. The analog-to-digital converter according to any one of Claims 1 to 11,
wherein the first quantization step and the second quantization step are different .
13. The analog-to-digital converter according to any one of Claims 1 to 125 ,
wherein the sampling clock generat ion unit selects whether to output clocks having
different phases from among a multiple-phase clock as the first and second
sampl ing clocks or to output one clock selected from the multi -phase clock as the
first and second sampling clocks.
10
14. The analog-to-digital converter according to Claim 13, wherein when
the clocks having different phases from among the mult i -phase clock are output as
the first and second sampling clocks, the sampling clock generation unit selects
clocks which will be the first and second sampling clocks from the multi -phase
15 clock so that an interval between a f irst sampling timing, which is a sampl ing
timing of the first analog-to-digital conversion cell , and a second sampling timing,
which is a sampling t iming of the second analog-to-digital conversion cell , wi ll be
different from an interval between the second sampl ing timing and the first
sampl ing timing.
20
15. The analog-to-digital converter according to any one of Claims 1 to 14,
further comprising:
a third analog-to-digi tal conversion cell that quantizes a voltage level of
the analog signal within a third input range at a third quantization step and outputs
25 a third digital value; and
a fourth analog-to-digi tal conversion cel l that quantizes a voltage level of
the analog signal within a fourth input range at a fourth quantization step and
outputs a fourth digital value, wherein
the sampling clock generation unit further outputs third and fourth
30 sampl ing clocks which will be suppl ied to the third and fourth analog -to-digital
conversion cells, respectively, and
the control means,
when the mode specifying s ignal indicates the first mode, outputs
the control signal that sets the first to fourth input ranges to the same voltage
48
range, and further, sets the first to fourth sampling clocks to different phases,
when the mode specifying signal indicates the second mode, outputs
the control signal that sets the first to fourth input ranges to one cont inuous
voltage range, and further, sets the first to fourth sampl ing clocks to the same
phase, an5 d
when the mode specifying signal indicates a fifth mode, outputs the
control signal that sets the first and second input ranges to one continuous vol tage
range, sets the third and fourth input voltages to one continuous voltage range, sets
a first sampling clock group including the first and second sampling clocks havin g
10 the same phase and a second sampling clock group including the third and fourth
sampl ing clocks having another same phase to different phases.
16. The analog-to-digital converter according to any one of Claims 1 to 15,
further comprising:
15 a conversion cell array that is composed of a plurality of analog -to-digital
conversion cells having a function equivalent to that of the first and second
analog-to-digital conversion cel ls,
wherein the control means outputs the control signal that instructs any one
of the plurality of analog-to-digital conversion cel ls to perform an operat ion
20 corresponding to the first and second modes.
17. A method for analog-to-digital conversion, the method comprising steps
of: a method for analog-to-digital conversion
quantizing a voltage level of an analog signal within a first input range at a
25 first quantization step and outputting a first digital value;
quantizing the voltage level of the analog signal within a second input
range at a second quantization step and outputtin g a second digi tal value;
when a mode specifying signal indicates a first mode, using a first
analog-to-digital conversion cel l having a first input range and a second
30 analog-to-digital conversion cel l having a second input voltage, sett ing the first
and second input ranges to the same voltage range, quant izing the voltage level of
the analog signal , and outputt ing the first digital value and the second digital value
at different sampling timings ;
when the mode specifying signal indicates a second mode, using the first
49
analog-to-digital conversion cel l and the second analog-to-digital conversion cell,
setting the first and second input ranges to one cont inuous voltage range, and
output ting the first digi tal value and the second digital value at the same sampling
timing; and
merging the first and second digital values and output ting output data.