4. BACKGROUND OF THE INVENTION

1. Field of invention

This invention relates to the formulation of Analog Signal Acquisition Card (ASAC) for Field Programmable Gate Arrays (FPGAs). In particular, it relates to a method of extending the functionality of on-board ADC channels in FPGA boards by providing a means of integrating analog multiplexer along with an embedded block. The embedded block developed inside the FPGA will have the full control of time multiplexing and selection of ADC channels thereby increasing the capability of FPGA board to handle more number of analog inputs that can be fed for processing. This embedded block also segregates and stores the digital values in different registers.

2. Description of the Related Art

Data acquisition systems (DAS), as the name notifies, are devices and/or components used to collect information in order to monitor or analyze some phenomenon. As electronic technology advances, the data acquisition process has been improved and has become accurate, versatile, and reliable through electronic devices. Data acquisition devices should interface to various sensors that specify the phenomenon under consideration. Most data acquisition systems obtain data from different kinds of transducers that produce analog signals. In most applications, these signals need some processing. Therefore, analog signals are converted into a digital form through analog to digital converter (ADC). A digital signal is superior to an analog signal because it is more robust to noise and can easily be recovered, corrected and amplified.

Existing DAS can acquire single channel or multi-channel signals. Many applications demand the existence of a multi-channel data acquisition. For example, power electronic applications in renewable energy systems (RES) and in flexible AC transmission systems (FACTS) require multi-channel data processing. Selection of the control device and specification of A/D converter are the important factors to design the system. Especially ADC should have high sampling rate and more number of channels for applications in digital control of power electronic systems.

As discussed above, there are extensive applications of multichannel DASs. However, existing multichannel DAS are cumbersome, expensive, and/or require design redundancy to achieve high reliability and high speed acquisition. Therefore, embedded processing capability systems must be used to reduce system size, avoid design redundancy, reduce cost and power consumption. Field Programmable Gate Array (FPGA) is one such technology in embedded systems field. FPGA has various advantages such as, it allows design upgrades without hardware replacement and also it provides a wide range of digital signal processing (DSP) operations. An example of state of the art FPGA devices is Xilinx Spartan 3 AN (XC3S1400AN-4FGG676C).

Summary of the Invention

Recently, many operations are accomplished by digital signal processing systems which in turn require signals to be in digital form. This process is done by ADC. An intuitive implementation of the multi-channel A/D conversion is to use a dedicated ADC for each channel. However, this approach has drawbacks such as multi-ADCs are expensive and special synchronous techniques are required across all ADCs. Another ADC technique is time division multiplex with a single ADC. The method has unique challenges such as time skewness and utilisation of ADC has to be optimized. Most of the ADCs use time division multiplex, wherein number of channels is less. So majority of the FPGA boards have less number of ADC channels, which limits its use as controller in power applications.

Here the integration of analog multiplexer with FPGA boards to enhance the capability of handling more number of analog signals by onboard ADC channels is presented. The value of selection bits for analog multiplexer are provided and controlled from embedded block developed inside the FPGA board, which operates with a programmable clock. The integrated module is designed specifically for applications in power electronic systems, wherein the fundamental frequency of analog signal is usually of either 50 Hz or 60 Hz. For illustration purpose, module is tested with both AC and DC signals. Four AC signals with a frequency of 50 Hz and 100 Hz are given to four input lines of the multiplexer. Further AC signals containing harmonics are given to the input of the multiplexer and the multiplexed signal is ted to brUA through one ot the channels ot existing on-board ADC the same is repeated for 8 and 16 DC signals. Multiplexed signal is de-multiplexed in the FPGA using hardware description language (HDL) coding, and the signals can be used for various computations depending upon the requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 describes the block diagram of digital controller for Power Electronics System which indicated the requirement of ADCs.

Fig. 2 indicates the block diagram of proposed analog signal acquisition System.

Fig. 3 shows the flow chart of the proposed scheme.

Fig. 4 presents the photograph of the setup implemented in the laboratory.

Fig. 5 is a photograph of the purported integrated module

Fig. 6 shows the multiplexed output when four AC signals (sine, triangular, ramp and square) of frequency 50 Hz each are given as input to multiplexer.

Fig. 7 presents the four signals (sine, triangular, ramp and square), which are incurred by de-multiplexing the signal in Fig. 6.

Fig. 8 shows the multiplexed output when four AC signals (sine, triangular, ramp and square) of frequency 100 Hz each are given as input to multiplexer.

Fig. 9 depicts the four signals (sine, triangular, ramp and square), which are incurred by de-multiplexing the signal in Fig. 8.

Fig. 10 shows the multiplexed output when four AC signals (sine and three harmonic signals) are given as input to multiplexer.

Fig. 11 depicts the four signals, which are obtained by de-multiplexing the signal in Fig. 10.

Fig. 12 shows the output of the multiplexer when fed from eight DC signals.

Fig. 13 evinces the photograph of the eight DC signals displayed on the monitor, which are obtained by de-multiplexing the signal in Fig. 12.

Fig. 14 shows the output of the multiplexer when fed from sixteen DC signals at the input.

Fig. 15 evinces the photograph of the sixteen DC signals displayed on the monitor, which are obtained by de-multiplexing the signal in Fig. 14.

DETAILED DESCRIPTION

The conceptual design of the proposed system is illustrated in Fig. 2. In this figure, 2N (or less) analog signals are connected to an analog multiplexer which in turn select one of them depending on the n-bit combination of selection lines. The output of the multiplexer is given to the on-board ADC. The multiplexer controller is embedded into the FPGA as well. For testing the developed algorithm analog multiplexer (CD74HC4067) procured from Texas instruments (TI) is used. Analog Multiplexer is a 24 pin IC, which has sixteen channels and it can be used as a multiplexer or a de-multiplexer depending upon the application. FPGA board employed for this purpose is Altium Nano-Board, which inherently has ADC (ADC084S021) and Xilinx Spartan 3AN FPGA on it. On-board ADC has an operating frequency of 3.2 MHz and can be configured to accept four input signals. ADC when operated at the maximum functioning frequency of 3.2 MHz can have a sampling rate of 200 ksps, i.e. when operated in single (four) channel, the sampling rate is 200 (50) ksps.

Digital controllers for power electronic applications such as FACTS, converters and drives require greater number of ADC channels (> 8 ch), wherein the fundamental frequency of the input analog signal usually of either 50 Hz or 60 Hz.

So instead of sampling a low frequency signal of 50 Hz or 60 Hz at a higher sampling rate of 200 ksps, a method is proposed in which the multiplexer is added to each ADC channel present on-board thus increasing the functionality of the existing board. A counter is formed for the digital data read from the ADC, which is given as selection bits for analog multiplexer through I/O pins of the host FPGA
board. As the number of channels are increased at the input of the multiplexer, the sampling rate of the analog signal decreases. The relationship between sampling rate and number of channels is given below
Maximum Sampling rate Sampling rate with N channels =

As most of the power electronic applications require 8 to 16 ADC channels, a test case is considered in which four AC signals are given to a multiplexer, thus extending each channel of the on-board ADC to four channels.

The host FPGA considered has four ADC channels, with the addition of a four channel multiplexer in each channel; a total of sixteen signals can be accessed by FPGA. An embedded module is developed inside the FPGA to provide the selection bits for multiplexer and to capture the digitized data of each signal in different registers so that the samples of each signal (out of 16) will be stored in different locations for further processing inside the FPGA. So, the sampling rate of each analog signal is 12.5 ksps, which is sufficient for digital conversion of an analog signal with frequency 50 Hz or 60 Hz. Also, reproducing of original analog input signal will be possible with the above mentioned sampling rate.

In another test case the algorithm is tested with DC signals. This case is tested with 8 and 16 DC signals, making the number of channels accessed by FPGA to 32 and 64 respectively. The sampling rate with 8(16) channel multiplexer is 6.25 (3.125) ksps, which can replicate the DC signals. As a part of testing, the proper reproduction of analog input signal is tested with the help of on-board DAC and also through VGA display with appropriate computations.

DESCRIPTION OF PREFERRED EMBODIMENTS

Fig. 1 describes the block diagram of a digital controller for Power Electronics System. It can be observed that the voltage and current signals of source and load are given to digital controller through A/D converter. Based on the requirements, several computations are performed on the input signals and pulses are generated, which are given to the inverter.

Fig. 2 indicates the block diagram of proposed analog signal acquisition system, where a 2N: 1 multiplexer is connected to each channel of on-board ADC. The selection bits for multiplexer are obtained from the embedded module developed inside the FPGA. Further, it can be observed the digitized data is stored in the registers.

Fig. 3 depicts the flow chart of the HDL coding implemented in the FPGA Board. As per the flowchart, the total number of ADC channels are taken as 'X', the inputs and selection bits of multiplexer is considered as 2N and N respectively. The size of register array (D) to store digital values inside FPGA is equal to 2 * X, each register D(J) is accessed using the pointer 'J'.

It is also considered that one multiplexer (2 :1) is connected to every ADC channel. Each ADC channel will be chosen sequentially and after that the selection bits of the multiplexer connected to it will be varied to get 2N digital values. Since the total number of ADC channels is taken as 'X', the total number of digital
values obtained from ADC and fed to FPGA will be 2N * X. For example, if each channel of the four channel ADC is connected with 4:1 multiplexer then the total number of ADC channels are enhanced to 4 * 4 (number of ADC channels * number of multiplexer inputs), which is equal to sixteen.

Fig. 4 presents the photograph of the setup implemented in the laboratory.

Function Generator (FG) and Regulated Power Supply (RPS) are used for giving the AC and DC signals respectively. Waveforms are recorded by Digital Signal Oscilloscope (DSO).

Fig. 5 is a photograph of the purported integrated module. It can be ascertained that the selection bits for Analog Multiplexer are furnished from I/O ports of the device. Further, it is shown that the multiplexer output is given to the channel 1 of the on-board ADC.

Fig. 6 shows the multiplexed output of the multiplexer with four AC signals (sine, triangular, ramp and square) of frequency 50 Hz each.

Fig. 7 shows the four signals (sine, triangular, ramp and square), which are incurred by de-multiplexing the signal in Fig. 6. The waveforms are observed through four channel DAC, (DAC084S085) which is present on the board and are recorded by DSO.

Fig. 8 shows the multiplexed output of the multiplexer with four AC signals (sine, triangular, ramp and square) of frequency 100 FIz each.

Fig. 9 depicts the four signals (sine, triangular, ramp and square), which are incurred by de-multiplexing the signal in Fig. 8. The waveforms are observed through four channel DAC, (DAC084S085) which is present on the board and are recorded by DSO.

Fig. 10 shows the multiplexed output when four AC signals (sine and three harmonic signals) are given as input to multiplexer.

Fig. 11 depicts the four signals, which are obtained by de-multiplexing the signal in Fig. 10. The waveforms are observed through four channel DAC, (DAC084S085) which is present on the board and are recorded by DSO.

Fig. 12 shows the output of the multiplexer when fed from eight DC signals. In this case eight DC signals of different amplitudes are given to the input of the multiplexer, which gives a multiplexed output. Further, HDL coding is developed to de-multiplex the signals, and is implemented in the device.

Fig. 13 evinces the photograph of the de-multiplexed signals displayed on the monitor when multiplexer is fed from eight DC signals.

Fig. 14 shows the output of the multiplexer when fed from sixteen DC signals at the input.

Fig. 15 evinces the photograph of the de-multiplexed signals displayed on the monitor when multiplexer is fed from sixteen DC signals.

IMPACT
Most of the FPGA boards available in the market are having lesser number of ADC channels, which limits its applications. So, with the addition of a low cost ASAC to the host FPGA board, multi-channel signal acquisition can be done by using the existing FPGA board, thereby extending its applications. ASAC is aimed mainly for power electronic applications, which requires larger number of ADC channels for signal acquisition and processing. The developed embedded block controls the multiplexer through the host FPGA board thereby avoiding the problems of synchronization.

In conventional multiplexing 'N' number of selection bits are used to multiplex 2 signals. In the proposed scheme, same N number of selection bits are used to multiplex 2N * X signals. Hence lesser number of i/o pins of FPGA are utilised for selection bits. Consequently, more number of i/o pins will be left for other tasks. The processing time taken by FPGA and the cost incurred to develop the ASAC card is less compared to any other signal/data acquisition cards.

5. CLAIMS

1. We claim that the Analog Signal Acquisition Card (ASAC) is developed for the FPGAs with lesser number of on-board ADC channels with an intention to use it for power electronic applications.

2. We claim that of claim 1, include integration of analog multiplexer to the host FPGA board along with embedded block.

3. We claim that of claim 2, the selection bits for analog multiplexer are provided and controlled from I/O pins of host FPGA board.

4. We claim that of claim 2, embedded block developed has full control of time multiplexing and the selection of ADC channels thereby increasing the number of analog inputs.

5. We claim that of claim 2, embedded block also segregates and store the digital values in different registers for further processing.

6. We claim that the device of claim 1, implements an extensive algorithm to implement the above claims in hardware.

7. We claim that the ASAC developed in claim 1 can be implemented using any analog multiplexer and any programmable device with lesser number of ADC channels.