Abstract: Analog & Synchro Acquisition Module is a electronic board used in Data Acquisition System (DAS) of Flight Data Recorder. This module receives multiple Analog Signal and Synchro signal representative of various aircraft parameters. A single address command from the flight data recorder central processing unit (CPU) causes a first multiplexer to select a set of analog signals. Each selected analog signal is passing through overvoltage & spike protection circuit to protect the internal hardware of module. After Voltage protection & spike suppression analog signals are conditioned for making compatible to each signal for digital conversion using analog to digital converter. Signal is passing through Buffer, amplification & de-amplification circuit for conditioning. For analog parameters, Analog to Digital Converter is carried out while Synchro to digital converter converts Synchro parameters to digital. It can handle analog input data of both Uni-polar & Bi-polar type. This module provides input impedance buffer for analogue DC aircraft parameter, which are an integral part of the analog multiplexers & multiplex the signals into a common data bus.
This invention relates to Analog & Synchro Acquisition Module (ASAM) for use in
Data Acquisition System (DAS) of Flight Data Recorders and, more particularly, to fight
data acquisition systems for receiving fight data signals in a variety of signal forms like
Analog, Synchro & Ratio metric (OAT Signals).
BACKGROUND OF THE INVENTION
Flight data recorders are monitoring and recording instruments, carried aboard
an aircraft, which systematically monitor and store the instantaneous values of various
aircraft parameters. Early recorders were analog electromechanical devices which
periodically marked, in analog form, the value of a given airplane parameter on a
moving wire or other permanent storage medium. The time of occurrence of the
parameter was also suitably scribed into the medium opposite the mark for the sensed
parameter. Subsequently, digital flight data recorders have been developed which
operate by converting each analog aircraft parameter into a corresponding digital signal,
and storing the digital signals on a permanent storage medium such as magnetic tape.
The numerous mechanical parts employed in the analog and digital type
electromechanical flight data recorders have rendered such units expensive to construct
and bulky in design, requiring periodic maintenance of the mechanical parts. In addition,
extraction of the stored data from these data recorders requires physical removal of the
storage medium.
The development of solid state memory devices, such as electrically erasable
read-only memory, has led to the design of all solid state flight data recorders. The solid
state flight data recorders commonly employ a data acquisition system (DAS) which
receives and processes the various aircraft input signals to be monitored and stored
under the control of a central processing unit (CPU). The analog signals are converted
to digital signals by the DAS and, under CPU control, are passed over a data bus to the
solid state memory devices. Programming within the CPU controls the processing of
input airplane signals to corresponding digital signals through the DAS and the
subsequent transference of these digital signals to controlled locations in the solid state
memory.
Annexure‐II
The signals representative of monitored aircraft parameters are typically either
discrete level signals or analog signals. Discrete signals are typically switch positions
and produce either a high or a low level output depending upon the status of the
particular switch. A typical example in an aircraft is a squat switch, which indicates
whether or not a load is being borne by the landing gear.
The analog signals may be straight DC signals, DC ratio metric signals, Synchro
signals or AC ratio metric signals. The DC signals are static in nature, and generally
range between a minimum and maximum value for the parameter being monitored. DC
ratio metric signals are DC signals having a ratio representative of the value of the
parameter being sensed. A typical DC ratio metric signal is that produced by a
potentiometer having a DC voltage applied across its resistive element, with the wiper
position indicative of the level of the sensed parameter. Thus, the ratio of the wiper
voltage to the voltage across the potentiometer’s resistive element represents the level
of the parameter being monitored.
Synchro is commonly employed to indicate the angle of a parameter. A Synchro
sensor is normally excited by two reference AC signals and outputs three active AC
signals. The relative phasing and amplitude between the active AC signals and the
reference signals indicate the angle of the Synchro and, thus, the angle of the sensed
parameter. A typical AC ratio metric aircraft signal is that produced by a linear variable
differential transformer (LVDT). LVDTs are commonly employed to indicate the relative
position of aircraft control surfaces. Here, the ratio of the LVDT output sense AC signal
to a reference AC signal is indicative of both total deflection and direction of deflection
of the control surface.
To accurately collect data from Synchro and ratio metric-type sensors, therefore,
the Analog & Synchro Acquisition Module (ASAM) of DAS should simultaneously collect
and hold each signal associated with the multi signal-type sensor. Further, it is desirable
to minimize the overhead on ‘the CPU in its accessing of data as collected by the DAS.
In prior art flight data recorder designs, the CPU sends a request to the DAS asking for
the value of a given aircraft parameter and this parameter is then selected, processed,
and analog-to-digital converted by the DAS which then signals the CPU that the
requested information is available. Since a large number of air plane parameters may
be monitored by the flight data recorder, constant requests by the CPU on the DAS
significantly increases CPU overhead.
Further, it is desirable to conform the flight data recorder such that it is capable of
being conveniently modified to operate in any one of several different types of aircraft.
To this end, the DAS is preferably configured such that its inputs may be assigned by
Annexure‐II
the CPU to handle any analog or Synchro input signal. Further, the levels of the various
signals at the inputs of the DAS must often be sealed for proper processing within the
DAS. For example, in as much as all input signals are analog-to-digital (A/D) converted;
the ASAM typically includes a single chip 12-bit A/D converter.
The accuracy of an A/D converter is a function of the signal level applied at the
input to the converter. To minimize A/D converter errors, therefore, it is essential that
each aircraft parameter sensor signal be scaled before being applied to the A/D
converter. In order to assure a universal flight data recorder design, the scaling factors
applied to each input signal should be under CPU control.
SUMMARY OF PRESENT INVENTION
The present invention, therefore, is directed to analog & Synchro acquisition
module (ASAM) of data acquisition system for use in a Flight data recorder.
An aspect of the present invention is the ability of the data acquisition system to
process a set of parameter sense signals in response to a single CPU request. In this
way, integrity of multiple signal sensor data is assured and overhead on CPU operation
is reduced.
A further aspect of the invention is the universal application of the present data
acquisition system. Analog or Synchro aircraft parameter signals may be assigned to
any of the multiple data acquisition system inputs under CPU control. Further, the
ASAM is responsive to CPU control to vary the scaling applied to each input signal.
Briefly, according to the invention, analog & Synchro acquisition module for an aircraft
flight data recorder is responsive to a central processor unit (CPU) for selectively
processing a plurality of input signals.
The ASAM comprises a multiplexer which outputs selected sets of the input
signals, with each selected input signal set being output responsive to a corresponding
address command signal. Logic is responsive to a single command from the CPU for
producing each address command signal. Each signal in a selected signal set is
processed by provided processing means.
Preferably, the processing means includes input impedance buffer for analogue
DC aircraft parameter, which are an integral part of the analog multiplexers & multiplex
the signals into a common data bus.
Annexure‐II
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent
and descriptive in the description when considered together with figures/flow charts
presented:
Figure 1: is a Block Diagram of Analog & Synchro Module (ASAM) of FDAU
Figure 2: is a Block Diagram of Processing of out Side Air Temperature (OAT)
Of ASAM
Figure 3: is a Block Diagram of Flight Data Acquisition Unit (FDAU) of FDR
DETAILED DESCRIPTION
This electronic module receives all the Analog parameters coming to FDR unit.
Module converts Analog inputs into Digital format to make compatible for storage in
Solid-state memory.
Analog & Synchro Acquisition Module carries out the following functions:
• This card selects one of the aircraft Analog or Synchro parameter. Converts
selected parameter into 12 bit digital data.
• Built-In Test (BIT) for ASAM Module.
This module consists of 6 multiplexers and one ADC. It accepts aircraft analog
parameters as input & converts the selected analog parameter into 12 bit data. It can
handle the analog i/p data of uni-polar & bipolar of amplitude (levels 0-5V, ±5V, 0-10V
and ±10 V). The particular signal is selected depending on the address and control word
given. The module carries out the following functions:
1. Built in test
2. Selection of signals and multiplexing
3. Analog to digital conversion.
The built in tests are performed to check multiplexers and ADC. This module also
helps in monitoring the correctness of the power supply for the unit.
Inputs to the dual 8 channel multiplexers IC-U2 to IC-U7 are DC signals from
external sources. All the inputs have over voltage and over current protection which is
Annexure‐II
an integral part of these analog multiplexer ICs and these also provide input impedance
buffer for analog DC aircraft parameter.
The particular multiplexer is selected through the address decoder IC (3-8
decoders). The multiplexed O/ P of all these multiplexers are again multiplexed by the
second stage multiplexer IC. The particular analog input signal is selected by the 6
Address lines A1-A6.The output of the multiplexer IC is fed in to the differential input
instrumentation amplifier to get single ended output.
The output from instrumentation amplifier is fed to the ADC, which uses
successive approximation method to convert an analog signal to a 12 bit digital output.
This ADC gives 12-bit parallel output format, which provides easy interface to
microprocessor.
Functioning of the card can be divided into following blocks:
Multiplexer and decoder:
All the analog inputs shall be available at the input side of multiplexer. At a time,
only one input shall be routed for acquisition. Inputs to multiplexer are differential type
analog signals. All signal levels are not more than 10V. Output of the multiplexer stage
is same as multiplexer input. Selection of acquisition of a particular analog parameter
input is done by one multiplexer channel selection at a time. Decoder generates enable
signal depending on the input address bits from processor board. Address lines select
the multiplexer channel.
Instrumentation Amplifier
This block performs two functions:
• Provides high input impedance to incoming analog signals. This fulfils SSFDR
specification requirement of high input impedance.
• This converts differential signal into single ended signal. This is requirement
for ADC input.
This block receives input from multiplexer stage. Output of this block is same to
input in respect of signal voltage, but single ended analog.
Annexure‐II
A to D Conversion
This block takes single ended analog inputs and converts into 12-bit digital
format. 12-bit digital output becomes available at the data lines D0 to D11. Conversion
of analog into digital is initiated from processor board by writing Control Byte into ADC.
After completion of conversion, ADC gives one interrupt to processor to tell that data is
ready for reading. Processor runs one read cycle to read the data from ADC.
Synchro to Digital conversion
This is receives Synchro input and reference signal and converts into digital form.
Digital data is read by processor card.
PROCESSING OF ANALOG PARAMETERS
Aircraft Provides twenty one Analog Parameter from different on-board Sensors.
These Parameter are simultaneously Processed to provide 12-bit digital data under
software Control. Each Parameter is given with Pre-fixed Sampling Rate i.e. Particular
Should come Pre-defined time in a frame, which last for one second. Keeping this thing
in mind, such logic is developed which can implement above idea.
3:8 Decoders is used to select one out of four multiplexers of stage-I depending
upon address on address line. These same address lines are also used to select input
channel of stage –II multiplexer, Stage- I Contains four multiplexers whose input
channels are directly connect with output of Aircraft Sensor.
Stage- II multiplexer is followed by Instrumentation Amplifier, which converts
differential output into single- ended output. Since, this device implements three Op-
Amp circuit, it also imparts high input impedance.
This Single- ended input is fed to Analog to Digital Converter for 12-bit digital
data. This chip takes 6usec to convert Analog into digital data. Finally, 12-bit data is
directly interfaced with data bus of CPU (Micro- Controller).
PROCESSING OAT PARAMETER
A Conditioning circuit is used for resistive input (OAT) to convert it into equivalent
voltage form. Resistive input from the aircraft is fed into the voltage stabilizer circuit of
the OAT circuit. The voltage stabilizer uses voltage reference diodes each having a
Annexure‐II
reference voltage of 6.2V. The circuit produces a voltage of 28.8V. This voltage is
supplied across the Kelvin double bridge. The output of the bridge is amplified using a
differential amplifier. The differential amplifier produces non-linear output which is linear
zed using a logarithmic amplifier. The final output ranges from -5V to +5V.
PROCESSING SYNCHRO PARAMETER
Synchro to Digital Converter is used to convert Synchro inputs. This Hybrid is
Single Channel. Data Bus of SDC is directly interfaced with data bus of microcontroller.
3:8 Decoders is used to trigger both channels of Mono stable Multi vibrator
simultaneously. Initially, Channel-I is used to triggers INH (Active low) pin of SDC. This
results in freezing of data after a period of 500nsec. Now, Channel-2 of multi vibrator is
triggered. This in- turn triggers EM & EL (both active Low) for data extraction. Settling
time for these two Signals is 150nsec. Thus, after 150nsec 12-bit data will be available.
Two transformers are used to provide electrical isolation as well as coupling. First
transformer couples reference signal while other couples Synchro signal in order to
detect phase reversal, if any.
WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A Analog & Synchro Acquisition Module (ASAM) for an aircraft flight data recorder responsive to a central processor unit (CPU) for processing a plurality of input signals to provide a digitally encoded signal representative of a selected set of input signals each time the CPU provides a simple command signal, said digitally encoded signal being used by said CPU for generation of recorded flight data information, said data acquisition system comprising: multiplexing means for outputting said selected set of said input signals, each selected input signal set being output responsive to a corresponding address command signal; logic means responsive to said single command from said CPU for producing each address command signal; and processing means for processing each signal in a selected signal set to supply said digitally encoded signal representative of said selected set of input signals.
2. The ASAM of claim 1, wherein said processing means comprises: Voltage spike suppressor & overvoltage circuits means responsive to conditioning circuits.
3. The ASAM of claim 2, further comprising of input scaling circuit means for attenuating selected input signals by a predetermined scaling factor; and wherein said gain factors for said gain controlled amplifiers are selected such that each signal, after being attenuated in said input scaling circuit means and amplified by said gain controlled amplifier, is in a range selected to minimize analog-to-digital converter means error.
4. The ASAM of claim 2, wherein said means for supplying said signals at the output of said analog-to-digital converter means as said digitally encoded signal lncludes digital memory means for storing each analog-to-digital converted instantaneous value of a signal in a selected signal set; and wherein said controller means produces an interrupt signal to said CPU upon all of the analog-to-digital converter signals in a selected signal set being stored in said digital memory means.
5. The ASAM of claim 4, wherein said logic means responds to a single CPU command signal to:
(a) produce a predetermined address command signal such that said multiplexing means outputs said set of selected input signals,
(b) produce predetermined gain control command signals such that each signal in a selected signal set is amplified by a predetermined gain factor, and
(c) Activate said controller means such that the analog-to-digital converted instantaneous value of each signal in a selected signal set is loaded into said digital memory means.
6. The ASAM of claim 1, wherein at least three of said input signals are the twenty one analog output signals of a Synchro sensor and wherein said logic means produces an address command signal causing said multiplexing means to output said three Synchro signals as a selected signal set.
7. The ASAM of claim 1, wherein at least one of said input signals is an AC ratiometric signal and at least one of said input signals is the reference AC signal for said AC ratiometric signals and wherein said logic means produces an address command signal causing said multiplexing means to output said AC ratiometric and reference AC signals as a selected signal set.
8. A ASAM for an aircraft flight data recorder of the type that selectively records flight data information, said flight data acquisition system being responsive to a central processor unit (CPU) for selectively processing multiple input signals and supplying to said CPU for utilization in selective recording of flight. ,TagSPECI:As per Annexure-II
| # | Name | Date |
|---|---|---|
| 1 | Drawings.pdf | 2014-12-11 |
| 1 | Specification.pdf | 2014-12-11 |
| 2 | FORM3MP.pdf | 2014-12-11 |
| 2 | form5.pdf | 2014-12-11 |
| 3 | FORM3MP.pdf | 2014-12-11 |
| 3 | form5.pdf | 2014-12-11 |
| 4 | Drawings.pdf | 2014-12-11 |
| 4 | Specification.pdf | 2014-12-11 |