FIELD OF INVENTION
[001] The present invention generally relates to a solar hybrid inverter. More
specifically, the present invention relates to an anti-islanding protection system for a solar hybrid inverter.
BACKGROUND
[002] Solar energy is a clean and sustainable renewable source of power.
Solar power generation systems use Photo Voltaic (PV) cells for conversion of solar energy into electricity by photovoltaic effect. Effective utilization of power becomes a challenge whenever there is excess generation of power from solar energy. Solar power systems connected to a power grid can transfer excess power to the power grid when not used by a consumer. A power grid-connected PV system consists of solar panels, power inverter, power conditioning unit, and power grid connection equipment. The inverter converts Direct Current (DC) generated by the PV panels to Alternating Current (AC) for feeding in to the power grid.
[003] Solar hybrid inverters consists of a solar inverter combined with a
battery inverter/charger in a single unit. During the day time, the power generated by the solar panels is used to charge the battery and also for operation of electrically operated appliances. When the battery gets fully charged and the solar power is still available, excess power is fed into the power grid. In the evening or night time when the solar power isn't available, the power stored in the battery is utilised for operation of electrically operated appliances. Further, when the power stored in the battery gets exhausted, power from the power grid can be utilized for operation of electrically operated appliances.

[004] Islanding is a condition in which a solar power system provides power
to a power grid when the power grid is no longer present i.e. is down. Islanding can be dangerous to persons operating on the power lines, such as the personnel carrying out maintenance work on the power lines. Therefore, the solar power system should be able to detect islanding condition and immediately stop supply of power to the power grid. This process is known as anti-islanding. Anti-islanding protection is a mandatory safety feature, which detects islanding and disables the inverters immediately during failure of a grid. As per the UL1741/ IEEE 1547 standards, islanding should be detected within 2 seconds.
[005] In the existing technology, harmonic components are injected into the
grid power for detecting operating status of the power grid, to detect and terminate islanding operation. When the grid is active, a center frequency is identified as the frequency of operation of the power grid. Alternatively, when the grid is down, presence of the harmonic components is determined. Over the time, the harmonic components keep accumulating until the detection operation is terminated. Conventionally, to meet the standard islanding detection time of 2 seconds, more harmonic components are added in the grid power, which increases Total Harmonic Distortion (THD) of the feeding current. Additionally, the existing anti-islanding detection systems rely on the injection of selected harmonic current components and the evaluation of power grid response. The power grid response is then compared with a predefined threshold value for detecting power grid failure.
[006] Therefore, there is a need of an anti-islanding protection system, which
can detect islanding within the standard time of 2 seconds without compromising the quality of the current fed into the power grid.
OBJECTS OF THE INVENTION
[007] An object of the present invention is to provide an anti-islanding
protection system for a solar hybrid inverter.

[008] An object of the present invention is to provide an anti-islanding
protection system using a Second Order Generalized Integrator based Phase Locked Loop (SOGI-PLL).
[009] Another object of the present invention is to provide an anti-islanding
protection system which operates at low Total Harmonic Distortion (THD).
[0010] Another object of the present invention is to provide an anti-islanding protection system without compromising the quality of the current fed into a power grid.
[0011] Yet another object of the present invention is to provide an anti-islanding protection system with an islanding detection time of less than 2 seconds.
SUMMARY OF THE INVENTION
[0012] The summary is provided to introduce aspects related to an anti-islanding protection system for a solar hybrid inverter, and the aspects are further described below in the detailed description. This summary is not intended to identify essential features of the claimed subject matter nor is it intended for use in determining or limiting the scope of the claimed subject matter.
[0013] The present invention relates to an anti-islanding protection system for a solar hybrid inverter. The solar hybrid inverter comprises a buck converter for stepping down input power received from a Photo Voltaic (PV) panel assembly. A battery is connected to the DC-DC buck converter for storing stepped down output provided by the buck converter. A power inverter, such as an H-bridge converter, is connected to the battery, the mains supply, and a load terminal.
[0014] A microcontroller is connected to the buck converter, the power inverter, and the mains supply. The microcontroller stores programmed instructions to implement the SOGI-PLL for detecting failure of the mains supply and

disconnecting flow of power from the PV panel assembly to the mains supply during failure of the mains supply. Gate pulses are provided to the DC-DC buck converter and the power inverter by the microcontroller at a predefined frequency for achieving maximum power extraction from the PV panel assembly, charging the battery, and feeding excess power to the grid.
[0015] In one aspect, the AC power received from the mains supply is converted into DC power for storing in the battery and the DC power stored in the battery is converted into AC power to be provided to the load terminal.
[0016] In one aspect, the microcontroller is connected to the mains supply through an Analog to Digital Converter (ADC) for providing parameters of the mains supply to the SOGI-PLL. The SOGI-PLL is tuned at a deviated frequency from a centre frequency of the mains supply.
[0017] In one aspect, the deviated frequency ranges up to ± 0.005% of the centre frequency. The Total Harmonic Distortion (THD) of the mains feeding current is up to 3.5%. The islanding detection is done within 215 ms of failure of the mains supply.
[0018] Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The accompanying drawings constitute a part of the description and are used to provide further understanding of the present invention. Such accompanying drawings illustrate the embodiments of the present invention which are used to describe the principles of the present invention. The embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that

references to "an" or "one" embodiment in this invention are not necessarily to the same embodiment, and they mean at least one. In the drawings:
[0020] Fig. 1 illustrates a basic structure of a Phase Locked Loop (PLL), in accordance with an embodiment of the present invention;
[0021] Fig. 2 illustrates a Second Order Generalized Integrator (SOGI) for orthogonal signal generation, in accordance with an embodiment of the present invention;
[0022] Figs. 3a and 3b illustrate frequency responses of transfer functions Hd(s) and Hq(s) for different values of 'k', in accordance with an embodiment of the present invention;
[0023] Fig. 4 illustrates an exemplary block diagram of a SOGI-PLL with its input and output, in accordance with an embodiment of the present invention;
[0024] Fig. 5 illustrates a block diagram of a hybrid solar inverter utilizing a SOGI-PLL for islanding detection, in accordance with an embodiment of the present invention; and
[0025] Fig. 6 illustrates a flow chart showing a method of detecting power grid failure using a SOGI-PLL based anti-islanding protection system, in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0026] The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. Each embodiment described in this invention is provided merely as an example or illustration of the present invention, and should not necessarily be construed as preferred or advantageous over other

embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.
[0027] Fig. 1 illustrates a basic structure of a Phase Locked Loop (PLL), in accordance with an embodiment of the present invention. PLL is a negative feedback based closed-loop control system that generates an output signal whose phase is similar to the phase of an input signal. PLL includes an orthogonal signal generator 102, a park transformation unit 104, a Low Pass Filter (LPF) 106, and a Voltage Controlled Oscillator (VCO) 108.
[0028] When the power grid power is available, the PLL remains in an equilibrium condition. The PLL starts to deviate from the equilibrium condition when the power grid fails. Hence, the deviation of the PLL from the equilibrium condition can be used for detecting failure of the power grid. The flow of power from a Photo-Voltaic (PV) panel assembly to the mains supply may be disconnected once the power grid failure is detected.
[0029] Fig. 2 illustrates a SOGI for orthogonal signal generation, in accordance with an embodiment of the present invention. The SOGI uses two first-order integrators 202-1,202-2 for the orthogonal signal generation. The SOGI has a lower non-linearity and is easy to be implemented digitally.
[0030] As illustrated in Fig. 2, the SOGI generates two orthogonal signals v'a and v'aq (leading lagging v'a by 90°). These orthogonal signals have same amplitude and frequency as that of an input signal va.
[0031] The two characteristic transfer functions of the SOGI, for the orthogonal signals are obtained using the below mentioned equations.
Va S +KCDS + CD

H(s) = ^(s)= kG)1
q va s2 + kcos + co2
[0032] In above mentioned equations, 'co' denotes the resonant frequency of SOGI in rad/s and 'k' denotes a gain parameter which decides the level of filtering.
[0033] Figs. 3a and 3b illustrate frequency responses of the transfer functions Hd(s) and Hq(s) for different values of 'k', in accordance with an embodiment of the present invention. For low values of 'k', a band-pass region of a filter becomes narrower causing more selective filtering. However, very less values of 'k' makes the filter response slow. Therefore, a trade-off value of 'k', between the filter response and selectivity of filtering must be chosen. It could be observed from Figs. 3a and 3b that magnitudes (in dB) of transfer functions become zero at 50 Hz, which indicates that SOGI filters offer zero attenuation to fundamental frequency signals. Further, phase angles of Hd(s) and Hq(s) become 0° and -90° respectively, at 50 Hz. Therefore, the output signals v'a and v'aq are in-phase and quadrature with the fundamental component of input signal va, respectively.
[0034] For discrete implementation using trapezoidal approximation, the transfer function Hd(z) could be determined using the below mentioned equation.
2 z-l
H {z)_ &"TSZ + \ (2to„rs)(z2-i)
2 z-lV 2 z-l , 4(z-l)2+(2^„rj)(zi-l) + K7"J)(* + !)
Tz + \ "Tz + l
[0035] Substituting 2kconTs with 'x' and (conTs)2 with 'y' causes the above equation to be represented as:

\ x
, x + y + 4 HAz)~
yx + y + 4) [x I
1 Iz-
x + y + 4 J b0 i ft,z"
:-_y-4^ 2 l-aYz ' -fl2z" ■y + 4.

2

[0036] Similarly, the transfer function Hq(z) could be determined using the below mentioned equation.

Ly 1 + 2
, x + y + 4
Hq(z) = ± y-

k.y
x + y + 4

z +

k.y
x + y + 4 J qb0+qbiz +qb2z
-1 ,. _-2

x + y + 4

x + y + 4

[0037] In above mentioned equations used for determining the transfer functions Hd(z) and Hq(z), con denotes a notch frequency. The notch frequency is same as the system frequency, or the power grid frequency estimated by the PLL.
[0038] Fig. 4 illustrates an exemplary block diagram of a SOGI-PLL with its input and output, in accordance with an embodiment of the present invention. Power signal from a grid is provided to the SOGI-PLL. From the power signal, the SOGI-PLL estimates information of the grid, such as amplitude (Vims), frequency (fgiid), and phase angle. A pre-defined amount of deviation is added in input PLL frequency. After inclusion of the pre-defined amount of deviation, reference centre frequency of the PLL becomes co±8dn. The deviation to be added in the notch frequency (Sdn) is decided from resonant frequency (co) of the power grid. Upon inclusion of the deviation, the updated centre frequency becomes:
COn ~ 2 Tl tpowei grid i OUn.
[0039] The input to SOGI-PLL brings the output of the SOGI-PLL to fp0wei grid when the power grid is present/ live, because the power grid acts as a source with infinite impedance. Alternatively, when the power grid fails, the SOGI-PLL tries to bring the output of an inverter to the centre frequency. However, in such case the centre frequency is not the notch frequency co, but co±8dn. The deviation added in the PLL frequency continues to accumulate in each cycle, and increases exponentially.
[0040] For anti-islanding protection, a frequency error (Sf) is calculated in each cycle. When the frequency error (Sf) is greater than a maximum allowed error in

frequency (Sfmax), a deviation count (nerr) is increased by 1. When the deviation count (nerr) becomes greater than a predefined count (n) used to decide the power grid failure, the power grid failure decision is taken and the anti-islanding protection is enabled. Harmonic component may also be added in the system when 5f is greater than 8fmax to fast track the islanding detection.
[0041] Fig. 5 illustrates a block diagram of a hybrid solar inverter utilizing a SOGI-PLL for islanding detection, in accordance with an embodiment of the present invention. The hybrid solar inverter includes a PV panel assembly 502 for converting solar power into electrical power. The electrical power is transferred to a DC-DC buck converter 504. The DC-DC buck converter 504 steps down the electrical power received from the PV panel assembly 502. A battery 506 is connected to the DC-DC buck converter 504 for storing the electrical power.
[0042] A power inverter 508 is connected to the battery 506, a mains supply 510, and a load terminal 512 indicative of the appliance(s) to be operated using electric power. In one implementation, the power inverter 508 may include an H-bridge converter. The power inverter 508 may convert the DC power stored in the battery 506 into AC power to be provided to the load terminal 512 and convert the AC power received from the mains supply 510 into DC power for storing in the battery 506.
[0043] A net metering unit 514 may be connected with the mains supply 510 to track the amount of electrical power consumed from and supplied to the mains supply 510. When the battery 506 is fully charged and the electrical power produced by the PV panel assembly 502 is greater than power consumption at the load terminal 512, additional power is supplied to the mains supply 510 i.e. to the power grid.
[0044] A microcontroller 516 is connected with the DC-DC buck converter 504, the power inverter 508, and the mains supply 510. In one implementation, the microcontroller 516 may be connected with the DC-DC buck converter 504 through an Analog to Digital Converter (ADC) 518 and connected with the mains supply

510 through an ADC 520 for receiving details of operational parameters of the DC-DC buck converter 504 and the mains supply 510 respectively. Further, the microcontroller 516 provides gate pulses to the DC-DC buck converter 504 and the power inverter 508 at a predefined frequency for achieving maximum power extraction from the PV panel assembly 502, charging the battery 506, and feeding excess power to the mains supply 510 (power grid).
[0045] The microcontroller 514 may store program instructions to implement a SOGI-PLL 522. The SOGI-PLL 522 may detect failure of the mains supply 510 and may disconnect the connection between the PV panel assembly 502 and the mains supply 510 during failure of the mains supply 510, to stop flow of power from the PV panel assembly 502 to the mains supply 510. The SOGI-PLL 512 is tuned at a deviated frequency from a centre frequency of the mains supply. The deviated frequency may range up to ± 0.005% of the centre frequency. A Total Harmonic Distortion (THD) of the mains feeding current may be up to 3.5%. The islanding detection may be performed within 215 ms of failure of the mains supply.
[0046] Fig. 6 illustrates a flowchart showing a method of detecting the power grid failure using a SOGI-PLL based anti-islanding protection system, in accordance with an embodiment of the present invention. At step 602, information regarding the power grid, such as amplitude, phase, and frequency of operation of the power grid may be obtained from the SOGI-PLL. At step 604, notch frequency of the PLL may be deviated by a factor 8dn. With this, the reference centre frequency of the PLL becomes co±8dn. The deviation to be added in the notch frequency (8dn) may be decided based on resonant frequency (co) of the power grid.
[0047] At step 606, a frequency error 8f may be measured. At step 608, the measured frequency error (8f) is compared with a maximum allowed error in frequency (Sfmax). If the measured frequency error (8f) is determined to be greater than the maximum allowed error in frequency (8fmax), the method proceeds to step 610 where power grid feeding current is generated with a Proportional Resonant (PR) compensation. Alternatively, when the measured frequency error (8f) is

determined to be less than the maximum allowed error in frequency (Sfmax) at step 610, the deviation count may be increased and a harmonic component may be added to check on further deviation, at step 612. At step 614, the deviation count is compared with a predefined count (n). If the deviation count is higher than the predefined count (n), it is determined that the power grid has failed, at step 616. Alternatively, if the deviation count is determined to be less than the predefined count at step 614, the method proceeds to step 610.
[0048] A main advantage of the present invention is that the proposed anti-islanding protection system does not require continuous injection of harmonics into the system. Due to such reason, the proposed anti-islanding protection system ensures that THD of the feeding current is not deteriorated. The harmonics can be added to detect the power grid failure only when the frequency of the inverter is shifted. This in turn facilitates reduction of the detection time i.e. time to detect failure of the power grid.
[0049] The terms "or" and "and/or" as used herein are to be interpreted as inclusive or meaning any one or any combination. Therefore, "A, B or C" or "A, B and/or C" mean "any of the following: A; B; C; A and B; A and C; B and C; A, B and C." An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive.
[0050] Any combination of the above features and functionalities may be used in accordance with one or more embodiments. In the foregoing specification, embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the invention, and what is intended by the applicants to be the scope of the invention, is the literal and equivalent scope of the set as claimed in claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction.

We Claim:

1. An anti-islanding protection system for a solar hybrid inverter, comprising:
a buck converter (504) for stepping down input power received from a Photo
Voltaic (PV) panel assembly (502);
a battery (506) connected to the buck converter (504) for storing stepped down output provided by the buck converter (504);
a power inverter (508) connected to the battery (506), mains supply (510), and a load terminal (512); and
a microcontroller (516) connected to the buck converter (504), the power inverter (508), and the mains supply (510), wherein the microcontroller (516) stores programmed instructions to implement a Second Order Generalized Integrator based Phase Locked Loop (SOGI-PLL) (522) for detecting failure of the mains supply (510) and disconnecting flow of power from the PV panel assembly (502) to the mains supply (510) during failure of the mains supply (510).
2. The anti-islanding protection system as claimed in claim 1, wherein the power inverter (508) converts AC power received from the mains supply (510) into DC power before storing in the battery (506) and converts the DC power stored in the battery (506) into AC power before providing to the load terminal (512).
3. The anti-islanding protection system as claimed in claim 1, wherein the SOGI-PLL (522) is tuned at a deviated frequency with respect to a centre frequency of the mains supply (510).
4. The anti-islanding protection system as claimed in claim 3, wherein the deviated frequency ranges up to ± 0.005% of the centre frequency.
5. The anti-islanding protection system as claimed in claim 1, wherein the power inverter (508) is an H-bridge converter.

6. The anti-islanding protection system as claimed in claim 1, wherein a Total Harmonic Distortion (THD) of mains feeding current is up to 3.5%.
7. The anti-islanding protection system as claimed in claim 1, wherein the anti-islanding protection is done within a time period ranging from 130ms to 215 ms of failure of the mains supply (510).
8. The anti-islanding protection system as claimed in claim 1, wherein the microcontroller (516) provides gate pulses to the buck converter (504) and the power inverter (508) at a predefined frequency for achieving maximum power extraction from the PV panel assembly (502), charging the battery (506), and feeding excess power to the mains supply (510).
9. The anti-islanding protection system as claimed in claim 1, wherein the microcontroller (516) is connected to the mains supply (510) through an Analog to Digital Converter (ADC) (520) for providing details of operational parameters of the mains supply (510) to the SOGI-PLL (522).