FIELD OF INVENTION
The present invention relates to a plasma display apparatus and its driving method, more particularly related to sustain pulses capable of enhancing luminous efficacy and applicable to improvement in picture quality
BACKGROUND OF THE INVENTION
PDP is composed of a matrix of discharge cells that are formed by partitions made by barrier ribs between a pair of glass substrates. A Ne-Xe discharge between pair of electrodes on top glass substrate occurs in discharge cell to display visual effects. Each pair of electrodes form a capacitor between them and these electrodes are known as sustain electrodes, shown in Fig.5, and here in after referred as X (sustain) and Y (scan) electrodes. The third electrode is used for application of address voltage, here in after referred as A electrode. Three color (Red, Blue and Green) phosphors are provided on the surface of the respective barrier ribs, and the cell volume is filled with a gas mixture (Ne + Xe). During PDP operation, the gas discharge takes place between electrodes in the cells that result in the generation of Vacuum Ultra Violet (VUV) photons with a wavelength of 147 nm and 173 nm. These phosphors absorb these VUV photons and emit visible light to display a picture including characters and graphics.
Plasma Displays are considered the natural successors to the CRT TV, the household name for last 6-8 decades. Like CRTs, PDPs provide an emissive, phosphor-based solution that is well suited to showing full-color; fast moving video images with high Dark Room Contrast Ratio and wide viewing angle. The only drawback of PDP is low luminous efficacy which leads to low Bright Room Contrast Ratio and high power consumption. A PDP is classified as DC (direct current) PDP and AC (alternating current) PDP depending on discharge mode and drive waveform of driving voltage applied thereto. In case of capacitive impedance, at discharge site an alternating voltage applied. The waveform for driving PDP includes a reset period, a scan period, a sustain period and an erase period, in temporal sequence.
In reset period a voltage across X, Y and A electrodes maintained in such way that a weak discharge, in dark discharge regime, occurs for duration of hundreds of microseconds. This discharge used for conditioning of the cell with appropriate charges on the wall to facilitate addressing. During the addressing period a cell is selected for turning-ON/OFF. An address voltage is applied between Y and A electrodes leading to a strong discharge. Thereafter voltages on X and Y electrode is maintained to accumulate appropriated wall charges such that the breakdown of Ne-Xe gas mixture occurs at voltage lower than breakdown voltage (VB) between X and Y electrodes. During sustain period an AC voltage (sustain voltage, Vs) is applied between X and Y electrodes and discharge sustains in glow regime. The sustaining discharge is terminated by erase pulse during erase period.
In AC-PDP, a capacitance exists between sustain (X) and scan (Y) electrodes. This capacitance acts as capacitive load between the electrodes while sustaining. A circuit for applying a sustain pulses has been presented in Japanese patent No. 3201603 and US patent No. 7176 854 B2.

The driver circuit suggested in Japanese patent No. 3201603, alternatively applies voltage Vs/2 and -Vs/2 to the Y electrode of the panel capacitor by using a capacitor and voltage source for applying a voltage Vs/2 that is one half of the voltage Vs necessary for sustaining. In other words the driver circuit applies voltage VJ2 to the Y electrode of the panel capacitor through the voltage source, and charges the capacitor to voltage Vs/2. Then the capacitor is coupled between the ground terminal and the Y electrode of the panel capacitor to apply -VJ2 to the Y electrode of the panel capacitor. Like this, the positive voltage + VJ2 and the negative voltage -VJ2 can be alternatively applied to Y electrode. Similarly positive voltage + Vs/2 and the negative voltage -Vs/2 can be alternatively applied to X. The respective voltages Vs/2 applied to X and Y electrodes are phase-inverted to each other, so the voltage Vs/2 necessary for sustaining is applied to both terminal of panel capacitor. This driver circuit used, could swing the voltage pulse between -Vs/2 and +V/2, and the necessary voltage difference for sustaining Vs is attained between the X and Y electrodes. While, in US patent No. 7176 854 B2, the driver circuit proposed could swing both voltage pulses between 0V to Vs and 0V to -Vs.
In aforementioned prior arts, on application of sustain voltage to the discharge cells formed between the sustain electrodes generate light output during initial phase of applied sustain pulse, which is for very short duration. During the remaining period of the sustain voltage, the sustain voltage does not generate light output, rather provides sufficient time to ions to gain translational energy which is dumped on the cathode of discharge cell surface, during each half-cycle and resulting in higher sustain current and hence high power consumption.
OBJECT OF THE INVENTION
Luminous efficacy of conventional AC PDP is low because of low brightness and high power consumption during sustain period. This invention provides a method and an apparatus for driving a PDP with reduced current and enhanced brightness.
Yet another objective of the invention is to provide a method and an apparatus to improve luminous efficacy of the AC-PDP by improving brightness by at least one intense, elongated light output during each sustain period.
Yet another objective of the present invention is to provide an apparatus, for generating a bipolar sustain waveform for application of voltages on one of the sustain electrodes and for generating another bi-polar sustain waveform for application of voltages on another sustain electrodes with controlled rise-time, ON-time, fall-time and OFF-time, for sustaining the discharge.
Yet another objective of the present invention is to provide an apparatus having lower capacitive losses by generating bi-polar sustain waveform with appropriate rise time, fall time, ON time and OFF time.
STATEMENT OF INVENTION
Accordingly this invention provides an apparatus and method of driving AC-PDP having three electrodes including a discharge cell at the intersection of Address, Scan and Sustain electrodes by applying driving signals to the said electrode and in order to display information electrode on AC PDP. One frame of image information is divided into a number of subfields and each subfield has reset period, address period and sustain period. Sustain period emits light for visual effects by conversion of VUV photons into visible photons generated during sustain discharge according to display information. The sustain discharge causes current to flow through sustain electrodes and resulting in power consumption equal to multiple of applied voltage and discharge current. The current in a discharge cell which flows through sustain electrodes comprises of electron current and ion current and these together causes power consumption corresponding to applied voltage. Due to higher mass of ions the ion current could be limited provided that the applied pulse is short enough to minimize the translational energy gain of ions. The optimum sustain voltage Vs between sustain electrodes can be applied in different combination of voltages on X and Y electrodes as Vs = [Vy - (- Vx)J or Vs = [Vx-(- Vy)] in different temporal sequence such that translational energy gain of ions is minimum. The apparatus and the method for driving the AC-PDP with bi-polar sustain voltage pulses with pre-determined frequency and amplitude applied on each terminal of discharge cell to reduce the sustain current and improve the brightness have been disclosed in present embodiment of invention. The predetermined temporal sequence defines the applied frequency on each electrode. Aforementioned temporal sequence refers to, the instant of application of voltages on X and Y electrodes, time taken to attain the peak value of the applied voltages, the time for which electrodes are coupled to the voltage sources, the time taken to reach to ground voltage from peak value of the applied voltages, time for which the electrodes are coupled to the ground are predetermined to limit the sustain current by reducing the ion current as well as the displacement current.
The sustain voltage Vs between X and Y electrodes i.e. between sustain electrodes, forming two end of discharge cell, is attained in at least two steps. A positive polarity voltage, say VI is applied on one of the terminals (i.e., Y electrode) of discharge cell and a negative polarity voltage, say V2 is applied on another terminal (i.e. X electrode) of the discharge cell such that Vs=Vl-(-V2). The polarity of voltages is reversed in next half cycle. The rise time, i.e. time taken to attain peak voltages on the electrodes after coupling the terminals of power supplies to the electrodes is different and pre-determined, i.e. the rate of voltage rise on first and second electrode is different and varied in range of lx8 Volts/Second to 8xl010 Volts/ Second.
Brightness of the plasma display panel is improved by application of such modulated sustain waveform on sustain electrodes without increasing the sustain current.
BRIEF DESCRIPTION OF DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of invention.
FIG. 1 is a schematic of bi-polar driver circuit;
FIG. 2 is a temporal sequence diagram showing the driving operation of bi-polar driver
circuit as illustrated in FIG. 1;
FIG. 3 is a schematic of bi-polar driver circuit with energy recovery;
FIG. 4 is a temporal sequence diagram showing the driving operation of bi-polar driver circuit with energy recovery as illustrated in FIG. 3;
FIG. 5 is a schematic of plasma display panel related to the present invention; FIGS.6 to 20 are illustrations showing current path in each mode of the driver circuit of bipolar driver according to the embodiment related to present invention;
FIG. 21 is a schematic of driver for asymmetrical ultra short bipolar wave form
FIG. 21a is a schematic of driver circuit for bipolar sustain wave form with multiple light output.
FIG. 22a is a schematic of conventional uni-polar sustain waveform;
FIG. 22b is a schematic of conventional bipolar sustain wave-form:
FIG. 23 is a schematic of new ultra short bi-polar sustain waveform with appropriate temporal sequence on X and Y electrode;
FIG. 24 is a schematic of bi-polar sustain waveform with multiple light output with appropriate temporal sequence on X and Y electrode;
FIG. 25 is a schematic for another mode of bi-polar sustain waveform with multiple light output with appropriate temporal sequence on X and Y electrode;
FIG. 26 is a schematic for alternate mode of bi-polar sustain waveform with multiple light output with appropriate temporal sequence on X and Y electrode;
FIG. 27 is a schematic for alternate mode of bi-polar sustain waveform with multiple light output with application of additional floating voltage waveform of lower amplitude during ON time.
FIG. 28 is a schematic for alternate mode of bi-polar sustain waveform with multiple light output with application of additional floating voltage waveform of lower amplitude during ON time, with appropriate sequential arrangement leading to formation of sine like waveform.

DETAILED DESCRIPTION OF INVENTION FOR THE PREFERRED EMBODIMENTS WITH REFERENCE TO DRAWINGS
In the following detailed descriptions, various exemplary embodiments of the invention has been shown and described, simply to illustrate a best mode contemplated by inventors of carrying out the invention. As will be realized, the invention is capable of modification in various obvious respects, all without departing from the invention. Accordingly drawings and descriptions are to be regarded as illustrative in nature, and not restrictive.
In some figures, some parts not related to description have been omitted for the better understanding of the present invention, and through out the specification same reference numeral is assigned to the same parts. However the numerals related to the temporal sequence of waveform in FIG. 24 to FIG. 28 are same and denoted with alpha-numeral sequence as Tl, T2, T3 etc, and they are different from the temporal sequence numeral of the waveforms shown in FIG. 2, FIG.4 and FIG. 23 and denoted with alpha-numeral sequence as tl, t2, t3 etc.. Also the temporal sequence numeral of FIG. 4 and FIG. 23 are same. The term "a part is coupled to another one" comprise the case where the two parts are indirectly connected via, for example, a third element as well as the case where the two parts are directly connected together.
Hereinafter, the ground voltage (GND) is referred as 0 V and all the voltages are measured with respect to GND. When a terminal of the capacitor forming discharge cell connected to negative or positive terminal of voltage source through switches, time taken to attain the maximum applied voltage is referred as rise-time, time for which voltage is maximum voltage is maintained is referred as ON time, time required to fall from applied voltage to lower voltage is referred as fall-time and time for which GND voltage is applied to the terminal of the capacitor forming discharge cell is referred as OFF time.
Hereinafter, a description will be given for the method and apparatus for driving an exemplary embodiment of plasma display panel (PDP) for enhanced brightness and low discharge current according to this invention with reference to accompanying drawings.
First reference will be made to FIG.5 to describe a schematic structure of an exemplary PDP according to this invention .The PDP according to this exemplary embodiment of this invention comprises as shown in FIG.5, a scan and sustain driver 100, a controller 200, a address driver 300, a plasma display panel 400.
The plasma panel 400 comprises a plurality of address electrodes Al to Am arranged in columns and a plurality of scan electrodes ( herein after referred to as "Y electrodes")Y 1 to Yn and sustain electrodes(herein after referred to as "X electrodes")Xl to Xn alternately arranged in rows.
The address driver 300 receives an address drive control signal from the controller 200, and applies a display data signal for section of discharge cells to be displayed to the individual address electrodes. The scan and sustain driver 100 receives a sustain discharge signal from

the controller 200 and applies a sustain discharge pulse alternately to the X and Y electrodes. The input sustain discharge pulse causes a sustain discharge on the selected discharge cells.
The controller 200 receives an external video signal, generates the address drive control signal and the sustain discharge signal, and applies the address drive control signal and the sustain discharge signal to the address driver 300 and the scan/sustain driver 100, respectively.
Below is a description of a driving method of the driver circuit according to the exemplary embodiments of the invention.
FIG.l illustrates an apparatus for bipolar driving circuit .In the F1G.1 the switches SI 1,S22,S33 and S44 forms an H-bridge of which the switches S3 3 and S22 are connected to the X electrode of the plasma display panel capacitor (hereinafter referred to as Cp) and the switches SI 1 and S44 are connected to the Y electrode of the Plasma display panel Capacitance (Cp).The switches S33 and 57/ are coupled to the Voltage source VI and to the ground (GND) through the switches S3 and S4 respectively. The switches S22 and S44 are coupled to voltage source V2 and to the GND through the switches S6 and S5 respectively.
FIG.2 illustrates the timing sequence for driving the bipolar driving circuit for ultra short sustain pulses according to this exemplary embodiment of this invention. From t/ to t4 voltage VI is applied to the Y electrode by the switching the switches S3 and S11 and X electrode is connected to the ground from tl to t2 through the switches S22 and S5. From t2 to t3 Voltage V2 is applied to the X electrode with the switches S22 and S6 such that V1-V2 equals to Sustain Voltage of Plasma Display Panel (herein after referred to as an Vs). The apparatus in FIG .1 is for application of ultra short bipolar sustain pulse with Vl = + Vs/2 and V2=-Vs/2. But the power sources VI and V2 can swing in magnitude from 0V to Vs such that VJ-V2 =Vs which equals to Sustain Voltage of Plasma Display Panel. According to the exemplary embodiment of the present invention an ultra short sustain pulse is obtained by varying ON time of the switches S5 and S6 i.e., by varying the time (t3-t2) by which the gain in energy of electrons is marginally affected and the gain in energy of ions is considerably affected due to lower mobility of ions. Hence the Xe and Ne ions gain much lower energy reducing the total ion current and hence reducing the discharge power for same or higher brightness.
From time (3 to t4 X electrode is connected to the ground through the switches S22 and S5. After the time t4 the Y electrode is connected to the ground through the switch SI I and S4 and in between the time t4 to t5 the switches SI 1 and S22, are turned off and the switches S33 and S44 are turned on .From t5 to t8 the Y electrode is connected to the voltage source V2 by the switches S44 and S5, the X electrode is connected to the ground from t5 to t6 through the switches S33 .From time t6 to t7 the X-electrode is connected to the power source VI through the switches S33 and S4 and the time (tl-t6) can be varied by varying the on time of the switches S3 and S4 for applying the ultra short bipolar pulses.
FIG.3 illustrates an apparatus for ultra short bipolar sustain driving circuit with the energy recovery circuit .Further the FIG.3 can be divided into three sections as (11, 22, 33). The sections 11 and 33 comprise of the energy recovery and the section 22 consist of the power sources VI and V2 coupled to the panel capacitance Cp through the H bridge network.
The switches S3,S4,S11,S22,S33,S44, S5,S6 are included in FIG.l and the switches S1,S2,S7 and S8 corresponding to the sections 11 and 33 of FIG.4 are shown as an simple switches but they can be MOSFETS , IGBTS or any other semiconductor devices which serves for performing the same functions as that of the switches to generate the ultra short bipolar sustain waveform according to the exemplary embodiment of the present invention.
FIG.4 illustrates the ultra short bipolar waveform applied to the X and Y electrodes with the temporal sequence applied to drive the driving circuit of FIG .3, to generate the ultra short bipolar waveform.
FIGS.6 to20 are the illustrations showing the current paths of the driver circuit according to the exemplary embodiment of the apparatus FIG.3 in accordance with the temporal sequence of the FIG.4
Reference will be made from FIG .6 to FIG .20 to describe the operation of driver circuit of FIG.3 to generate an ultra short bipolar sustain with reference to the temporal sequence in FIG.4 .The description of the driver circuit FIG.3 with reference to the temporal sequence is divided into two modes for the better description for the operation of FIG.3 to generate the ultra short bipolar sustain pulse. From the time tl to t8 it is considered as Mode 1 and Mode 2 is considered from t9 to tl6.
Mode 1
Reference will be made to FIGS. 6 to FIGS. 12 to describe the operation of Mode 1.
Before the start of the Mode 1 from tO to tl it is assumed that both the X electrodes and Y electrodes of the panel capacitance Cp is coupled to the ground.
From tl to t2 switches Sll, S22 of the H- bridge in section 22 of FIG.3.These are turned on to connect the Y electrode to either the power source VI or to ground and X electrode to power source V2 or to ground. Also from tl to t2 switches SI and S5 are closed such that an current path is formed between the energy recovery capacitor Cy, (herein after referred to as Cy) LI and the Cp which forms an LC resonant circuit to raise the panel capacitance voltage to the VI as given in FIG .6.The ramp time from // to t2 can be varied. At time t =tl the switch S3 is turned on to clamp the Y electrode of Cp to the voltage source VI till t=t7.
From time tl to t3 the X electrode of the panel capacitor is clamped to ground through the switches S5 and S22 and the Y electrode of the panel capacitor is clamped to the voltage VI .The path for the flow of the current through the Cp is shown in the FIG.7 .At time t=t3 the switch S2 is turned off and the switch S7 is closed to form an LC resonant circuit with L2 and panel capacitor Cp to raise the voltage of the panel capacitor to Voltage V2 from t3 to

t4 as shown in the FIG.8 .The voltage ramp rate on the X side i.e. the time difference tS-t4 can be varied. At t=t4 the switch S6 is turned on and the X electrode of the panel is clamped to the X voltage V2 till t5 as shown in FIG9 .At t=t 5 the switch S8 is turned on ramp down the panel capacitance voltage through the LC resonant circuit formed between the Panel capacitor Cp and the inductor L2, the current path for the LC resonant circuit is shown in FIG. 10. At t= t6 the switch S5 is turned on to clamp the X electrode voltage to ground.
The time (t6- t3) can be varied by varying the times (t4-t3), (t5-t4) and (t6-t5) each independently such that the time (t6- t3) can be varied to obtain the desired duration for the application of the ultra short sustain bipolar pulse in accordance with exemplary embodiments of the present invention .
From time t6 to t7 the X electrode is clamped to the ground voltage and the Y electrode is clamped to the voltage source VI and current flow through the panel capacitor as shown in the FlG.7.At t=t7 the switch S2 is turned on to form an LC resonant circuit between the panel capacitor Cp and the L1 so as to ramp down the voltage of the Y electrode to ground till time t=t18.From t7 to t8 the current flows through the panel capacitor is shown in the FIG. 11 .At t-t8 the switch S4 is turned on and the Y electrode is also clamped to the ground.
Mode 2
Reference will be made from FIGS. 14 to 20 to describe the operation of Mode 2.
Before the entering into the Mode 2 the switches 57/and S22 of the H Bridge which are connected to the Y electrode and X electrode turned on in Mode 1 are turned off and the switches S33 and S44 are turned on to form a current path for the panel as shown in FIG. 13
From t9 to tlO the switch S7 is turned on in order to raise the Y electrode voltage of panel capacitor to V2 through the LC resonant circuit formed by L2 and panel capacitor Cp, and the X electrode is connected to the ground through the switch S33 and S4 .The current path during the period t9 to tlO to raise the Y electrode panel voltage through the LC resonant network is shown in FIG. 14. At t=tl0 the switch S6 is turned on to clamp the Y electrode to voltage V2 till t=tl5. From \9 to til the X electrode is connected ground through the switch S4.The current path through the panel capacitor Cp from tlO to til is shown in the FIG. 15.The time (t9-tl0) to raise the Y electrode voltage of panel capacitor Cp to V2 can be varied accordingly as time (tl-t2) in Mode 1 .And the X electrode is coupled to ground from t9 to til through the switch S4
At til the switch S4 is turned off and the switch SI is turned on till tl2 to raise X electrode voltage of panel capacitor Cp to voltage VI through the LC resonant circuit formed by the LI and panel capacitor Cp. The current path for the capacitor during the period til to tl2 is given in FIG.16.The voltage rise time on the X side i.e. the time difference tl2-tl 1 can be varied .At t=tl2 the switch S3 is turned on and the X electrode of the panel is clamped to the voltage VI till t!3 as shown in FIG17.At t=t 13 the switch S2 is turned on and ramp down the panel capacitance voltage to ground through the LC resonant circuit formed between the Panel capacitor Cp and the inductor LI, the current path for the resonant circuit is shown in FIG. 18.At t= tl4 the switch S4 is turned on to clamp the X electrode voltage to ground .

The time (tl4- t11) can be varied by varying the times (tl2-tll), (tl3-tl2) and (tl4-tl3) each independently such that the time (tl4- t11) can be varied to obtain the desired duration for the application of the ultra short sustain bipolar pulse in accordance with exemplary embodiments of the present invention .
From time tl4 to tl5 the X electrode is clamped to the ground voltage and the Y electrode is clamped to the voltage source V2 and current flows through the panel capacitor as shown in the FIG. 19.At t=tl5 the switch S8 is turned on to form an LC resonant circuit between the panel capacitor Cp and the L2 so as to ramp down the voltage of the Y electrode to ground till time t=t 16.From tl5 to tl6 the current flows through the panel capacitor is shown in the FIG.20 .At t=tl6 the switch S6 is turned on and the Y electrode is also clamped to the ground.
Subsequently, the Model and Mode2 are repeated to generate Voltages on Y and X electrodes that swinging between the X and Y electrodes at a sustain discharge voltage of the panel Vs. The apparatus in FIG .3 is for applying the ultra short bipolar sustain pulse with Vl = + Vs/2 and V2=-Vs/2.But the power sources VI and V2 can swing in magnitude from 0 to Vs such that V1-V2 =Vs, i.e. equal to sustain voltage of Plasma Display Panel.
FIG. 21 is an apparatus to drive the Plasma display panel with ultra short bipolar sustain pulse waveform. This apparatus is used swing the voltage between the X and Y electrodes through the power sources VI,-VI, V2 and -V2 in magnitude from 0 to Vs such that (Vl-(-V2)) =Vs, (V2-(-Vl)) =Vs. Vs is the sustain voltage of panel capacitor. The temporal sequence to obtain the ultra short bipolar sustain waveform from apparatus of FIG.21 remains the same as in FIG.4 which is applied to FIG.3 with Vl = + Vs/2 and V2=-Vs/2, except that in the Mode 2 of the temporal sequence the switches S3a and S6 are the switched instead of S3 and S6 with same temporal sequence as in FIG .4 by keeping the S3 and S6 turned off during this Mode.
FIG.21a is an apparatus to drive the plasma display panel with ultra short bipolar sustain pulse waveform to generate multiple light output. The apparatus is used apply the voltage VI to first terminal of the panel capacitor from the power source VI by switch S3, and the second terminal is applied with the voltage -V2 for a predetermined time through the switch S6a .Subsequently the switch S6a is tuned off and one of the switches in parallel to
the S6a i.e. S6b,...S6n are turned on to apply the different voltages i.e. -V3,-V4, -Vn
according to the predetermined temporal sequence such that {(Vl-(-V2)),(Vl-(-V3) (VI-
(-Vn) = Vs} where Vs is the sustain voltage of the panel capacitor to obtain the multiple light outputs . In the subsequent sustain period the switch S3 is turned off and the switch S6 is tuned on to couple the first terminal of panel capacitor to power source -VI and the second terminal of panel capacitor is coupled power source V2 for a predetermined time through the switch S3a .Subsequently the switch S3a is tuned off and one of the switches in parallel
to the S3a i.e.S3b,...S3n are turned on to apply different voltages i.e. V3.V4, Vn
according to the predetermined temporal sequence such that {(V2-(-Vl)),(V3-(-Vl) (Vn-
(-Vl) = Vs}where Vs is the sustain voltage of the panel capacitor, to obtain the multiple light
outputs. The rate of raise of the voltages VI ,-V2,-V3, -Vn and -V1,V2,V3, Vn

can be controlled in similar manner as illustrated in the exemplary embodiments of the FIG
4 with Model and Mode2.
FIG. 22a illustrates the conventional uni-polar sustain waveform for the electrode arrangement for AC PDP illustrated in FIG. 5. A positive voltage equal to sustain voltage Vs of the structure is applied alternatively on X and Y electrodes. The frequency of applied sustain waveform is higher than 1 kHz. The discharge emits VUV for initial few hundred nano-seconds (e.g. 500 ns), during rest of the period of the sustain pulse VUV emissions is significantly low. Thus, during rest of the period of the sustain pulse charges accelerate towards electrodes biased with opposite voltage. For example, in the first half cycle of the sustain pulse, for sustain voltage applied on Y electrodes, the electrons rush towards Y electrode, Y being anode, and ions rush towards X electrodes, X electrodes being cathode. On other hand for next half cycle of the sustain pulse, sustain voltage applied on X electrodes, the electrons rush towards X electrode, X being anode, and ions rush towards Y electrodes, Y electrode being cathode. This process is repeated for each cycle. These electrons and ions constitute sustain discharge current and consequently account for total discharge power.
FIG. 22b illustrates the conventional bipolar sustain waveform for the electrode arrangement for AC PDP illustrated in FIG. 5. The sustain voltage Vs required for sustaining the discharge for given structure, is achieved by applying different combination of voltages on X and Y electrodes, with opposite polarity. For example, the sustain voltage Vs between X and Y electrodes could be attained either by application of voltage + Vs/2 on X electrodes and -Vs/2 on Y electrodes or by application of voltage -Vs/2 on X electrodes and +Vs/2 on
Y electrodes. After each half cycle of the sustain pulse, polarity of the applied sustain
voltage is reversed. Also for the bipolar sustain waveform, VUV emission from discharge
lasts initial few hundred nano-seconds (e.g. 500 ns), during rest of the period of the sustain
pulse VUV emissions is significantly low. Thus, during the remaining period of the applied
sustain pulse charges accelerate towards electrodes biased with opposite polarity voltage.
For example, for the first half cycle + Vs/2 is applied on Y electrodes, the electrons rush
towards Y electrode, Y being anode, and ions rush towards X electrodes, X electrodes being
cathode with biased voltage -Vs/2. On other hand, for next half cycle of sustain pulse, +Vs/2
is applied on X electrodes, the electrons rush towards X electrode, X being anode, and ions
rush towards Y electrodes, Y electrode being cathode with biased voltage -Vs/2. These
electrons and ions constitute sustain discharge current and consequently account for total
discharge power. The discharge power dissipation is same for uni-polar and bipolar sustain
waveforms, since the energy distributed to ions and electrons is independent of polarity and
depend on applied voltage difference only.
FIG. 23 illustrates embodiment of the present invention with temporal sequence for the application of voltage VI on Y electrodes and voltage V2 on X electrodes, to obtain voltage difference equal to sustain voltage Vs, required for sustaining the discharge, between X and
Y electrodes. As per embodied invention disclosed in FIGS. 4-21; the voltages of opposite
polarities are applied on X and Y electrode in predetermined temporal sequences for
sustaining the discharge. At time to, both the X and Y electrodes are at 0 V. Where, to
represent initiation time for each cycle of the sustain waveform. At time tl voltage is
applied on Y electrodes, it rises to maximum value +V1 by time t2. This voltage remains

fixed at + V1 upto time t7. Voltage on Y electrode is begins to fall at t7 and reduces to 0 V by time t8. 0 V is maintained on Y electrodes up to time t9. At time t9, voltage -VI is applied on Y electrodes and peak value -VI is attained by time tlO. Voltage -VI is maintained on Y electrodes up to time tl5. Voltage on Y electrode begins to rise at tl5 and reduces to 0 V by time tl6.
On other hand, the voltage is applied on X electrodes at time t3 with polarity opposite to that applied on Y electrodes; it rises to maximum negative value -V2 by time t4. The X electrode maintained at voltage -V2 up to time t5 after that its voltage is raised to OV. OV on X electrode is attained by time t6. The electrode X is maintained on OV from time t6 to time til. Subsequently the voltage on the X electrode is raised from OV to +V2 from time tl 1 and peak value is achieved by time tl2. Voltage +V2 is maintained on X electrode from time tl2 to time tl3. After time tl3, the voltage is reduced to OV by the time tl4. 0 V is maintained on X electrode till time tl6. Temporal sequence of application of voltages on X and Y electrodes repeats itself at tl6 onwards i.e. tl6 is same as to. The voltages VI and V2 can take any value from OV to Vs. The combination of these voltages on X and Y electrodes applied to attain voltage difference of OV to Vs or higher between X and Y electrodes. Thus the effective minimum sustaining voltage, i.e. Vs = Vl-(-V2) = Vl + V2= V2-(-Vl) = V2+V1, between X and Y electrodes is applied only for duration, say ts = (t5-t4) = (tl3-12). While, the VUV light emission lasts only for duration tL = (t5-t3) = (t 13-11). Moreover, when the voltage between X and Y electrodes is peaked to sustain voltage Vs, during which the VUV photons are emitted. For rest of the time, when the voltage between the electrodes is Vs -V2, the light is not emitted. Thus, in case of embodied invention, ions and electrons experience voltage Vs for shorter duration and for remaining period voltage between electrodes is less than the sustain voltage Vs. In comparison to conventional uni-polar and bipolar waveform, the gain in energy of electrons affected and the gain in energy of ions is considerably affected due to lower mobility of ions. Further, the Xe and Ne ions gain much lower energy than conventional waveforms reducing the total ion current and hence reducing the discharge power for same or higher brightness.
According to this invention the rise time of voltage VI (for both polarities) on Y electrodes tvR = (t2- tl) = (tl0-t9) and rise time of voltage V2 on X electrodes txR = (t4-t3) = (tl2-tll), and fall time of VI voltage on Y. electrodes tyF = (t8- (7) = (tl6 - tl5) and fall time of voltage V2 on X electrodes txF = (t6-t5) = (tl3 - tl2) are appropriately adjusted according to magnitude of voltage VI and V2 to minimize the displacement current and hence the capacitive losses.
FIG. 24 illustrates the embodiment of the present invention for generation of at least two light outputs during each half cycle of the sustain wave applied on X and Y electrodes. At time To, both the X and Y electrodes are at OV. Where, T0 represent initiation time for each cycle of the sustain wave. At time Tl voltage Vy is applied on Y electrodes, it rises to maximum value +Fby time T3. The electrodes Y, maintained at voltage V till time T13. After time TJ3, voltage on Y electrodes is reduced to OV by time T15 and maintained on OV till time T17. At time T17 voltage -V is applied on Y electrode and it rises to -V by time T19. The electrode Y is maintained on voltage — V till T29 and then voltage increased to 0 V by time T31.

On other hand X electrode is maintained at OV till T3 and voltage Vx is applied and it attains voltage Vxl at time T4. The X electrode is maintained on voltage Vxl till 75 and is raised to OV by the time T6, The X electrodes are maintained on OV till T9 and further, voltage Vx2 is applied and they attain voltage Vx2 by time 770. After time 777 the X electrodes voltage is raised to OV by time T12 and kept on same voltage till T19. Further, on X electrodes voltage Vx3 is applied at T19 and X electrode attains Vx3 at time T20. After time T21 the voltage is reduced and reaches to OV by T22 and is maintained on same voltage till 725. Further the voltage Vx4 is applied on X electrode and it attains voltage Vx4 at time T26. The voltage on X electrodes is reduced to OV at T28 and is maintained on the same potential till T31. Temporal sequence of application of voltages on X and Y electrodes repeats itself after T31 onwards i.e. T16 is same as To.
According to this invention the rise time for the voltages on Y (for both polarities) electrodes, i.e., TyR = (T3- Tl) = (T19-T17) and rise time for the voltage on X electrodes i.e., TXRI = (T4-T3) = (T20-T19) for Vxl and Vx3 respectively, and the rise time for the voltage Vx2 and Vx4 are TxR2 = (T10-T9) = (T26-T25) respectively. The fall time for the voltages on Y electrodes (for both polarities) 7vf = (T15- T13) = (Til - T29) and fall time for the voltages Vxl, Vx3 and on X electrodes are TxF! = (T6-T5) = (T2 - T21) respectively, and fall time for the voltages Vx2 and Vx4 are Txi.2 = (T12-Til) = (T28-T27) respectively, and these timings are appropriately adjusted according to magnitude of voltages on X and Y electrodes to minimize the sustain current and capacitive losses and improve the brightness.
FIG. 25 illustrates the embodiment of the present invention another mode of sustain waveform for generate at least two light outputs during each half cycle of the sustain wave applied on X and Y electrodes. At time T0, both the X and Y electrodes are at 0 V. Where, To represent initiation time for each cycle of the sustain wave. At time Tl voltage +Vy is applied on Y electrodes, it rises to maximum value +V by time T3. The electrodes Y, maintained at voltage V till time T13. After time T13, voltage on Y electrodes reduces to OV by the time T15 and maintained on OV till time Tl 7. At time Tl 7 voltage -V is applied on Y electrode and it rises to—V by time T19. The electrode Y maintained on voltage -V till T29 and then voltage increased to 0 V by time T31.
On other hand X electrode is maintained at 0 V till T3 and voltage Vx is applied and it attains voltage Vxl at time T4. The X electrode is maintained on voltage Vxl till 75 and is raised to voltage Vx2 by the time T7. The X electrodes are maintained on Vx2 till T8, and after that the voltage Vx3 is applied and they attain the voltage Vx3 by time 770. After time 777 X electrodes voltage is to OV by time T12 and kept on same voltage till T19. Further, on X electrodes the voltage Vx4 is applied and they attain the voltage Vx4 by time T20. After time T21 voltage on X electrodes is reduced to voltage Vx5 by time T23 and maintained on same voltage till T24. The voltage Vx6 is applied and they attain the voltage Vx6 by time T26 and maintained on the same voltage till T27. From the time T27 the voltage on X electrodes is reduced to 0 V by time T28 and maintained on same potential till T31. Temporal sequence of application of voltages on X and Y electrodes repeats itself after T31 onwards i.e. T16 is same as To.
According to this invention the rise time for the voltages on Y (for both polarities) electrodes, i.e., TyR = (T3- Tl) = (T19-T17). The rise time for the voltage on X electrodes

i.e., TXRI = (T4-T3) = (T20-T19) for -Vxl and +Vx4 respectively, and the rise time for the voltage Vx3 and Vx6 are TxR2 = (T10-T9) = (T26-T25) respectively, the rise time of voltages Vx2 and Vx5 are (T7-T5) and (T23-T21) respectively. The fall time for the voltages on Y electrodes 7> = (775- T13) = (T31 - T29) and fall time for the voltages Vxl, Vx3 and on X electrodes are TxF! = (T6-T5) = (T2 - T21) respectively, and fall time for the voltages Vx2 and Vx4 are TXFI = (T12-T11) = (T28-T27) respectively, and these timings are appropriately adjusted according to magnitude of voltages on X and Y electrodes to minimize the sustain current and capacitive losses and improve the brightness. In other words, the application of voltages Vxl, Vx2, Vx3, Vx4, Vx5 and Vx6 on X electrodes and application of voltages Vy (of both polarities) on Y electrodes in pre-determined temporal sequence are portrayed in this figure. Moreover, this figure describes application of modulated sustain waveform on sustain electrodes.
FIG. 26 illustrates the embodiment of the present invention and yet another mode of sustain wave for generation of at least two light outputs during each half cycle of the sustain wave applied on X and Y electrodes. At time to, both the X and Y electrodes are at 0 V. Where, To represent initiation time for each cycle of the sustain wave. At time Tl voltage -V is applied on X electrodes, it rises to maximum value - V by time T3. The electrodes X, maintained at voltage V till time T13. After time 773, voltage on X electrodes reduced to OV by the time T15 and maintained on 0 V till time T17. At time Tl 7 voltage +Fis applied on X electrodes and it rises to -V by time T19. The electrode Y maintained on voltage — K till T29 and then voltage increased to 0 V by time T31.
On other hand Y electrode is maintained at 0 V till T3 and voltage Vy is applied. The Y electrodes attain voltage Vyl by time T4 and they are maintained at voltage Vyl till T5. And after that voltage on Y electrodes is reduced to Vy2 by the time T7. The Y electrodes are maintained on voltage Vy2 till T8, and after which the voltage Vy3 is applied and they attains the voltage Vy3 by time T10. After time Tl 1 the voltage on Y electrodes is reduced to OV by time T12 and kept on same voltage till T19. Further, on Y electrodes the voltage Vy4 is applied and they attain the voltage Vy4 by time T20. After time T21, Y electrodes are applied with voltage Vy5 and they attain the voltage Vy5 by time T23, and they are maintained on same voltage till T24. Further the voltage Vy6 is applied on Y electrodes at time T24 and they attain voltage Vx6 by time T26. The voltage on Y electrodes is further reduced to 0 V by time T28 and maintained on same potential till T31. Temporal sequence of application of voltages on X and Y electrodes repeats itself after T31 onwards i.e. T16 is same as To.
According to this invention the rise time for the voltages on X (for both polarities) electrodes, i.e., TxR = (T3- Tl) = (T19-T17). The rise time for the voltage on Y electrodes i.e., TyM = (T4-T3) = (T20-T19) for Vyl and Vy4 respectively, and the rise time for the voltage Vy3 and Vy6 are TvR2 = (T10-T9) = (T26-T25) respectively, the rise time of voltages Vy2 and Vy5 are (T7-T5) and (T23-T21) respectively. The fall time for the voltages on Y electrodes TxF = (T15- T13) = (T31 - T29) and fall time for the voltages Vyl, Vy3 and on X electrodes are TyF/ = (T6-T5) = (T2 - T21) respectively, and fall time for the voltages Vy2 and Vy4 are TyF2 = (T12-T11) = (T28-T27) respectively, and these timings are appropriately adjusted according to magnitude of voltages on X and Y electrodes to minimize the sustain current and capacitive losses and improve the brightness. In other words, the application of

voltages Vyl, Vy2, Vy3, Vy4, Vy5 and Vy6 on Y electrodes and application of voltages Vx (of both polarities) on X electrodes in pre-determined temporal sequence are portrayed in this figure. Moreover, this figure describes application of modulated sustain waveform on sustain electrodes.
FIG. 27 illustrates the embodiment of the present invention and yet another mode of sustain waveform. With reference FIG. 26, a modulated waveform is applied to the X electrode, i.e. by superimposing small amplitude voltages during ON time of the applied sustain pulse.
FIG. 28 illustrates the embodiment of the present invention and yet another mode of sustain waveform. With reference FIG. 26 and FIG. 27, a sine wave like voltage pulses is applied on Y electrodes.
In the embodiment of present invention, voltage sources on X and Y electrodes are interchanged to get the same desired effect. Moreover, appropriate temporal sequence arrangement of applied voltages result in square-waveform, triangular waveform, sine waveform etc. While this invention has been described in connection with what is presently considered to be most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements possible with in the spirit and scope of the appended claims.

CLAIMS:
An apparatus and a method for driving a plasma display panel, comprising 1. A method for driving plasma display panels with reduced discharge current along with reduced capacitive losses by application of sustain voltages of opposite polarity, on first and second electrodes in predefined temporal sequence, pre-determined rate of voltage rise, predetermined rise-time, pre-determined ON-time, pre-determined OFF time such that sustain voltage between panel capacitor formed between first and second electrodes is attained in at least one step. The method for driving plasma display panel consists of:
a. Coupling a positive polarity terminal of a floating voltage source for supplying a
voltage to first terminal of panel capacitor; and coupling a negative polarity terminal
of the another floating voltage source for supplying a voltage to second terminal of
panel capacitor between sustain electrodes; with a predetermined and specific
temporal sequence.
b. Coupling a positive polarity terminal of a floating voltage source for supplying a
voltage to first terminal of panel capacitor via circuit controlling rate of voltage rise
of aforesaid voltage; and coupling a negative polarity terminal of the another floating
voltage source for supplying a voltage to second terminal of panel capacitor between
sustain electrodes; via circuit controlling rate of voltage rise of aforesaid voltage
with a predetermined rate of voltage rise of applied voltages.
c.Coupling a positive polarity terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor for a predetermined ON time of aforesaid voltage and coupling a negative polarity terminal of the another floating voltage source for supplying a voltage to second terminal of panel capacitor, between sustain electrodes, for a predetermined ON time of aforesaid voltages.
d.Coupling first terminal of panel capacitor to the GND via circuit controlling fall time of aforesaid voltage and coupling second terminal of panel capacitor to the GND, between sustain electrodes, via circuit controlling fall time of aforesaid voltage with a predetermined fall rate of voltages.
e. Coupling first terminal of panel capacitor to the GND via a circuit controlling fall
time of aforesaid voltage with a predetermined fall rate of voltages and coupling
second terminal of panel capacitor to GND, between sustain electrodes.
f. Coupling first terminal of panel capacitor to the GND and coupling second terminal
of panel capacitor, to the GND via circuit controlling fall time of aforesaid voltage,
between sustain electrodes, with a predetermined fall rate.
g.Coupling first terminal of panel capacitor to the GND and coupling to the GND to second terminal of the panel capacitor, between sustain electrodes, for a predetermined time.
h.Coupling the negative terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor; and coupling a positive polarity terminal of the another floating voltage source for supplying a voltage to second terminal of panel capacitor between sustain electrodes; in predetermined and specific temporal sequence.
i. Coupling the negative terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor via circuit controlling rise time of aforesaid

voltage; and coupling a positive polarity terminal of the another floating voltage source for supplying a voltage to second terminal of panel capacitor between sustain electrodes; via circuit controlling rise time of aforesaid voltage with a predetermined rise time of voltages.
j. Coupling the negative terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor via circuit controlling rise time of aforesaid voltage; and coupling a positive polarity terminal of the another floating voltage source for supplying a voltage to second terminal of panel capacitor between sustain electrodes.
k.Coupling the negative terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor; and coupling a positive polarity terminal of the another floating voltage source for supplying a voltage to second terminal of panel capacitor between sustain electrodes; via circuit controlling rise time of aforesaid voltage with a predetermined rise time of the voltage.
1. Coupling the negative terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor for a predetermined ON time of aforesaid voltage and coupling the positive polarity terminal of another floating voltage source for supplying a voltage to second terminal of panel capacitor, between sustain electrodes, for predetermined ON time of aforesaid voltages.
m. Coupling the positive terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor for a predetermined ON time of aforesaid voltage and coupling the negative polarity terminal of another floating voltage source for supplying a voltage to second terminal of panel capacitor, between sustain electrodes, for predetermined ON time of aforesaid voltages.
n.Coupling second terminal of panel capacitor to the GND via circuit controlling fall time of aforesaid voltage and coupling first terminal of panel capacitor to GND, between sustain electrodes, via circuit controlling fall time of aforesaid voltages with a predetermined fall rate of voltages.
o.Coupling second terminal of panel capacitor to the GND via circuit controlling fall time of aforesaid voltage with a predetermined fall rate of voltages, and coupling first terminal of panel capacitor to GND, between sustain electrode.
p.Coupling second terminal of panel capacitor to the GND and coupling first terminal of panel capacitor to the GND, between sustain electrodes, via circuit controlling fall time of aforesaid voltage with predetermined fall rate.
q. Coupling second terminal of panel capacitor to the GND and coupling first terminal of the panel capacitor to the GND, between sustain electrodes, for a predetermined time.
2. A method for driving a plasma display panel with reduced discharge current and obtaining more than one light output, i.e. multiple light output in each half cycle of sustain pulse by applying sustain voltages on first and second electrodes in pre-determined temporal sequence and opposite polarity to a panel capacitor formed between first and second electrodes:
a. Coupling a positive polarity terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor via circuit controlling rise time/fall time of aforesaid voltage with a predetermined ON time; and coupling a negative polarity terminal of the another floating voltage source for supplying a voltage to second

terminal of panel capacitor between sustain electrodes via circuit controlling rise time/fall time or without controlling rise time/fall time of aforesaid voltage with predetermined appropriate ON time sufficiently less than the ON time of supplied voltage on first terminal, such that, on second terminal of panel capacitor coupled to negative polarity of another source via circuit controlling rise time/ fall time of aforesaid voltage with pre-determined ON time could be applied at least once or more.
b.Coupling a negative polarity terminal of a floating voltage source for supplying a voltage to first terminal of panel capacitor via circuit controlling rise time/fall time of aforesaid voltage with a predetermined ON time; and coupling a positive polarity terminal of the another floating voltage source for supplying a voltage to second terminal of panel capacitor between sustain electrodes via circuit controlling rise time/fall time or without controlling rise time/fall time of aforesaid voltage with predetermined appropriate ON time sufficiently less than the ON time of supplied voltage on first terminal, such that, on second terminal of panel capacitor coupled to positive polarity of another source via circuit controlling rise time/ fall time or without controlling rise time/ fall time of aforesaid voltage with pre-determined ON time could be applied at least once or more.
c.Coupling a positive terminal of a floating voltage source for supplying a voltage to second terminal of panel capacitor via circuit controlling rise time/fall time of aforesaid voltage with a predetermined ON time; and coupling a negative polarity terminal of the another floating voltage source for supplying a voltage to first terminal of panel capacitor between sustain electrodes via circuit controlling rise time/fall time or without controlling rise time/fall time of aforesaid voltage with predetermined appropriate ON time sufficiently less than the ON time of supplied voltage on second terminal, such that, on first terminal of panel capacitor coupled to negative polarity of another source via circuit controlling rise time/ fall time of aforesaid voltage with predetermined ON time could be applied at least once or more.
d.Coupling a negative terminal of a floating voltage source for supplying a voltage to second terminal of panel capacitor via circuit controlling rise time/fall time of aforesaid voltage with a predetermined ON time; and coupling a positive polarity terminal of the another floating voltage source for supplying a voltage to first terminal of panel capacitor between sustain electrodes via circuit controlling rise time/fall time or without controlling rise time/fall time of aforesaid voltage with predetermined appropriate ON time sufficiently less than the ON time of supplied voltage on second terminal, such that, on first terminal of panel capacitor coupled to positive polarity of another source via circuit controlling rise time/ fall time or without controlling rise time/ fall time of aforesaid voltage with pre-determined ON time could be applied at least once or more.
3. A method for driving a plasma display panel as claimed in claim 1 and claim 2, wherein brightness is enhanced by application of sustain pulses with appropriate ON time, OFF time, rise time, fall time on first terminal and second terminal of panel capacitor, i.e. first and second electrodes, forming a discharge cell.
4. A method for driving a plasma display panel as claimed in claim 1 and claim 2, wherein current reduced by application of sustain pulses with appropriate ON time, OFF time,rise time, fall time on first terminal and second terminal, i.e. first and second electrodes, of panel capacitor forming a discharge cell.
5. A method for driving a plasma display panel as claimed in claim 1 and claim 2, wherein current by reduced by application of sustain pulses with appropriate ON time, OFF time, rise time, fall time on first terminal and second terminal of panel capacitor, i.e. first and second electrodes, forming a discharge cell, with opposite polarity voltages in appropriate temporal sequence.
6. A method for driving a plasma display panel as claimed in claim 1 and claim 2, wherein brightness enhanced by application of sustain pulses with appropriate ON time, OFF time, rise time, fall time on first terminal and second terminal of panel capacitor, i.e. first and second electrodes, forming a discharge cell, with opposite polarity voltages in appropriate temporal sequence.
7. A method for driving a plasma display panel as claimed claim 1 and claim 2, wherein dielectric losses reduced by application of sustain pulses with appropriate ON time, OFF time, rise time and fall time on first terminal and second terminal of panel capacitor, i.e. first and second electrodes, forming a discharge cell, with opposite polarity voltages in appropriate temporal sequence.
8. An apparatus for driving a plasma display panel, comprising
a.Driving circuit comprising switches i.e. a first, a second, a third and a fourth of which the first and the second switches are coupled to first terminal of panel capacitor and the third and the fourth to the second terminal of panel capacitor.
b.The driving circuit also comprises a fifth and a sixth switches. The fifth switch is coupled to the contact of first and third switches and to the first power source for supplying the voltage for either terminals of the panel capacitor, also the sixth switch is coupled to the contact of second and fourth switches and to the third power source for supplying either terminals of panel capacitor.
c.The driving circuit also comprises of seventh and an eighth switch. The seventh switch is coupled to the terminal of second and fourth switches and to the third power source for supplying either terminals of panel capacitor, also eighth switch is coupled to the contact of second and fourth switches and to the second power source for supplying either terminals of panel capacitor.
9. The apparatus for driving plasma display panel according to claim 8 wherein further
comprises
a. One or more switches in parallel to the fifth switch, wherein the switches in parallel to fifth switch are coupled between the contact of first and third switches and to the one or more different power source for supplying different voltages to either terminals of panel capacitor.
b.At least one switches in parallel to the fifth switch, wherein the switches in parallel to fifth switch are coupled between the contact of first and third switches and to the
one or more different power source for supplying different voltages to either terminals of panel capacitor.
c.At least one switch in parallel to the eighth switch in which one or more switches in parallel to eight switches are coupled between the contact of the second and fourth switches and to different power supplies for supplying either terminals of panel capacitor.
The apparatus for driving plasma display panel according to claim 8 further comprises, sections for controlling the rate of voltage applied to the either of the terminals of panel capacitor and to recover the reactive power used in panel.
The apparatus for driving a plasma display panel according to claim 10 wherein the power recovery sections further includes,
a. One or more capacitors of which one terminal of capacitors is coupled to the third power source, the other terminal is coupled to the contact of the switch nine and to the unidirectional switching device.
b.One or more inductors of which one terminal of inductors are couple to the contact of two unidirectional switching devices and the other terminal of inductors are coupled to the contact of first, third, fifth and sixth switches.
An apparatus for driving a plasma display panel which has panel capacitor, according to claim 8 and 10 drive each terminal of panel by alternatively applying both the first and third voltages in a predetermined temporal sequence.
An apparatus for driving a plasma display panel which has panel capacitor ,according to claim 8 and 10 drive each terminal of panel capacitor by applying voltage from one power source to one terminal of the panel capacitor and one or more power sources applying different voltages alternatively in an predetermined temporal sequence.
The apparatus for driving a plasma display panel according to claim 12 and 13, where in fifth switch or one of the switches in parallel to the fifth switch is turned on to couple to first terminal of panel capacitor through the first switch , and the eighth switch or one of the switches in parallel to the eighth switch is turned on for an predetermined time to couple to second terminal of panel capacitor through the fourth switch ,after which the switch which is on is turned off , and another switch in parallel to that of the eighth switch is on to couple to the second terminal of panel capacitor to different power source for supplying different voltage ,and keeping same fifth switch or one of the switches turned on to couple to the first terminal of panel capacitor.
The apparatus for driving a plasma display panel according to claim 12 and 13, where in eighth switch or one of the switches in parallel to the eighth switch is turned on to couple to second terminal of panel capacitor through the second switch , and the fifth switch or one of the switches in parallel to the fifth switch is turned on for a predetermined time to couple to first terminal of panel capacitor through the third switch ,after which the switch which is on is turned off, and another switch in parallel to that of the fifth switch is turned on to couple to the first terminal of panel capacitor to different power source

for supplying different voltage ,and keeping same eighth switch or one of the switches turned on to couple to the first terminal of panel capacitor.
16. An apparatus for driving a plasma display panel according to claim 10 wherein, in the
section for controlling the rate of voltage rise applied to either of the terminals of the
panel capacitor, the ninth switch is turned on to raise the voltage of either terminal of the
panel capacitor in a controlled manner by the path formed with one or more capacitors,
and the ninth switch, and a unidirectional device, and with either of the first or third
switch with either terminal of panel capacitor, by selectively switching on the first or
third switch, in a predetermined temporal sequence.
Also by turning on the tenth switch, the voltage of either terminal of panel capacitor is lowered in a controlled manner by the path formed with either terminal of the panel capacitor, and through first or third switch by selectively switching either of them, to couple either of the terminals of panel capacitor with one or more inductors, and a unidirectional device, and the tenth switch with one or more capacitors.
17. An apparatus for driving a plasma display panel according to claim 10 wherein, in
second section for controlling the rate of voltage rise applied to either of the terminals of
the panel capacitor, the eleventh switch is turned on to raise the voltage of either
terminals of the panel capacitor in a controlled manner by the path formed with one or
more capacitors, and the eleventh switch, and a unidirectional device, and with either of
the first or third switch with either terminal of the panel capacitor, by selectively
switching on the second or fourth switch, in a predetermined temporal sequence .
Also by turning on the twelfth switch, the voltage of either terminal of panel capacitor is lowered in a controlled manner by the path formed with either terminals of the panel capacitor, and through second and fourth switches by selectively switching either them, to couple either of the terminals of panel capacitor with one or more inductors, and a unidirectional device, and the twelfth switch with one or more capacitors.