Claims:1. A method comprising:
generating a bounding volume hierarchy (BVH) comprising hierarchically-arranged BVH nodes based on input primitives, at least one BVH node comprising one or more child nodes;
determining motion values for a quantization grid based on motion values of the one or more child nodes of the at least one BVH node; and
mapping linear bounds of each of the child nodes to the quantization grid.
, Description:BACKGROUND
Field of the Invention
[0002] This invention relates generally to the field of graphics processors. More particularly, the invention relates to an apparatus and method for implementing motion blur with a dynamic quantization grid.

Description of the Related Art
[0003] Path tracing is an existing technique for rendering photorealistic images for special effects in films, animated movies, and professional visualization. Generating these realistic images requires the computation of a physical simulation of light transport in a virtual 3D scene, using ray tracing as a tool for visibility queries. A high performance implementation of these visibility queries requires construction of a 3D hierarchy over the scene primitives (typically triangles) in a preprocessing phase. The hierarchy allows the ray tracing step to quickly determine the closest intersection point between a ray and a primitive (triangle).
[0004] Motion blur is an important feature in photorealistic rendering of animations, where the effect of objects moving in the scene while the camera shutter is open is simulated. Simulating this effect results in an oriented blur of the moving objects, which causes the animation to appear smooth when played back. Rendering motion blur requires randomly sampling the time for each ray path evaluated, and the average over many of these paths provides the desired blur effect. To implement this technique, the underlying ray tracing engine has to be capable of tracing a ray through the scene at an arbitrary time inside the camera shutter interval. This requires an encoding of the motion of the geometric object inside the spatial acceleration structure used for ray tracing.

BRIEF DESCRIPTION OF THE DRAWINGS
[0005] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
[0006] FIG. 1 is a block diagram of an embodiment of a computer system with a processor having one or more processor cores and graphics processors;
[0007] FIG. 2 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;
[0008] FIG. 3 is a block diagram of one embodiment of a graphics processor which may be a discreet graphics processing unit, or may be graphics processor integrated with a plurality of processing cores;
[0009] FIG. 4 is a block diagram of an embodiment of a graphics-processing engine for a graphics processor;
[0010] FIG. 5 is a block diagram of another embodiment of a graphics processor;
[0011] FIGS. 6A-B illustrate examples of execution circuitry and logic;
[0012] FIG. 7 illustrates a graphics processor execution unit instruction format according to an embodiment;
[0013] FIG. 8 is a block diagram of another embodiment of a graphics processor which includes a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline;
[0014] FIG. 9A is a block diagram illustrating a graphics processor command format according to an embodiment;
[0015] FIG. 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment;
[0016] FIG. 10 illustrates exemplary graphics software architecture for a data processing system according to an embodiment;
[0017] FIGS. 11A-B illustrate an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly;
[0018] FIG. 12 illustrates an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment;
[0019] FIGS. 13A-B illustrates an exemplary graphics processor of a system on a chip integrated circuit that may be fabricated using one or more IP cores;
[0020] FIG. 14A-B illustrate exemplary graphics processor architectures;
[0021] FIG. 15 is an illustration of a bounding volume, according to embodiments;
[0022] FIGS. 16A-B illustrate a representation of a bounding volume hierarchy;
[0023] FIG. 17 is an illustration of a ray-box intersection test, according to an embodiment;
[0024] FIG. 18 is a block diagram illustrating an exemplary quantized BVH node according to an embodiment;
[0025] FIG. 19 is a block diagram of a composite floating point data block for use by a quantized BVH node according to a further embodiment;
[0026] FIG. 20 illustrates ray-box intersection using quantized values to define a child bounding box relative to a parent bounding box, according to an embodiment;
[0027] FIG. 21 is a flow diagram of BVH decompression and traversal logic, according to an embodiment;
[0028] FIG. 22 is an illustration of an exemplary two-dimensional shared plane bounding box;
[0029] FIG. 23 is a flow diagram of shared plane BVH logic, according to an embodiment;
[0030] FIG. 24 is a block diagram of a computing device including a graphics processor having bounding volume hierarchy logic, according to an embodiment;
[0031] FIG. 25 illustrates an apparatus or system on which embodiments of the invention may be implemented;
[0032] FIG. 26 illustrates one embodiment of an apparatus for building, compressing and decompressing nodes of a bounding volume hierarchy;
[0033] FIG. 27 one embodiment in which leaf nodes are compressed by replacing pointers with offsets;
[0034] FIG. 28 illustrates code associated with three BVH node types;
[0035] FIG. 29 compares embodiments of the invention with existing implementations with respect to memory consumption (in MB) and total rendering performance (in fps);
[0036] FIG. 30 is used to compare existing implementations with embodiments of the invention with respect to memory consumption (in MB), traversal statistics and total performance;
[0037] FIG. 31 illustrates a naïve extension of quantized bounding boxes to motion blurred triangles;
[0038] FIG. 32 illustrates one embodiment of the invention which uses smaller quantization grids at the start and end times;
[0039] FIG. 33 illustrates one embodiment of an architecture including motion blur processing hardware/logic; and
[0040] FIG. 34 illustrates a method in accordance with one embodiment of the invention.

DETAILED DESCRIPTION
[0041] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.