Claims:1. An apparatus comprising:
trace/debug circuitry and/or logic to implement trace/debug operations on a semiconductor chip to generate trace/debug data; and
compression resource selection circuitry and/or logic to select one or more compression resources of the semiconductor chip to compress the trace/debug data to generate compressed trace/debug data.
, Description:BACKGROUND
Field of the Invention
[0001] This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for data compression such as the compression of debug/trace data implemented, for example, within a system-on-a-chip (SoC) or other type of system or processor.

Description of the Related Art
[0002] Computer architectures are moving from interfacing discrete components on a printed circuit board or through use of other package configurations, to integrating multiple components onto a single integrated chip, which is commonly referred to as a System on a Chip (SoC) architecture. SoCs offer a number of advantages, including denser packaging, higher speed communication between functional components, and lower temperature operation. SoC designs also provide standardization, scalability, modularization, and reusability.