Claims:1. An apparatus comprising:
a package comprising one or more integrated circuit dies, the one or more integrated circuit dies comprising:
a plurality of cores; and
a security controller coupled to the plurality of cores, a first core of the plurality of cores comprising:
a decoder to decode a microcode patching instruction, the microcode patching instruction comprising an operand to be used to identify an address; and
execution circuitry to execute the microcode patching instruction, wherein responsive to the microcode patching instruction, the execution circuitry and/or security controller are to:
retrieve a microcode patch from a location in memory based on the address,
validate the microcode patch,
apply the microcode patch to update or replace microcode associated with the one or more integrated circuit dies, and
transmit the microcode patch to a persistent storage device;
wherein the microcode patch is to be subsequently retrieved from the persistent storage device by one or more external security controllers of one or more external integrated circuit dies, the one or more external security controllers to cause the microcode patch to be applied to update or replace microcode associated with the one or more external integrated circuit dies.
, Description:BACKGROUND
Field of the Invention
[0001] The embodiments of the invention relate generally to the field of computer processors. More particularly, the embodiments relate to an apparatus and method for secure and efficient microcode patching.

Description of the Related Art
[0002] An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term “instruction” generally refers herein to macro-instructions – that is instructions that are provided to the processor for execution – as opposed to micro-instructions or micro-ops – that is the result of a processor’s decoder decoding macro-instructions. The micro-instructions or micro-ops can be configured to instruct an execution unit on the processor to perform operations to implement the logic associated with the macro-instruction.
[0003] The ISA is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale CA implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA may be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used herein to refer to that which is visible to the software/programmer and the manner in which instructions specify registers. Where a distinction is required, the adjective “logical,” “architectural,” or “software visible” will be used to indicate registers/files in the register architecture, while different adjectives will be used to designate registers in a given microarchitecture (e.g., physical register, reorder buffer, retirement register, register pool).

BRIEF DESCRIPTION OF THE DRAWINGS
[0004] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
[0005] FIG. 1 illustrates an example computer system architecture;
[0006] FIG. 2 illustrates a processor comprising a plurality of cores;
[0007] FIG. 3A illustrates a plurality of stages of a processing pipeline;
[0008] FIG. 3B illustrates details of one embodiment of a core;
[0009] FIG. 4 illustrates execution circuitry in accordance with one embodiment;
[0010] FIG. 5 illustrates one embodiment of a register architecture;
[0011] FIG. 6 illustrates one example of an instruction format;
[0012] FIG. 7 illustrates addressing techniques in accordance with one embodiment;
[0013] FIG. 8 illustrates one embodiment of an instruction prefix;
[0014] FIGS. 9A-D illustrate embodiments of how the R, X, and B fields of the prefix are used;
[0015] FIGS. 10A-B illustrate examples of a second instruction prefix;
[0016] FIG. 11 illustrates payload bytes of one embodiment of an instruction prefix;
[0017] FIG. 12 illustrates instruction conversion and binary translation implementations;
[0018] FIG. 13 illustrates a system comprising a plurality of system-on-chip devices and security controllers;
[0019] FIG. 14 illustrates a transaction diagram showing interactions between management software, SoCs, and persistent storage;
[0020] FIG. 15 illustrates a method in accordance with one embodiment of the invention; and
[0021] FIG. 16 illustrates one example of a system architecture.

DETAILED DESCRIPTION
Exemplary Computer Architectures
[0022] Detailed below are describes of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.