Field of the invention
This invention relates to an improved Digital Delay / Phase Lock Loops (DLLs/PLLs) with duty cycle locking mechanism. More specifically it provides an apparatus for enabling duty cycle locking at the rising / falling edge of the clock.
Background of the Invention
PLLs / DLLs are extensively used in large digital chips like SOC's, microprocessors, memories, etc. to cancel the on chip clock amplification and buffering delays, and to improve the I/O timing margins. DLLs are preferred over PLLs as the increasing clock speeds and increasing levels of complexity in digital circuits create a hostile operating environment for the phase alignment circuits.
Analog DLLs have been employed in the past to perform synchronization, which comprise of a delay chain having delay of its elements varied by analog bias voltages supplied by a phase detector. In digital systems such as memories, microprocessors and application specific integrated circuits, these types of DLLs introduce analog design complications in mainly digital design and therefore are avoided.
To overcome the above-mentioned complications, digital DLLs were developed that used a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Although digital DLLs have a much higher jitter than analog DLLs, their ease of implementation in the digital system makes them preferred solution in most digital applications.
The block diagram for a conventional digital DLL is illustrated in Figure 1. It comprises of a DLL/PLL 4 receiving the input or the external clock and is connected to a clock tree 5, the output of which is fed back to the DLL/PLL 4. The problem with a conventional DLL is that the input clock has to pass through long delay chains and other logic. Secondary effects on semiconductor delays and logic devices alter the shape of the input
clock pulse and hence, the duty cycle of the output clock is not the same as that of input clock.
The problem of altered duty cycle in a DLL is illustrated with the help of waveforms shown in Figure 2. It can be observed that output of the prior art DLL DLLOUT has a different duty cycle when compared with the external clock EXTCLK. Similarly, in case of Phase and Frequency locking PLLs, the duty cycle is dependent on the VCO clock. So it is impossible to get the same duty cycle of the output clock as that of the input clock.
This change in duty cycle may not be a problem in chips operating on only one clock edge (falling or rising edge) as the period of the clock remains unaltered and hence one of the PLL/DLL output clock edges can be synchronized with the external clock edge for the chip operation. However, this is a critical problem in high performance digital chips, which perform operations on both falling and rising clock edge. As both edges cannot be synchronized due to alteration in duty cycle, the chip may produce erroneous output because the devices using the external clock (I/O ports etc) may perform an operation before/after an operation is performed on a device using the internal clock (logic blocks, memory etc). For example, in high performance DDR memories, where read and write operation occur at both rising edge and falling edge of the clock having some duty cycle (other than that of 50%), an external clock may result in new input being sampled by I/O port before the memory is able to write the previous data in a memory location. Thus it is necessary to preserve the duty cycle of the input clock as altered duty cycle of the input clock may result in erroneous operation in cases where both clock edges are used for chip operations.
A US patent application number US2003218486 describes a digital DLL for correcting the duty cycle. The digital DLL apparatus for correcting a duty cycle includes, a buffer for producing a clock input signal; a delay line unit for receiving/delaying the clock input signal and outputting the clock input signal; a blend circuit for bypassing the first clock signal or producing a blended clock signal; a delay model unit for compensating a time difference of an external clock and an internal clock and generating a compensate clock
signal; a direct phase detector for generating a first comparison signal; and a phase detector for generating a second comparison signal. The disclosed apparatus corrects the duty error by using the blend circuit and generates an internal clock signal having 50% of the duty cycle.
The main problem with the conventional DLL arises when the duty cycle of the input clock is not 50% as the DLL is unable to set the duty cycle of the output clock other than 50%. Although proper sizing of the delay chain and other logic blocks in the clock path can preserve the duty cycle, yet the process variations would cause disturbance in the duty cycle. Further the sizing of the same may have to be varied for different process. This acts as a limitation to the use of DLL/PLL.
Hence, there is a need for DLLs/PLLs that provide duty cycle locking for input clocks having duty cycle other than 50% Additionally, there is also a need for a DLLs/PLLs whose duty cycle is process independent.
Object and Summary of the Invention
To obviate the drawbacks of the prior art, the object of the instant invention is to provide digital DLLs/PLLs with duty cycle locking mechanism for input clocks with varying duty cycles.
Additionally, the instant invention provides for a process independent DLLs/PLLs whose duty cycle does not change with the semiconductor technology process.
To achieve the aforesaid objects the instant invention provides an apparatus for enabling duty cycle locking at the rising / falling edge of the clock comprising:
a delay locked loop for clock synchronization;
an edge locking block connected to said delay locked loop for locking the
duty cycle at the edge of the clock, and
a clocktree delay connected to said edge locking block being fed back to
said delay locked loop

Said edge locking block comprising:
a counter receiving a gated input clock;
a lock detector receiving an input clock for generating control signals;
an address decoder connected to said counter for generating set of
selection signals;
a first multiplexer having its select lines connected to said selection
signals;
plurality of delay chains providing multiple output taps with first delay
chain connected to said first multiplexer;
a second multiplexer connected to one of said plurality of delay chains
with its select lines being hard wired; and
a latch connected to the output of said first multiplexer and said second
multiplexer for providing the output.
The middle tap of the second delay chain is selected.
A logic gate is connected to the output of said first multiplexer for negative edge locking.
Said logic gate is an inverter.
The output of said apparatus is feedback to said DLL / PLL through a clocktree delay.
A method for enabling duty cycle locking at the rising/falling edge comprising the steps
of.
synchronizing the external clock with the internal clock;
adjusting the unsynchronized edge of the external clock with the
corresponding internal clock edge for duty cycle locking; and
feeding back the adjusted clock until duty cycle locking.
The duty cycle locking comprising the steps of
generating control signals for duty cycle locking;
counting the clock cycles of gated input clock based on said control
signals
selecting a first delayed signal using first multiplexer depending upon the
counter value;
selecting a second delayed signal corresponding to the middle tap of the
second delay chain; and
setting the latch by said second delayed signal and resetting the latch by
said first delayed signal.
The instant invention uses a Edge Locking block for duty cycle locking as the negative edge of the external clock is continuously compared with the negative edge of the DLL output Appropriate changes are made to the duration of DLL output clock based on the comparison of the external clock and the DLL output The DLL apparatus is process independent as duty cycle locking is achieved using duty cycle locking mechanism, which is independent of semiconductor technology used.
Brief Description for the Accompanying Drawings
The invention will now be described with reference to the accompanying drawings.
Fig 1 shows the setup used in prior art DLLs.
Fig 2 illustrates the waveform of conventional DLLs
Fig 3 shows the DLL setup for duty cycle locking in accordance with the invention.
Fig 4 shows the circuit diagram of Negative Edge Locking block for Duty cycle locking in accordance with the invention.
Fig 5 shows the waveforms for the Lock Detector in accordance with the invention.
Fig 6 shows the waveforms describing duty cycle locking process in accordance with the invention.
Detailed Description of the Invention
The present invention relates to an improved DLL/PLL with a variable duty cycle locking mechanism. The instant invention is process independent and works for input clocks with duty cycles other than 50%. Due to the current trend of using digital DLLs in many applications, the described embodiment describes the invention in relation to a digital DLL. However the same architecture may be applied with other types of DLLs or even PLLs
Figure 3 describes the block diagram of the instant invention. The figure discloses a conventional DLL/PLL block 1 connected to an Edge Locking block 2. CLKTREE delay 3 is the internal delay of the DLL/PLL feedback path or the associated path and is illustrated in the figure to communicate the same. When compared with Figure 1, the modified architecture illustrated herein has an additional Edge Locking Block 3 in the feedback path for duty cycle locking. A modified structure of present invention may be used with rising Edge Locking Block where the conventional DLL/PLL performs edge locking for falling edge. The current invention covers all such embodiments of the modified DLL/PLL architecture,
The operation of Edge Locking Block 2 is initiated after the DLL/PLL 1 has performed the operation of edge detection and locking for one of the edges using the LOCK signal generated by the DLL/PLL 1. Basically Edge Locking Block 2 is initiated when the LOCK signal generated by the DLL/PLL 1 goes logic high and is received on the enable pin of the Edge Locking Block 2. After the Edge Locking Block 2 is enabled, the OUTCLK 15, the external clock 11 and the internal clock 12 are fed to the Edge Locking Block 2 The duty cycle of the internal clock 12 with clock tree delay, which is the DLL/PLL output 15 on feedback path, is increased or decreased based on comparison of the non matching edges of the internal clock 12 and the external clock 11. In the present embodiment, the negative edges of the internal and external clock are compared and the
duration of the high in the internal clock (duty cycle) is accordingly increased or decreased based on whether the falling edge of the internal clock is to the left or right of the external clock. The OUTCLK 15 is fed back to the DLL/PLL 1 through the Edge Locking Block 2 without any changes when LOCK signal is low.
Figure 4 describes the Edge Locking Block 2 that comprises of a Lock Detector 28, a counter 21 connected to an address decoder 22, which in turn is connected to the select lines of multiplexer 24. The digital delay chain 23 receives the clock output of the DLL 1 and is connected to the multiplexer 24. The second digital delay chain 25 also receives the clock output of the DLL 1 and is connected to the multiplexer 26. A Flip Flop 27 receives the output of multiplexers 24 & 26 at its reset and set inputs respectively.
The operation of the Edge Detection block 2 is dependent on three internally generated control signals namely, LS 110 for left shift, LK 111 for Lock and RS 112 for right shift. The Lock Detector 28 is used for negative edge locking by using inverted internal clock signal 11 and inverted external clock signal 11 as inputs. The three control signals are generated based on the locking window around the negative edge of external clock 11. LS 110 signal is high only when the negative edge of internal clock is to the right of the window and RS 112 signal is high only when the negative edge of internal clock is to the left of the window. Similarly, the LK 111 signal is high only when the negative edge of the internal clock is within the window. Hence only one of the three control signals is high at any stage of the operation. These signals are used in other blocks for generating a modified output 16, which has the same duty cycle as the external clock 12.
The Edge Locking Block 2 also has an enabling logic, which receives the internal clock 12, inverted internal Lock control signal LK 111, and the LOCK signal from the DLL/PLL. At initialization, the middle tap of the identical delay chains 23 and 25 is selected using the multiplexers 24 and 26. The signal 109 is hard wired to select the middle tap permanently and generate a delayed version of signal 15. This is used to provide uniformity in secondary effects due to presence of delay chain 23 and multiplexer 24 The counter 21 receives the internal clock signal 11 when LOCK signal

from DLL/PLL 1 is high and while the Lock condition is not achieved for negative edge locking. The counter 21 counts up or down based on the control signals RS 110 and LS 112 and generates a set of inputs 105 for the address decoder 22. The address decoder 22 generates a set of selection signals 114 for the multiplexer 24, which accordingly selects from amongst the delayed versions of the DLL output 15 to generate signal 107. Hence by delaying the DLL/PLL output 15 till negative edge locking is achieved, the signal 107 is attained whose negative edge matches with the negative edge of the external clock signal 11. The signal 108 is fed to the set pin of the flip-flop 27 and the inverted signal 107 is fed to the reset pin.
Since signal 108 is fed to the set pin of the flip flop 27, the output 16 goes high on the rising edge of the unmodified delayed version 108 of the DLL/PLL output 15. Hence its rising edge matches with that of the external clock signal 11. The signal 16 remains high until the inverted signal 107 used as a reset signal for the flip flop goes high. Hence the signal 16 is reset to low on the falling edge of signal 107. As mentioned above, the falling edge of signal 107 is matched with the falling edge of external clock 11 and hence, the output 16 is reset at the negative edge of the external clock 11. As a result, the duty cycle of the signal 16 is same as that of the external clock signal 11.
Figure 5.1 shows the window formed around the falling edge of external clock FBCLK. As shown in Figure 5.2, when the falling edge of RCLK is towards the right of the window, the Lock Detector generates logic high at LS and logic low at LK & RS Similarly as shown in Figure 5.3, when the falling edge of RCLK is towards the left of the window, the Lock Detector generates logic low at LS & LK and logic high at RS. As shown in Figure 5.4, when the falling edge of RCLK falls in line with window, the Lock Detector generates logic low at LS & RS and logic high at LK.
Figure 6 1 illustrates the case when output of clocktree 12 has less duty cycle as compared to the external clock 11. In this case, the falling edge of clocktree 12 is towards the left of the window around the falling edge of 11. The Lock Detector 28 generates RS
high and LS & LK low. At the rising edge of 11, the counter gets incremented. As a result, next TAP is selected from the delay chain 23.
Similarly figure 6.2 shows the case where clocktree output 12 has higher duty cycle as compared to the external clock 11. The falling edge of 12 is towards the right of the window around the input clock 11. The Lock Detector 28 generates LS high and LK & RS low. Hence, at the rising edge of the clock 11, the counter gets decremented and a previous TAP is selected from the delay chain 23.
In figure 6.3, falling edge of 12 is inside the window around 11. The Lock Detector generates LK high and LS & RS low. So the clock to the counter '21' is disabled and the counter keeps the current value.
Hence, the present invention provides a technique and for duty cycle locking where both rising and falling edges are locked to the external clock. Hence there is no duty cycle distortion in the instant invention. The technique is fully digital and process independent as same duty cycle locking mechanism can be used in different semiconductor technologies.
A simulation of the present invention at 90nm process at Slowest corner and highest frequency (400MHz) shows that if we use the DLL without using the duty cycle technique, then the duty cycle variation is 700ps to 900ps (excluding the duty cycle disturbance in Clock tree). Whereas if we use the duty cycle locking technique and use 60ps locking window, then the maximum duty cycle disturbance will be the size of the window i.e. 60ps.

We claim:
1. An apparatus for enabling duty cycle locking at the rising / falling edge of the
clock comprising:
a delay locked loop for clock synchronization;
an edge locking block connected to said delay locked loop for locking the
duty cycle at the edge of the clock; and
a clocktree delay connected to said edge locking block being fed back to
said delay locked loop.
2. An apparatus for enabling duty cycle locking at the rising / falling edge of the
clock as claimed in claim 1 wherein said edge locking block comprises:
a counter receiving a gated input clock,
a lock detector receiving an input clock for generating control signals;
an address decoder connected to said counter for generating set of
selection signals,
a first multiplexer having its select lines connected to said selection
signals,
plurality of delay chains providing multiple output taps with first delay
chain connected to said first multiplexer,
a second multiplexer connected to one of said plurality of delay chains
with its select lines being hard wired; and
a latch connected to the output of said first multiplexer and said second
multiplexer for providing the output.
3. An apparatus for enabling duty cycle locking at the rising / falling edge of the clock as claimed in claim 2 wherein the middle tap of the second delay chain is selected.
4. An apparatus for enabling duty cycle locking at the rising / falling edge of the
clock as claimed in claim 2 wherein a logic gate is connected to the output of said
first multiplexer for negative edge locking.
5. An apparatus for enabling duty cycle locking at the rising / falling edge of the
clock as claimed in claim 4, wherein said logic gate is an inverter.
6. A method for enabling duty cycle locking at the rising/falling edge comprising the
steps of:
synchronizing the external clock with the internal clock;
adjusting the unsynchronized edge of the external clock with the
corresponding internal clock edge for duty cycle locking; and
feeding back the adjusted clock until duty cycle locking
7. A method for enabling duty cycle locking at the rising/falling edge as claimed in
claim 6 wherein duty cycle locking comprising the steps of
generating control signals for duty cycle locking;
counting the clock cycles of gated input clock based on said control
signals;
selecting a first delayed signal using first multiplexer depending upon the
counter value;
selecting a second delayed signal corresponding to the middle tap of the
second delay chain; and
setting the latch by said second delayed signal and resetting the latch by
said first delayed signal.
8. An apparatus for enabling duty cycle locking at the rising / falling edge of the
clock substantially as herein described with reference to the accompanying
drawings
9 A method for enabling duty cycle locking at the rising/falling edge substantially as herein described with reference to the accompanying drawings .